JP4540827B2 - Driver circuit and signal transmission system - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a signal transmission technique for performing high-speed signal transmission between a plurality of LSI chips or between a plurality of elements and circuit blocks in one chip, or between a plurality of boards or a plurality of enclosures. In particular, the present invention relates to a driver circuit and a signal transmission system for performing bidirectional signal transmission.
[0002]
In recent years, the performance of components constituting computers and other information processing devices has been greatly improved. For example, the performance improvement of semiconductor storage devices such as DRAM (Dynamic Random Access Memory) and processors is remarkable. As the performance of the semiconductor memory device, processor, etc. is improved, the performance of the system cannot be improved unless the signal transmission speed between components or elements is improved. Specifically, for example, a signal transmission speed between a main storage device such as a DRAM and a processor (between LSIs) is becoming an obstacle to improving the performance of the entire computer. Furthermore, not only signal transmission between the chassis and the board (printed wiring board) such as between the server and the main storage device or the server via the network, but also high integration and enlargement of the semiconductor chip and low power supply voltage. Due to (lowering of signal amplitude level) and the like, it is necessary to improve the signal transmission speed in signal transmission between chips and signal transmission between elements and circuit blocks in the chip. Therefore, a driver circuit having a linear output impedance suitable for bidirectional transmission or multilevel transmission, which can increase the use efficiency of the signal transmission path or obtain an equivalent signal transmission speed with a smaller number of signal lines. There is also a need to provide a signal transmission system.
[0003]
[Prior art]
In recent years, it is necessary to increase the signal transmission speed per pin in order to cope with an increase in the amount of data transmission between LSIs and boards or between enclosures. This is also to avoid an increase in the cost of the package and the like due to an increase in the number of pins. As a result, recently, the signal transmission speed between LSIs exceeds 1 Gbps, and in the future (about 3 to 8 years ahead), it is expected to become extremely high values (high-speed signal transmission) such as 4 Gbps or 10 Gbps. Yes.
[0004]
At such a high signal frequency, the signal transmission path causes a loss due to the skin effect on the high signal frequency, and the high-frequency component is reflected due to the influence of the parasitic inductor and parasitic capacitance. The bandwidth is limited. These restrictions can be relaxed, for example, by using a cable with a thick core, but if it is necessary to bundle a large number of signal lines in parallel for large-capacity data transmission, the thickness of the cable bundle is also limited. There is. Thus, when the transmission frequency increases, the transmission path itself becomes a bottleneck for signal transmission.
[0005]
In high-speed signal transmission, the signal waveform is disturbed due to signal reflection at unmatched line ends, so that the end of the signal line is matched (matched) to the characteristic impedance of the line. This impedance matching is required not only at the receiving end of the signal line but also at the transmitting end. This is because reflection from an impedance mismatch point such as a connector or a package is also absorbed at the transmission end.
[0006]
By the way, as a method for reducing the number of signal lines, bidirectional transmission technology and multi-value transmission in which a plurality of bits are transmitted with one symbol are known. However, in these methods, the value of the line termination is only matched to the line impedance. In addition, it is necessary that the nonlinearity is small. This is because in bidirectional transmission, if the contribution from the driver circuit of its own is subtracted from the received signal, an error occurs if there is nonlinearity, and the number of bits per symbol is limited by nonlinearity even in multilevel transmission. .
[0007]
[Problems to be solved by the invention]
FIG. 1 is a diagram for explaining an example of a conventional driver circuit. FIG. 1A shows an inverter as an example of a driver circuit, and FIG. 1B shows an ON state of a p-channel MOS (pMOS) transistor. FIG. 1C shows a case where an n-channel MOS (nMOS) transistor is turned on. In FIG. 1A, reference numeral 100 denotes a driver circuit (CMOS inverter), 101 denotes a pMOS transistor, and 102 denotes an nMOS transistor.
[0008]
As a conventional signal driver (driver circuit 100), for example, as shown in FIG. 1A, a push-pull inverter type is widely used. The impedance of the inverter type driver circuit 100 increases as the drain-source voltage of the output transistors 101 and 102 increases because the IV characteristic of the transistor is a saturation characteristic.
[0009]
That is, as shown in FIGS. 1B and 1C, the currents (Iout, −Iout) flowing through the output transistors 101 and 102 change nonlinearly with respect to the terminal voltage (Vout). The characteristic deviates by several 10% from the straight line.
For this reason, when bidirectional signal transmission is performed using such a driver circuit 100, for example, an error of several tens of percent of the transmission output occurs due to the nonlinearity of the impedance, and particularly when the received signal is attenuated. In some cases, the received signal cannot be almost discriminated.
[0010]
SUMMARY OF THE INVENTION The present invention has been made in view of the above-described problems in the conventional signal transmission technology, and it is an object of the present invention to enable bidirectional transmission or multilevel transmission in which the bandwidth of a transmission path can be effectively used by providing linearity to the impedance of a driver circuit. To do.
[0011]
[Means for Solving the Problems]
A first form of the present invention is a driver circuit including a first transistor, a second transistor, and a control circuit. The first transistor includes a first terminal connected to an output signal line, a first transistor A second terminal connected to the power supply line and a control terminal, and the second transistor has a first terminal connected in parallel with the first transistor, a second terminal and a control terminal . The control circuit controls the voltage applied to the control terminal of the second transistor in accordance with the potential of the output signal line.
[0012]
  The second aspect of the present invention includes a first transistor and a control circuit, and the first transistor includes a first terminal connected to the output signal line and a second terminal connected to the first power supply line. The control circuit controls the voltage applied to the control terminal of the first transistor in accordance with the potential of the output signal line and the control signal.The control circuit includes a resistive device that connects the output signal line and the control terminal of the first transistor, and resistive device control means that controls the resistance of the resistive device with a voltage.
  Furthermore, according to the present invention, there is provided a signal transmission system in which the driver circuit is arranged at both ends of a signal transmission path, and bidirectional signal transmission is performed so that each driver circuit also serves as a reception termination of the other party's signal. The
[0013]
FIG. 2 is a diagram showing the principle configuration of the driver circuit according to the first embodiment of the present invention. 2A shows the current (drain current) Id flowing through the transistor Tr when the drain voltage is Vd, the source voltage is Vs, and the gate voltage is Vg, and FIG. 2B shows the source voltage Vs. FIG. 2C shows the current I1 flowing through the transistor Tr1 when the gate voltage Vg is constant at 0 V. FIG. 2C shows the shifter SFT with the source voltage Vs at 0 V and the gate voltage Vg from the drain voltage Vd by a predetermined voltage (Vth). The current I2 flowing through the transistor Tr2 when the voltage shifted by is shown. 2D shows the current I1 in FIG. 2B, the current I2 in FIG. 2C, and a combination of these currents I1 and I2 (I1 + I2).
[0014]
  The driver circuit according to the first aspect of the present invention connects the first transistor Tr1 and the second transistor Tr2 in parallel, and cancels the saturation characteristics of the first transistor Tr1 with the current flowing through the second transistor. Thus, an output impedance with high linearity is obtained.
  Here, the characteristics of the first transistor Tr1 and the second transistor Tr2 are the same, and the analysis in the case of the following square characteristics is shown below. In addition, pull using nMOS transistordownThe case of the device will be explained.upThe same analysis holds for devices.
[0015]
First, transistor characteristics are:
Id = β [(Vg−Vth−Vs) · (Vd−Vs) − (Vd−Vs)²/ 2]
Given in. Here, reference symbols Vd, Vs, and Vg indicate a drain potential, a source potential, and a gate potential, respectively, and Vth indicates a threshold voltage. Note that because of the pull-down, the source potential Vs is 0 volt (Vs = 0).
[0016]
When the gate potential Vg of the transistor is constant (Vg = const), the conductance Gd of the drain is given by δI / δVd,
Gd = β [Vg−Vth−Vd]
It becomes. Reflecting that the current-voltage characteristic is convex upward, the conductance Gd decreases with Vd.
[0017]
Next, when the gate potential Vg of the transistor is Vg = Vth + Vd, that is, when the gate voltage is changed depending on the output voltage Vd of the driver circuit, the drain conductance substitutes Vg = Vth + Vd into the current equation. Then, by differentiating with Vd,
Gd ′ = β [Vd−Vs] = βVd
It becomes. In other words, since the current-voltage characteristic is convex downward, the conductance increases with the output voltage Vd of the driver circuit.
[0018]
Therefore, when these two transistors are connected in parallel, the total conductance is the sum of Gd and Gd ',
Gd + Gd ′ = β [Vg−Vth]
It becomes. Here, Vg is a gate voltage of an element having a constant gate voltage.
As described above, the dependence of the conductance on the drain voltage Vd (signal voltage: the output voltage of the driver circuit) can be eliminated by connecting the two transistors (first and second transistors) in parallel.
[0019]
According to the present invention, the saturation characteristic of a transistor can be compensated by the downward current-voltage characteristic of a parallel element, and an internal impedance having excellent linearity with respect to voltage can be realized. In other words, the nonlinearity of the transistor current-voltage characteristics can be compensated to realize an internal impedance with excellent linearity. By making this internal impedance a load device of the driver circuit, the voltage dependence of the output impedance can be realized. A small driver circuit can be realized.
[0020]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of a driver circuit and a signal transmission system according to the present invention will be described in detail with reference to the accompanying drawings.
FIG. 3 is a circuit diagram showing a first embodiment of the driver circuit of the present invention. In FIG. 3, reference numerals 1 and 2 are pMOS transistors, 3 is a gate voltage generation circuit (voltage shift circuit), 4 is an output signal line, and 5 and 6 are nMOS transistors.
[0021]
As shown in FIG. 3, in the driver circuit of the first embodiment, the first transistor 1 has a source connected to the high potential power supply line Vdd, a drain connected to the output signal line 4, and a gate connected to the output signal line 4. It is connected to the low potential power line Vss. The second transistor 2 is connected in parallel with the first transistor 1, and the output of the gate voltage generation circuit 3 is applied to the gate of the second transistor 2. The drains of the transistors 1 and 2 are connected in common and connected to the output signal line 4 and also connected to the drain of the transistor 5, and the source of the transistor 5 is passed through the transistor 6 whose bias voltage Vcn is applied to the gate. It is connected to the low potential power line Vss. Here, an input signal (IN) is supplied to the gate of the transistor 5.
[0022]
The gate voltage generation circuit 3 controls the gate voltage of the transistor 2 and is configured to include pMOS transistors 31 and 32 and nMOS transistors 33, 34 and 35, and shifts the voltage of the output signal line 4 to form a transistor. 2 to the gate.
That is, in the driver circuit of the first embodiment, the gate voltage generating circuit 3 receives the voltage of the signal line 4 by a buffer having a gain of 1, and drives the gate of the transistor 2 with the output voltage. In the first embodiment, a current supplied from a constant current driver composed of nMOS transistors 5 and 6 is applied to a pMOS load (transistors 1 and 2) to generate an output voltage. Here, since the gate voltage of the transistor 2 changes with the signal voltage, the current-voltage characteristic of the transistor 2 becomes a downwardly convex curve that compensates for the saturation characteristic of the transistor 1, and as a result, the load device (transistor 1 and transistor 1 and The impedance of the second parallel element) is less dependent on the voltage and exhibits good linearity.
[0023]
FIG. 4 is a circuit diagram showing a second embodiment of the driver circuit of the present invention.
The difference between the second embodiment and the first embodiment is that the load devices 112, 113 and 114, 115 are in series with the output of the voltage mode driver instead of the constant current driver. Reference numerals 117 and 118 respectively denote a gain 1 buffer (gate voltage generation circuit).
[0024]
As shown in FIG. 4, the load devices are pMOS transistors 112 and 113 and nMOS transistors 114 and 115, and a voltage depending on the signal line voltage (OUT) is applied to the gates of the transistors 113 and 115. ing.
In the second embodiment, the signal line voltage (IN) is applied as it is to the gates of the transistors 111 and 116. When the pMOS transistor 111 is on, the nMOS transistor 116 is turned off, and the pull-up load device ( All the load currents flowing through the transistors 112 and 113) are taken out of the driver circuit as signal currents. On the other hand, when the pMOS transistor 111 is off, the nMOS transistor 116 is turned on and the load device for pull-down (transistors 114 and 115) is obtained. All of the load current flowing through the circuit is taken out of the driver circuit as a signal current (all the signal current flows through the pull-down load device), and the current consumption is reduced (halved) compared to the first embodiment. Can do.
[0025]
FIG. 5 is a circuit diagram showing a third embodiment of the driver circuit of the present invention. In FIG. 5, reference numerals 201, 202; 301, 302 are load devices formed of pMOS transistors, 203, 303 are nMOS differential pair transistors, 200 is a current limiting transistor (nMOS bias transistor), and 206 and 306. Indicates a buffer (gate voltage generating circuit).
[0026]
As shown in FIG. 5, in the third embodiment, the current driver is configured as an nMOS differential pair, and the current is applied to the pMOS load devices 201, 202 and 301, 302. In the third embodiment, since the drain voltage of the current limiting transistor 200 that generates a constant current by the constant current driver is held almost constant, the switching time is shortened and the removal characteristic for the input common mode voltage is improved. There is an advantage that noise resistance is increased.
[0027]
FIG. 6 is a circuit diagram showing a fourth embodiment of the driver circuit of the present invention.
The overall configuration of the fourth embodiment is the same as that of the first embodiment shown in FIG. 3, and the configuration of the gate voltage generation circuit (voltage shift circuit) 30 is different. That is, the gate voltage generation circuit 30 in the fourth embodiment is not a mere gain 1 buffer, but outputs a voltage (Vo) shifted by a fixed value from the input voltage (Vi).
[0028]
The gate voltage generation circuit 30 is realized by a voltage shift circuit having nMOS transistor differential pairs 37 and 38 as inputs, and the voltage shift amount is equal to the threshold voltage (Vth) of the pMOS transistor 36. Bias voltages Vcp and Vcn are applied to the gates of the pMOS transistor 36 and the nMOS transistor 39, respectively.
[0029]
  That is, assuming that the current flowing through the transistor 38 is I31 and the current flowing through the transistor 36 (37) is I32, a current of I31 + I32 flows through the transistor 39. Here, when the voltage of the connection node between the transistors 37 and 38 and the transistor 39 is Vs, the currents I31 and I32 are I31 = β (Vi−Vs−Vth).², I32 = β (Vo−Vs−Vth)²And Vi = (I31 / β)^1/2+ Vs + Vth, Vo (I32 / β)^1/2+ Vs + Vth. Therefore, Vi-Vo = (I31 / β)^1/2-(I32 / β)^1/2It becomes. By selecting the voltage shift amount in this way, the load device (transistor1and2The linearity of the impedance of the parallel element) can be further improved.
[0030]
FIG. 7 is a circuit diagram showing a fifth embodiment of the driver circuit of the present invention.
As shown in FIG. 7, the fifth embodiment includes a pMOS transistor 81 having a gate voltage generation circuit connected to a diode and a constant current source 82 for supplying a current thereto. Thereby, in the fifth embodiment, the generated voltage shift amount becomes the threshold voltage of the pMOS transistor 81 and matches the threshold voltage of the load device (pMOS transistors 1 and 2). Even if the voltage changes, a voltage (gate voltage of the transistor 2) that compensates for it is generated. As a result, there is an advantage that even if the semiconductor manufacturing process fluctuates, the linearity of the load device is not affected.
[0031]
FIG. 8 is a circuit diagram showing a sixth embodiment of the driver circuit according to the present invention.
As shown in FIG. 8, the sixth embodiment is similar to the second embodiment shown in FIG. 4 in that a pull-up load device (pMOS transistors 11 and 12) and a pull-down load device (nMOS transistor 21). And 22), and a voltage depending on the signal line voltage (OUT) is applied to the gates of the transistors 12 and 22. An input signal is applied to the gates of the transistors 11 and 21 to drive them directly from the previous stage, but the gates of the transistors 12 and 22 need to change depending on the signal voltage when each load device is on. Switching transistors (51, 52) are provided between the gate voltage generation circuit (61, 62) and the gate.
[0032]
When the input signal (IN) is at the low level “L”, the pull-up load 11 is turned on and the pull-down load 21 is turned off. At this time, the pull to which the high level “H” voltage is applied via the inverter 71 The up transistor 41 is off and the pull down transistor 42 is on. Furthermore, the gate transistor 51 to which the low level “L” voltage is applied via the inverters 71 and 72 is turned on, and the gate transistor 52 is turned off. Therefore, the output of the buffer 61 is supplied to the gate of the pull-up load 12, the impedance of the load device (parallel element of the transistors 11 and 12) exhibits a good linearity, and the load device (transistors 11, 12). The current consumption can be reduced by taking out all of the load current flowing through the driver circuit as a signal current from the driver circuit.
[0033]
When the input signal (IN) is at a high level “H”, the pull-up load 11 is turned off and the pull-down load 21 is turned on. Further, the pull-up transistor 41 is turned on and the pull-down transistor 42 is turned off. . Then, the gate transistor 51 is turned off, the gate transistor 52 is turned on, and the output of the buffer 62 is supplied to the gate of the pull-down load 22, so that the impedance of the load device (parallel element of the transistors 21 and 22) has a good linearity. Furthermore, it is possible to reduce current consumption by taking out all of the load current flowing through the load device (transistors 21 and 22) as a signal current out of the driver circuit (flowing all of the signal current to the load device). .
[0034]
As described above, the sixth embodiment eliminates the need for large switching transistors (transistors 111 and 116 in FIG. 4) for turning on / off the load device itself as in the second embodiment. There is an advantage that the power consumption of the pre-driver for driving can be reduced.
FIG. 9 is a circuit diagram showing a seventh embodiment of the driver circuit according to the present invention. In FIG. 9, reference numerals 211 and 212 are load devices (nMOS transistors), 213 is a switch (nMOS transistor), 214 is a current source (pMOS transistor), 215 is a resistor, and 216 is a gate voltage generation circuit (shifter). Show.
[0035]
  As shown in FIG.7In the embodiment, in order to shorten the switching time when the load device (transistor 211) transitions from off to on, a current injection mechanism for transiently speeding up the change of the gate voltage is provided. The current injection mechanism used here is based on capacitive coupling, and is coupled by a capacitor 217 from the gate of the transistor (load device) 211 to the gate of the transistor 213.
[0036]
Due to this capacitive coupling, when the gate voltage of the transistor 211 transitions from the low level “L” to the high level “H” (ie, when the load device changes from off to on), the gate voltage of the transistor (load device) 212 Is temporarily driven to the high level side to increase the transition speed. Similarly, when the load device (211) transitions from on to off, the transition speed is similarly increased by capacitive coupling.
[0037]
FIG. 10 is a circuit diagram showing an eighth embodiment of the driver circuit of the present invention.
As is apparent from FIG. 10, in the eighth embodiment, the load devices 221, 222 and 223, 224 and the portions (transistors 225 to 227) that generate the shift voltage in the gate voltage generation circuit of the load device are all the same. Channel conductive transistors (here, nMOS transistors).
[0038]
As described above, in the eighth embodiment, the load device and the shift voltage generating transistor are configured by the same conductive transistor (nMOS transistor), so that the transistors that determine the non-linearity have the same conductivity. Even if it fluctuates, it has the advantage that the linearity is not easily affected. Further, the use of the nMOS transistor has an advantage that the driving transistor can be made smaller than the case where the pMOS transistor is used.
[0039]
FIG. 11 is a circuit diagram showing a ninth embodiment of the driver circuit according to the present invention.
As shown in FIG. 11, the present invention is applied to a signal transmission system in which two sets of driver circuits 231 and 232 are connected to face each other and their outputs are the other end. That is, the driver circuit of the present invention can be applied to a bidirectional signal transmission system that transmits signals bidirectionally with one signal line. Since the output impedance of the driver circuit has a linearity independent of voltage, the driver circuit Impedance matching can be performed without depending on the output state of the circuit and the magnitude of the input voltage, and signal transmission with a small non-linear error becomes possible.
[0040]
As described above, according to the first aspect of the present invention, bidirectional signal transmission or multi-value can be obtained by increasing the use efficiency of the signal transmission path and obtaining an equivalent signal transmission speed with a smaller number of signal lines. It becomes possible to provide a driver circuit and a signal transmission system excellent in linearity of output impedance for transmission.
FIG. 12 is a diagram showing a principle configuration of a driver circuit according to the second embodiment of the present invention. Here, an nMOS transistor will be described as an example, but the same applies to a pMOS transistor or another transistor other than a MOS transistor.
[0041]
As shown in FIG. 12A, the gate voltage (gate-source voltage) of the nMOS transistor 400 is Vgs, the drain voltage (drain-source voltage) is Vds, and the current flowing through this transistor is Id. . Note that the threshold voltage of the transistor is indicated by Vth.
As shown in FIGS. 12B and 12C, the driver circuit according to the second embodiment of the present invention uses the gate voltage of the output transistor in the driver circuit to obtain an output impedance with high linearity. Control is performed depending on both the control signal CS and the driver output voltage (potential of the output signal line) Vout. Here, FIG. 12B shows a state in which the nMOS transistor 401 is used as a pull-up element, and FIG. 12C shows a state in which the nMOS transistor 412 is used as a pull-down element.
[0042]
  An analysis in the case where the output stage transistor of the driver circuit has the following square characteristics is shown below. The following equation is used for the analysis.
Id = β ((Vgs−Vth) Vds− (1/2) Vds²)) ... Vgs> Vds + Vth (1a)
    = (Β / 2) (Vgs-Vth)²... Vgs <Vds + Vth (1b)
  First, in the case of the pull-up nMOS transistor 401 as shown in FIG. 12B, the drain voltage is constant (Vd = Vr), and the output current Iout = Id is extracted from the source side. Since Vds is Vd−Vs and Vs = Vout (output voltage),
Vg = (Vout + VgO) / 2 + Vth + Vr / 2 VgO> Vr-Vout (2a)
    = SQRT (VgO * (Vr-Vs))VgO <Vr-Vout (2b)
Iout = (β / 2) VgO * (Vr−Vout) (2c)
It becomes. Therefore, when the gate voltage generation circuit 403 applies the gate voltage Vg as described above to the gate of the transistor 401, linear characteristics can be obtained.
[0043]
Next, in the case of the pull-down nMOS transistor 411 as shown in FIG. 12C, if Vds = Vout and Vgs = Vg,
Vg = (Vout + VgO) / 2 + Vth VgO> Vout (3a)
= SQRT (VgO * Vout) VgO <Vout (3b)
Iout = (β / 2) VgO * Vout (3c)
It becomes. Therefore, when the gate voltage generation circuit 413 applies the gate voltage Vg as described above to the gate of the transistor 411, linear characteristics can be obtained.
[0044]
As described above, according to the driver circuit of the second embodiment of the present invention, it is possible to compensate for the non-linearity of the current-voltage characteristics of the transistor and to realize an internal impedance with excellent linearity. By using this internal impedance as a load device of the driver, it becomes possible to realize a driver circuit with a small voltage dependency of the output impedance.
[0045]
FIG. 13 is a circuit diagram showing a tenth embodiment of the driver circuit of the present invention. In FIG. 13, reference numerals 421 and 422 are pMOS transistors, 423 to 425 are nMOS transistors, and 426 and 427 are gate voltage generating circuits.
As shown in FIG. 13A, the gate voltage generation circuit 426 receives the control signal CS1 and a signal from the output node N41 of the driver circuit (the potential of the output signal line: the output voltage of the driver circuit), and receives the gate voltage Vg1. Is applied to the gate of the transistor 421. The gate voltage generation circuit 427 receives the control signal CS2 and a signal (output voltage of the driver circuit) from the output node N42 of the driver circuit, generates a gate voltage Vg2, and applies it to the gate of the transistor 422.
[0046]
Here, as shown in FIG. 13B, each gate voltage generation circuit 426 (427) receives the input control signal CS1 (CS2) and the output voltage of the driver circuit, and divides the resistance by resistors 428 and 429. Thus, the gate voltage Vg1 (Vg2) is generated. Transistors 423 and 424 constitute an nMOS differential pair, and a bias voltage Vcn is applied to the gate of the transistor 425.
[0047]
In the tenth embodiment, current supplied from a constant current driver composed of nMOS differential pairs 423 and 424 is applied to pMOS loads (pMOS transistors) 421 and 422 to generate output voltages (/ OUT, OUT). To do. Since the gate voltages of the pMOS transistors 421 and 422 change according to the signal voltage (IN, / IN), the impedance of the load device (421, 422) becomes less dependent on the voltage and exhibits good linearity.
[0048]
FIG. 14 is a circuit diagram showing an eleventh embodiment of the driver circuit according to the present invention. Reference numerals 431 and 432 denote nMOS transistors, and 433 and 434 denote gate voltage generating circuits.
As shown in FIG. 14, the driver circuit of the eleventh embodiment includes a pull-up nMOS transistor 431 connected to a high-potential power line Vdd and a pull-down nMOS transistor 432 connected to a low-potential power line Vss. It has.
[0049]
Here, one pull-up transistor 431 is turned off when the other pull-down transistor 432 is turned on, and turned on when the other pull-down transistor 432 is turned off. That is, in the eleventh embodiment, since either one of the load devices is always turned off, all of the load current is taken out of the driver as a signal current, and the current consumption is reduced (for example, half that of the tenth embodiment). )can do.
[0050]
FIG. 15 is a circuit diagram showing a twelfth embodiment of the driver circuit of the present invention. In FIG. 15, reference numeral 441 denotes a load, 442 denotes an nMOS transistor (control transistor), and 440 denotes a gate voltage generation circuit (control circuit).
The gate voltage generation circuit 440 includes gate voltage generation units 443 and 444. The gate voltage generation unit 443 includes switches 4431 and 4432 and resistors 4433 and 4434, and the gate voltage generation unit 444 includes switches 4441 and 4442 and resistors. 4443, 4444 are provided. Here, reference symbols Vc and / Vc indicate control voltages (control signals), and / Vc is obtained by inverting Vc. Each switch 4431, 4432; 4441, 4442 is constituted by, for example, a CMOS transfer gate.
[0051]
In the twelfth embodiment, the gate voltage generation circuit 440 determines the gate voltage (Vg) from the driver output voltage (OUT) and the control voltage by resistance division in the same manner as in the above embodiment, but the complementary control voltage The resistance division ratio is changed depending on whether the driver is on or off by a transistor switch (transfer gate) controlled by (Vc, / Vc).
[0052]
That is, when the control voltage Vc is at a high level “H” (control voltage / Vc is at a low level “L”), the switches 4431 and 4441 are turned off and the switches 4432 and 4442 are turned on, and the control voltage Vc and the output voltage ( OUT) is divided by resistors 4434 and 4444, and a voltage (Vg) is applied to the gate of the transistor 442. On the other hand, when control voltage Vc is at a low level “L” (control voltage / Vc is at a high level “H”), switches 4431 and 4441 are turned on, switches 4432 and 4442 are turned off, and resistors 4433 and 4443 are divided by resistors. The applied voltage (Vg) is applied to the gate of the transistor 442. Here, the divided voltage by the resistors 4434 and 4444 and the divided voltage ratio by the resistors 4433 and 4443 are set to predetermined different ratios, and not only the linearity of the impedance with respect to the output voltage (OUT) but also the control voltage (Vc, / Vc). ) To improve the linearity of the output impedance.
[0053]
Therefore, for example, the values of the resistors 4433, 4434; 4443, 4444 so that the output impedance when the control voltage Vc is the high-potential power supply voltage Vdd is Zo and the output impedance when the control voltage Vc is Vdd / 2 is 2Zo. Can be adjusted so that the output conductance of the driver is substantially proportional to the control voltage. The twelfth embodiment has an advantage that the output impedance of the push-pull driver can be kept substantially constant even during the transition period in which the driver output is changing.
[0054]
  FIG. 16 is a circuit diagram showing a thirteenth embodiment of the driver circuit according to the present invention, which is a modification of the twelfth embodiment described above. In FIG. 16, reference numeral 451 indicates a load, 452 indicates an nMOS transistor (control transistor), 450 indicates a gate voltage generation circuit (control circuit), and 4551 and 4552 indicate delay circuits.
  The gate voltage generation circuit 450 includes gate voltage generation units 453 and 454, and the gate voltage generation unit 453 includes switches 4531 to 4536 and a resistor 4.537-4539, and the gate voltage generator 454 includes switches 4541 to 4546 and resistors 4547 to 4549. As described above, each of the switches 4531 to 4536 and 4541 to 4546 is composed of, for example, a CMOS transfer gate.
[0055]
In the thirteenth embodiment, the resistance value of the voltage dividing circuit used for the gate voltage generating circuit 450 is switched to three values by switches (transfer gates) 4531 to 4536; 4541 to 4546. That is, each voltage dividing resistor is switched by a switch in which two transfer gates are connected in series, and each switch is controlled by control clocks φ1, φ2, φ3 (/ φ1, / φ2, / φ3) having different phases.
[0056]
Specifically, the first voltage dividing resistor group (resistors 4537 and 4547) is effective during the period when both of the control clocks φ1 and / φ2 are at the high level “H”, and the second voltage dividing resistor group (resistor 4538). And 4548) are effective during the period when both of the control clocks φ2 and / φ3 are at the high level “H”, and the third voltage dividing resistor pair (resistors 4539 and 4549) is high when both of the control clocks φ3 and / φ1 are high. Effective during the period when the level is “H”. Here, the control clocks (φ 1) φ 2 and φ 3 are sequentially generated by the delay circuits 4551 and 4552.
[0057]
According to the thirteenth embodiment, for example, the input / output characteristics of the control circuit for the three cases of when the driver circuit is on, when the conductance is half that when the driver circuit is on, and when the driver circuit is off are shown. Since it can be set, the output conductance of the driver circuit can be made almost linearly dependent on the control signal.
[0058]
FIG. 17 is a circuit diagram showing a fourteenth embodiment of the driver circuit according to the present invention.
The fourteenth embodiment is generally the same as the twelfth and thirteenth embodiments described above, but the gate voltage generation circuit 460 includes a plurality of diode-connected transistors and resistors (4611, 4612; 4621, 4622). ; 4631, 4632), which is a so-called broken line approximation circuit. Reference numeral 463 is a pMOS transistor to which a control signal is input, and 464 is one resistance serving as a reference for resistance division.
[0059]
The broken line approximating circuit shows the characteristics of a broken line having a plurality of bent points by changing the division ratio of the voltage dividing circuit every time the output voltage exceeds the reference voltage value. The broken line approximating circuit of the fourteenth embodiment shown in FIG. In this case, the ideal input / output characteristic can be approximated by a straight line having three bending points. Of course, the number of diode-connected transistors and resistors is not limited to three. In practice, since the diode characteristics are not steep, a curve is obtained instead of a broken line, which is closer to the ideal characteristics.
[0060]
FIG. 18 is a circuit diagram showing a fifteenth embodiment of the driver circuit according to the present invention.
In the fifteenth embodiment, capacitors (4711, 4721) are provided in parallel to the resistance elements (4712, 4722) of the resistor divider circuit in the twelfth embodiment. Here, the values of the capacitors 4711 and 4721 are selected so that the gate voltage versus control voltage characteristic determined by the capacitance division has a conductance that is half that when the output impedance of the driver circuit is on.
[0061]
For example, when the control voltage is Vdd / 2, the output impedance of the driver circuit can be statically close to half of the on-state, but in reality, the control voltage changes transiently, resulting in an error. Occurs. Therefore, in the fifteenth embodiment, by introducing capacity division of the capacitors 4711 and 4721, the division ratio at a high frequency is determined by the capacitance, so that a transient error is reduced.
[0062]
FIG. 19 is a circuit diagram showing a sixteenth embodiment of the driver circuit according to the present invention.
In the sixteenth embodiment, an element that performs feedback from the output node (OUT) of the driver circuit to the gates of the transistors 481 and 482 is a transistor using the same carrier as the driver stage transistors (481 and 482) (in this embodiment, NMOS transistors) 485 and 486 are diode-connected, and pMOS transistors 483 and 484 to which control signals Vc and / Vc are inputted are used as load devices.
[0063]
According to the sixteenth embodiment, for example, if the threshold voltage Vth of the output stage transistors (481, 482) of the driver circuit is increased due to process variation or the like, the gate voltage is increased accordingly. It can be made less susceptible to fluctuations.
FIG. 20 is a circuit diagram showing a seventeenth embodiment of the driver circuit according to the present invention.
[0064]
As apparent from the comparison between FIGS. 20 and 19, the transistors 491 to 496 in the seventeenth embodiment correspond to the transistors 481 to 486 in the sixteenth embodiment. In the seventeenth embodiment, the pMOS load transistors 483 and 484 in the sixteenth embodiment are replaced with two pMOS transistors 4930, 493, 4940, and 494 connected in series, respectively, and the gates of the respective transistors 4930 and 4940 are used. A gate voltage is applied to keep the conductance constant.
[0065]
That is, the bias generation circuit 497 includes pMOS transistors 4971 and 4972, nMOS transistors 4972 and 4974, and a resistor (external reference resistor) 4975, and generates a gate bias voltage that provides a conductance proportional to the external reference resistor 4975. To do. According to the seventeenth embodiment, the process variation of the pMOS transistor can be compensated, so that the process dependency can be further reduced as compared with the sixteenth embodiment.
[0066]
FIG. 21 is a circuit diagram showing an eighteenth embodiment of the driver circuit according to the present invention.
As shown in FIG. 21, in the eighteenth embodiment, a control circuit (gate voltage generating circuit) 503 for driving a transistor 501 on the high potential side of the driver stage and a control circuit (for driving the transistor 502 on the low potential side) The gate voltage generation circuit 504 is asymmetrically configured according to the respective voltages. For example, the voltage Vdd is 1.8 volts, Vr is 0.9 volts, and Vss is 0 volts.
[0067]
First, the gate voltage generation circuit 503 includes pMOS transistors 531 to 533 and nMOS transistors 534 to 536, and has inverters (transistors 531 and 534) as pre-drivers. The output voltage (OUT) is fed back to the gate of the transistor 501 through the diode-connected transistor 536 as in the sixteenth embodiment shown in FIG. Here, the transistor 536 is configured as the same nMOS transistor as the output transistor 501 in order to be hardly affected by process variations.
[0068]
On the other hand, the gate voltage generation circuit 504 includes pMOS transistors 541 to 544 and nMOS transistors 545 to 549. Here, the nMOS transistor 549 and the pMOS transistor 543 are controlled to be switched by the control signals Vc and / Vc as in the twelfth embodiment of FIG. Note that these transistors 549 and 543 function not only as switching elements but also as resistance elements. As a result, the gate voltage of the transistor 502 is controlled in accordance with the levels of the control signals Vc and / Vc to improve the linearity of the output impedance.
[0069]
In the above description, a MOS (CMOS) transistor has been described as an example of a transistor, but the present invention is not limited to this.
(Supplementary note 1) a first transistor having a first terminal connected to the output signal line, a second terminal connected to the first power supply line, and a control terminal;
A second terminal having a first terminal and a second terminal and a control terminal connected in parallel with the first transistor;
And a control circuit that controls a voltage applied to a control terminal of the second transistor in accordance with a potential of the output signal line.
[0070]
(Supplementary note 2) The driver circuit according to supplementary note 1, wherein the first power supply line is a high-potential power supply line, and the first transistor pulls up the output signal line. circuit.
(Supplementary Note 3) The driver circuit according to Supplementary Note 1, wherein the first power supply line is a low-potential power supply line, and the first transistor pulls down the output signal line. .
[0071]
(Supplementary Note 4) In the driver circuit according to Supplementary Note 1, the control circuit applies a shift voltage obtained by approximately shifting the voltage of the output signal line by a constant value to a control terminal of the second transistor. A driver circuit characterized by the above.
(Supplementary Note 5) In the driver circuit according to Supplementary Note 4, the voltage shift circuit is configured to generate the shift voltage by passing a current through a voltage shift load device connected to the output signal line. Driver circuit characterized by.
[0072]
(Supplementary note 6) The driver circuit according to supplementary note 5, wherein the voltage shift load device and the first and second transistors have the same channel conductivity.
(Supplementary Note 7) In the driver circuit according to Supplementary Note 1, when the second transistor is switched from the off state to the on state, the voltage applied to the control terminal of the second transistor is changed from the off voltage to the on voltage. A driver circuit comprising a charge or current injection means for accelerating the change to the.
[0073]
(Supplementary Note 8) A first transistor connected to an output signal line, a second terminal connected to a high-potential power line, and a control terminal, and a first transistor that pulls up the output signal line;
A second terminal having a first terminal and a second terminal and a control terminal connected in parallel with the first transistor;
A first control circuit for controlling a voltage applied to a control terminal of the second transistor in accordance with a potential of the output signal line;
A third transistor having a first terminal connected to the output signal line, a second terminal connected to a low-potential power line and a control terminal, and pulling down the output signal line;
A fourth transistor having a first terminal and a second terminal and a control terminal connected in parallel with the third transistor;
And a second control circuit for controlling a voltage applied to a control terminal of the fourth transistor in accordance with the potential of the output signal line.
[0074]
(Supplementary note 9) In the driver circuit according to supplementary note 8, the driver circuit is a differential constant current driver circuit, and the third and fourth transistors connected in parallel with the first and second transistors connected in parallel. A driver circuit comprising a transistor as a load of the differential constant current driver circuit.
(Additional remark 10) In the driver circuit according to additional remark 8, the first control circuit has a first shift voltage obtained by shifting the voltage of the output signal line of the driver by an approximately constant value. A first shift voltage circuit applied to a control terminal, wherein the second control circuit generates a second shift voltage obtained by shifting the voltage of the output signal line of the driver by an approximately constant value; A driver circuit which is a second shift voltage circuit applied to a control terminal.
[0075]
(Supplementary note 11) In the driver circuit according to supplementary note 10, each of the first and second voltage shift circuits causes each of the first and second voltage shift circuits to flow by passing a current through a voltage shift load device connected to the output signal line. A driver circuit, wherein each of the second shift voltages is generated.
(Supplementary note 12) The driver circuit according to supplementary note 11, wherein the voltage shift load device and the first to fourth transistors have the same channel conductivity.
[0076]
(Supplementary note 13) In the driver circuit according to supplementary note 8, further, a first switch means provided between the first control circuit and a control terminal of the second transistor, and the second control circuit And a second switch means provided between the control terminal of the fourth transistor,
When one of the pull-up load device having the first and second transistors and the pull-down load device having the third and fourth transistors is turned on, the corresponding one of the first and second switch means A driver circuit characterized in that the switch means is turned on and the other switch means is turned off.
[0077]
(Supplementary note 14) The driver circuit according to supplementary note 13, further comprising pull-up means for pulling up the control terminal of the second transistor, and pull-down means for pulling down the control terminal of the fourth transistor,
The pull-up means pulls up the control terminal of the second transistor when the first switch means is turned off, and the pull-down means works when the second switch means is turned off. A driver circuit characterized by pulling down a control terminal of four transistors.
[0078]
(Supplementary note 15) a first transistor having a first terminal connected to the output signal line, a second terminal connected to the first power supply line, and a control terminal;
And a control circuit that controls a voltage applied to a control terminal of the first transistor in accordance with a potential of the output signal line and a control signal.
[0079]
(Supplementary note 16) The driver circuit according to supplementary note 15, wherein the first power supply line is a high-potential power supply line, and the first transistor pulls up the output signal line. circuit.
(Supplementary note 17) The driver circuit according to supplementary note 15, wherein the first power supply line is a low-potential power supply line, and the first transistor pulls down the output signal line. .
[0080]
(Supplementary note 18) In the driver circuit according to supplementary note 15, the control circuit controls a resistance device that connects the output signal line and a control terminal of the first transistor, and controls a resistance of the resistance device with a voltage. And a resistive device control means.
(Additional remark 19) The driver circuit of Additional remark 15 WHEREIN: The said control circuit is a circuit which combined the resistive element and the switch element, The driver circuit characterized by the above-mentioned.
[0081]
(Supplementary note 20) In the driver circuit according to supplementary note 19, the switch element is a transistor or a diode, and the output voltage of the control circuit is dependent on the potential of the output signal line and the control signal by a so-called broken line approximation circuit. A driver circuit obtained.
(Supplementary note 21) The driver circuit according to supplementary note 15, wherein the control circuit includes a capacitor that connects the output signal line and a control terminal of the first transistor.
[0082]
(Supplementary note 22) The driver circuit according to supplementary note 15, wherein the control circuit includes a diode-connected transistor that connects between the output signal line and a control terminal of the first transistor. circuit.
(Supplementary note 23) In the driver circuit according to supplementary note 15, a device that connects the output signal line and the control terminal of the first transistor has the same conductivity type as the first transistor, and the control circuit includes A circuit for supplying a bias current is controlled so as to have an impedance scaled to an impedance level of the first transistor.
[0083]
(Supplementary Note 24) A first transistor connected to an output signal line, a second terminal connected to a high-potential power supply line, and a control terminal, and a first transistor that pulls up the output signal line;
A first control circuit that controls a voltage applied to a control terminal of the first transistor in accordance with a potential of the output signal line and a first control signal;
A second transistor having a first terminal connected to the output signal line, a second terminal connected to a low-potential power line and a control terminal, and pulling down the output signal line;
A driver circuit comprising: a second control circuit that controls a voltage applied to a control terminal of the second transistor in accordance with a potential of the output signal line and a second control signal.
[0084]
(Supplementary Note 25) In the driver circuit according to Supplementary Note 24, each of the first and second control circuits is a resistive circuit that connects a control terminal of each of the first and second transistors corresponding to the output signal line. A driver circuit comprising: a device; and resistive device control means for controlling a resistance of the resistive device with a voltage.
(Additional remark 26) The driver circuit of Additional remark 24 WHEREIN: Each said 1st and 2nd control circuit is a circuit which combined the resistive element and the switch element, The driver circuit characterized by the above-mentioned.
[0085]
(Supplementary note 27) In the driver circuit according to supplementary note 26, the switch element is a transistor or a diode, and an output voltage of each of the first and second control circuits is a potential of the output signal line and each of the first and second control circuits. A driver circuit characterized in that the dependency on the second control signal is obtained by a so-called broken line approximation circuit.
[0086]
(Supplementary Note 28) In the driver circuit according to Supplementary Note 24, each of the first and second control circuits includes a capacitor that connects between the output signal line and a control terminal of the first transistor. A driver circuit.
(Supplementary note 29) In the driver circuit according to supplementary note 24, each of the first and second control circuits connects between the output signal line and a control terminal of each of the corresponding first and second transistors. A driver circuit comprising a diode-connected transistor.
[0087]
(Supplementary Note 30) In the driver circuit according to Supplementary Note 24, a device that connects the control terminal of each of the first and second transistors corresponding to the output signal line is the same as each of the first and second transistors. A circuit having a conductivity type and supplying a bias current to each of the first and second control circuits is controlled to have an impedance scaled to an impedance level of each of the first and second transistors. A driver circuit.
[0088]
(Supplementary Note 31) The driver circuit according to any one of Supplementary Notes 1 to 30 is disposed at both ends of the signal transmission path, and bidirectional signal transmission is performed so that each driver circuit also serves as a reception termination of the partner signal. A signal transmission system characterized by performing.
[0089]
【The invention's effect】
As described above in detail, according to the present invention, it is possible to increase the use efficiency of the signal transmission path and perform bidirectional signal transmission or multilevel transmission capable of obtaining an equivalent signal transmission speed with a smaller number of signal lines. Therefore, it is possible to provide a driver circuit and a signal transmission system excellent in linearity of output impedance.
[Brief description of the drawings]
FIG. 1 is a diagram for explaining an example of a conventional driver circuit;
FIG. 2 is a diagram showing a principle configuration of a driver circuit according to a first embodiment of the present invention.
FIG. 3 is a circuit diagram showing a first embodiment of a driver circuit according to the present invention;
FIG. 4 is a circuit diagram showing a second embodiment of the driver circuit of the present invention;
FIG. 5 is a circuit diagram showing a third embodiment of the driver circuit according to the present invention;
FIG. 6 is a circuit diagram showing a fourth embodiment of the driver circuit according to the present invention;
FIG. 7 is a circuit diagram showing a fifth embodiment of the driver circuit according to the present invention;
FIG. 8 is a circuit diagram showing a sixth embodiment of the driver circuit according to the present invention;
FIG. 9 is a circuit diagram showing a seventh embodiment of the driver circuit according to the present invention;
FIG. 10 is a circuit diagram showing an eighth embodiment of the driver circuit according to the present invention.
FIG. 11 is a circuit diagram showing a ninth embodiment of the driver circuit according to the present invention;
FIG. 12 is a diagram showing a principle configuration of a driver circuit according to a second embodiment of the present invention.
FIG. 13 is a circuit diagram showing a tenth embodiment of a driver circuit according to the present invention.
FIG. 14 is a circuit diagram showing an eleventh embodiment of the driver circuit according to the present invention;
FIG. 15 is a circuit diagram showing a twelfth embodiment of the driver circuit according to the present invention;
FIG. 16 is a circuit diagram showing a thirteenth embodiment of the driver circuit according to the present invention;
FIG. 17 is a circuit diagram showing a fourteenth embodiment of the driver circuit according to the present invention;
FIG. 18 is a circuit diagram showing a fifteenth embodiment of the driver circuit according to the present invention;
FIG. 19 is a circuit diagram showing a sixteenth embodiment of the driver circuit according to the present invention;
FIG. 20 is a circuit diagram showing a seventeenth embodiment of the driver circuit according to the present invention.
FIG. 21 is a circuit diagram showing an eighteenth embodiment of the driver circuit according to the present invention;
[Explanation of symbols]
1 ... 1st transistor
2 ... second transistor
3; 403, 413 ... Gate voltage generation circuit
4 ... Output signal line
401 ... Pull-up element
402, 412 ... load
411 ... Pull-down element

Claims (7)

A first transistor having a first terminal connected to the output signal line, a second terminal connected to the first power supply line, and a control terminal;
A second terminal having a first terminal and a second terminal and a control terminal connected in parallel with the first transistor;
And a control circuit that controls a voltage applied to a control terminal of the second transistor in accordance with a potential of the output signal line.   2. The driver circuit according to claim 1, wherein the control circuit is a voltage shift circuit that applies a shift voltage obtained by shifting the voltage of the output signal line by approximately a constant value to a control terminal of the second transistor. Driver circuit characterized by.   2. The driver circuit according to claim 1, further comprising: changing a voltage applied to a control terminal of the second transistor from the off voltage to the on voltage when the second transistor is switched from an off state to an on state. A driver circuit comprising a charge or current injection means for accelerating the motor. A first transistor connected to the output signal line; a second terminal connected to a high-potential power line; and a control terminal; a first transistor for pulling up the output signal line;
A second terminal having a first terminal and a second terminal and a control terminal connected in parallel with the first transistor;
A first control circuit for controlling a voltage applied to a control terminal of the second transistor in accordance with a potential of the output signal line;
A third transistor having a first terminal connected to the output signal line, a second terminal connected to a low-potential power line and a control terminal, and pulling down the output signal line;
A fourth transistor having a first terminal and a second terminal and a control terminal connected in parallel with the third transistor;
And a second control circuit for controlling a voltage applied to a control terminal of the fourth transistor in accordance with the potential of the output signal line. A first transistor having a first terminal connected to the output signal line, a second terminal connected to the first power supply line, and a control terminal;
A control circuit for controlling a voltage applied to a control terminal of the first transistor in accordance with a potential of the output signal line and a control signal ;
Wherein the control circuit includes a resistive device for connecting a control terminal of the first transistor and the output signal line, and wherein Rukoto a resistive device control means for controlling the resistance of said resistive device voltage Driver circuit. A first transistor connected to the output signal line; a second terminal connected to a high-potential power line; and a control terminal; a first transistor for pulling up the output signal line;
A first control circuit that controls a voltage applied to a control terminal of the first transistor in accordance with a potential of the output signal line and a first control signal;
A second transistor having a first terminal connected to the output signal line, a second terminal connected to a low-potential power line and a control terminal, and pulling down the output signal line;
A second control circuit that controls a voltage applied to a control terminal of the second transistor in accordance with a potential of the output signal line and a second control signal ;
The first control circuit includes a first resistive device that connects the output signal line and a control terminal of the first transistor, and a first resistor that controls a resistance of the first resistive device with a voltage. Device control means,
The second control circuit includes a second resistive device that connects the output signal line and a control terminal of the second transistor, and a second resistor that controls the resistance of the second resistive device with a voltage. driver circuit according to claim Rukoto a sexual device control means. The driver circuit according to any one of claims 1 to 6 is disposed at both ends of a signal transmission path, and bidirectional signal transmission is performed such that each driver circuit also serves as a reception termination of a partner signal. A characteristic signal transmission system.

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