JPH09139434A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make it possible to remove the substrate floating effect of a MOS transistor by a method wherein a low density diffusion layer region is provided in the vicinity of the source diffusion layer region of the MOS transistor, and a region having a recombination center structure is provided in the low density diffusion layer region. SOLUTION: A MOS type field effect transistor, which is formed on a SOI substrate 1, is provided. The high density n-type source diffusion layer 91 of the above-mentioned MOS transistor has the first diffusion layer 12 which is connected to a source electrode 14, and the second diffusion layer of a low impurity density region 3 which is at least in the neighborhood of the lower region of the first diffusion layer 12. Also, a region (crystal defective region) 11, having a recombination center mechanism relative to electric charge, is provided inside the second diffusion layer 3. As a result, the minority carrier generated on the SOI substrate 1 can be implanted into the crystal defective region 11 and annihilated, and the substrate floating effect is cancelled.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, a storage device having the semiconductor device as a constituent element, an electronic control device,
It also relates to an electronic computer device.

[0002]

2. Description of the Related Art A method of forming a transistor in a single crystal semiconductor layer on an insulating film is SOI (Silicon On Insulator).
It is known as a structure, and the structure shown in FIG.
It is described in the 1993 Spring Applied Physics Society Proc. A MOS field effect transistor (hereinafter simply abbreviated as MOS) is composed of a single crystal silicon (Si) film 30 isolated from a support substrate 1 by a thick insulating film 2. In FIG. 2, 4 is an element isolation insulating film, 5 is a gate insulating film, 61 is a gate electrode, 7 is a gate protective insulating film, 8 is a gate side wall insulating film, and 9 and 10 are The n-type high-concentration diffusion layer is a source region and a drain region, respectively. Since the SOI-MOS as shown in FIG. 2 has the thick insulating film 2 immediately below, it has a feature that the drain junction capacitance and the wiring parasitic capacitance can be reduced to about 1/10 as compared with the conventional MOS. Further, since the MOS is insulated and separated from the substrate, it has a feature that a malfunction due to α-ray irradiation and a latch-up phenomenon can be fundamentally eliminated.

The drawback of the conventional SOI-MOS is that since the single crystal Si film 30 is insulated from the supporting substrate 1, minority carriers generated by a strong drain electric field or the like are generated in the single crystal Si film 3.
There is a so-called substrate floating effect in which the threshold voltage value is transiently accumulated in 0 and the threshold voltage value is changed. The above-mentioned effect is reduced as the potential increases due to the accumulation of minority carriers in the single crystal Si film 30.
It is also a parasitic bipolar effect in which a majority carrier inflow from the memory occurs. In the n-conductivity SOI-MOS (abbreviated as nMOS), holes are accumulated, the threshold voltage value fluctuates in the negative direction, and a peculiar hump is observed in the current-voltage characteristic, or the leakage current in the off state increases In addition, the breakdown voltage between the source and drain is reduced. The substrate floating effect described above may be a fatal defect for a differential amplifier or an analog circuit that requires detection of a minute current difference.

The SOI-MOS shown in FIG. 2 has a structure proposed for eliminating the above-mentioned floating effect of the substrate, and germanium (Ge) is ion-implanted into the source high-concentration diffusion layer 9 to obtain a Ge component ratio. About 10% of SiGe mixed crystal 16 is formed. FIG. 3 is an energy band diagram along the channel in the state where the drain voltage Vds is applied in the SOI.MOS of FIG. Efn is a pseudo Fermi level and Ei is an intrinsic Fermi level. SiGe mixed crystal 1
Introducing 6 narrows the bandgap by about 0.1 eV,
The valence band Ev in the source is constructed as shown by the broken line. The difference in diffusion potential for holes near the source is eliminated. As a result, the holes generated near the drain and injected into the single crystal Si film 30 easily diffuse into the source and disappear. It is said that the conduction band Ec is not affected by the SiGe mixed crystal and has no adverse effect on the behavior of electrons that are majority carriers.

Other known techniques having the same problem are disclosed in Japanese Patent Application Laid-Open Nos. 5-75120 and 6-291142.

In the technique described in Japanese Patent Laid-Open No. 75120/1993, a p-type high-concentration region is provided in the n-type high-concentration source diffusion layer in contact with the buried insulating film, and the p-type region is used as a collector. The pnp parasitic bipolar transistor is used to eliminate the holes injected into the n-type high-concentration source diffusion layer.

However, in this method, the following 2
It turned out to have one drawback. First, since the concentration of the n-type diffusion layer acting as the base of the pnp parasitic bipolar transistor is high, holes can be injected from the p-type SOI substrate into the n-type high-concentration source diffusion layer. The diffusion potential difference is too high, and the hole injection efficiency is extremely low.

Secondly, even if holes are injected, the p-type high-concentration region itself that acts as a collector does not act as a recombination center, and the absorption of holes cannot be maintained. When the p-type high-concentration region itself does not have a hole annihilation mechanism, the p-type high-concentration region acting as a collector in order to maintain the hole flow is negative with respect to the n-type high-concentration source diffusion layer. It is necessary to apply a voltage. When the collector terminal is open, no collector current flows and the p-type SOI
The holes generated in the substrate cannot be extracted. JP 6
The technique of Japanese Patent Application No. 291142 provides a p-type diffusion layer in contact with the bottom of the n-type high-concentration source diffusion layer. This p
The type diffusion layer is in side contact with the p-type SOI substrate, which is a hole generation region. In such a structure, the generated holes are p
Since it is also dispersed in the type diffusion layer, the hole density in the channel region is relatively lowered, and the substrate floating effect is reduced. However, even in the present technology, the generated holes do not disappear, and this is not an essential solution. In particular, in order to reduce the substrate floating effect, it is necessary to increase the area of the p-type diffusion layer region that acts as a collector, which hinders miniaturization, low parasitic capacitance, or high-speed operation.

[0009]

The structure shown in FIG. 2 is effective in eliminating the substrate floating effect of SOI.MOS.
Limited to MOS, not versatile. p conductivity type MOS (pM
It is not applicable to OS) and complementary MOS (abbreviated to CMOS). That is, the presence of the SiGe mixed crystal eliminates the diffusion potential difference in the valence band near the source diffusion layer even in the pMOS, and the diffusion potential difference in the conduction band is preserved. In this situation, holes, which are majority carriers, are punch-through.
This means that a phenomenon is caused and it cannot be controlled by the gate potential. On the contrary, electrons of minority carriers injected into the single crystal Si film 30 cannot be injected into the source and the substrate floating effect cannot be eliminated.

The object of the present invention is not limited to an nMOS, but is also a p-conductivity type MOS (abbreviated as pMOS) and a complementary type MOS.
Another object of the present invention is to provide a semiconductor device having a highly versatile substrate floating effect elimination structure that can be applied to (abbreviated as CMOS) and the like.

Further, in the conventional structure shown in FIG. 2, SOI is used.
The elimination of the substrate floating effect of MOS is not sufficient, and in order to further promote the elimination of the substrate floating effect, the mixed crystal ratio of Ge in the SiGe mixed crystal is increased. Along with this, the conventional method has the drawback of increasing the junction leak current due to the occurrence of crystal strain and further causing the junction breakdown.

Another object of the present invention is to provide a semiconductor device capable of eliminating the substrate floating effect without deteriorating the junction characteristics.

Furthermore, GeH is usually used for implanting Ge ions.
_Although GeH ₄ is used as an ion source, GeH ₄ is a substance that is extremely easily decomposed, it is difficult to stably supply the implanted ions, and it is difficult to control the ion current and thus the ion implantation conditions. In addition, since the ion chamber is contaminated, it is difficult to share it with other ion implantations, and it is necessary to introduce an ion implantation device dedicated to Ge.

Another object of the present invention is to provide a method of manufacturing a semiconductor device having a substrate floating effect eliminating structure which can be manufactured only by an existing sharable semiconductor manufacturing device.

Another object of the present invention is to provide in CMOS
It is intended to realize the elimination of the floating body effect of the nMOS and the pMOS at the same time by the same manufacturing process, thereby simplifying the manufacturing process and eventually reducing the manufacturing cost.

[0016]

The operating principle of the present invention is described in nM.
The OS will be described as an example. The pMOS can be operated in the same manner by replacing the conductivity type with the opposite conductivity type.

In the present invention, it occurs near the drain,
The holes accumulated in the substrate are promptly injected into the source diffusion layer and disappeared.

As the above means, a region having a small diffusion potential difference formed between the p-type substrate region immediately below the channel and the source diffusion layer, that is, an n-type diffusion layer region having a sufficiently low concentration is used as a source high-concentration diffusion layer. Adjacent to each other. Further, a region that acts as a recombination center for holes is provided in the n-type low-concentration diffusion layer region to eliminate the holes injected into the n-type low-concentration diffusion layer region. The electrons required for annihilation of holes are supplied from the n-type high concentration diffusion layer region on the surface of the source. In the present invention, a recombination center based on a crystal defect or the like is used as a hole annihilation mechanism by the recombination center.

FIG. 4 is an enlarged sectional view in the vicinity of the source diffusion layer in this semiconductor device, and FIG. 5 is an energy band diagram in the vicinity of the source when the drain voltage is the ground voltage. The bottom of the source region is assumed to be separated from the outside by a buried oxide film. In FIG. 4, the energy band in the case of the conventional source structure with the high-concentration source diffusion layer is also shown by the broken line, but in the structure of the present invention, the reduction of the diffusion potential difference for holes is obvious. The impurity concentration in the low-concentration diffusion layer is preferably as low as 1 × 10 ¹⁵ /
It is desirable that the density is at least cm ³ and at most 1 × 10 ¹⁸ / cm ³ . The formation of crystal defects that act as recombination centers performs ion implantation with an element that does not increase the diffusion potential difference for holes in the n-type low-concentration diffusion layer, and amorphizes the bottom surface of the SOI layer. Since the bottom portion of the amorphous material is an oxide film even after a short time high temperature heat treatment, single crystallization by recrystallization heat treatment is not performed except for the side surface portion of the single crystal SOI layer directly below the gate, and polycrystallization is performed. It just progresses. The polycrystallinity or amorphousness can be controlled by the heat treatment condition, and the recombination center characteristic can be controlled.

CMOS which is the mainstream of MOS type semiconductor devices
In applying the method of the present invention to a semiconductor device, applying nMOS and pMOS separately causes an increase in the number of manufacturing steps and a decrease in yield of non-defective products, leading to an increase in manufacturing cost. Therefore, as an ion implantation source for forming recombination centers, elements that do not increase the diffusion potential difference with respect to minority carriers in the n-type and p-type low-concentration diffusion layers are added to the source low-concentration diffusion regions of pMOS and nMOS in the same step. It is desirable to implant ions to form recombination. From the above viewpoint, in the MOS semiconductor device made of Si semiconductor, it is desirable that the ion implantation source is an element other than P, B, As, Sb, Ga, which is easily activated to form n or p conductivity type. Furthermore, it is desirable that the element be an element that makes the semiconductor substrate non-amorphous by ion implantation, and an element having an atomic mass of 10 or less is not preferable. Alkali metals such as Na and K, which have an extremely large diffusion coefficient in the Si semiconductor and impair reliability, and alkaline earth metals including Mg are also not preferable. In the present invention, Group 14 elements such as Si, Ge, C, etc., which constitute the semiconductor, halogen elements such as F, Cl, etc., and rare gas elements such as Ne, Ar, etc. are preferable. Particularly inexpensive, stable supply, easy ionization and stable S
The elements such as i, C, Ne, Ar and Cl are most preferable.

As one method of forming the semiconductor device of the present invention, first, a low-concentration source and a high-concentration source are formed using the gate electrode as a mask.
A drain diffusion layer is formed. The low concentration diffusion layer is SOI
Each time it reaches the thick silicon oxide film immediately below the layer, it is formed by ion implantation and subsequent heat treatment. From this state, a gate side wall insulating film is formed, and ion implantation of, for example, Si is performed using the gate electrode and the gate side wall insulating film as a mask so as to reach a thick silicon oxide film immediately below the SOI layer. The SOI layer in the interface region is made amorphous. The interface portion of the amorphous region is not single-crystallized by subsequent heat treatment, but is polycrystallized by fine grain boundaries and functions as a recombination center. Spacing between recombination center region and channel region SOI substrate,
That is, the width of the source low concentration n-type diffusion layer is controlled by the film thickness of the gate side wall insulating film. The width of the source low concentration n-type diffusion layer is preferably 100 nm or less so that the minority carriers easily reach the recombination center region and disappear. In the n-type high-concentration source region formed on the surface of the SOI layer, after the recombination center region is formed, a certain thickness of the surface portion is selectively removed.
It may be formed by leaving the semiconductor film by the deposition method.

As another method of forming the present semiconductor device, a source / drain region having a desired diffusion layer structure is formed on the basis of a conventional manufacturing method, and then a contact hole for connecting to a source electrode is formed. Ion implantation for forming a low-concentration diffusion layer reaching the thick silicon oxide film directly below the SOI layer is selectively performed from the contact hole. After that, a sidewall film may be provided so as to reduce the contact hole size by a certain width, and ion implantation for forming a recombination center region using the sidewall film as an implantation mask may be performed so as to reach a thick silicon oxide film immediately below the SOI layer. .

Since the method of the present invention is carried out by using the gate electrode and the gate sidewall insulating film or the contact hole as an ion implantation mask, a similar structure is formed in the drain region. In the drain, the drain voltage is applied to the n-type high-concentration region, but since the relationship between the n-type high-concentration region and the bottom recombination center region in the drain has a reverse characteristic with respect to the hole injection, it is a junction re-connection. The increase in the output current can be ignored, and there is no hindrance to the operation of the NOS transistor.

In the structure shown in FIG. 4, the hole current flowing when the n-type high-concentration region is set to the ground potential and a positive voltage is applied to the p-type low-concentration SOI substrate is separated between the recombination center region and the channel region SOI substrate. FIG. 6 shows the result obtained by numerical analysis as a parameter of Thickness of 300n for the above analysis
p-type SOI with uniform concentration distribution of m, 4 × 10 ¹⁷ / cm ³
The layer was used as a parameter, and the distance between the recombination center region and the channel region SOI substrate, that is, the source low-concentration n-type diffusion layer width. Source low concentration n-type diffusion layer has maximum concentration of 1 × 10 ¹⁶ / c
It has a Gaussian distribution of m ^{3 and} is configured so as to be in contact with the buried insulating film at the bottom of the SOI layer. The recombination time is assumed to be 1/10 ¹⁰ seconds in the recombination center region and 1/10 ⁴ seconds in other regions. The value of recombination time of 1/10 ¹⁰ seconds is a value usually observed in a polycrystalline Si film.

For reference, FIG. 6 also shows the hole current of a normal source structure having no recombination center region as a thin line. Regarding the hole current, there is a threshold voltage at which a current proportional to the applied voltage starts in an exponential function, and below the threshold voltage, the behavior is as if the current becomes zero when the applied voltage is zero. In the case of this semiconductor device structure, the hole current in the vicinity of the threshold voltage value is about three orders of magnitude higher than the conventional structure under the condition that the source low-concentration n-type diffusion layer width is 40 nm or less, and the threshold voltage is 0.2 V. A decline is seen.
The above meaning means that the source diffusion potential for the hole current is 0.2 eV in the present semiconductor device structure as compared with the conventional structure.
It has been lowered. The above-mentioned values are the values of reduction of the source diffusion potential of the well-known SiGe mixed crystal formation of 0.
It is twice as high as 1 eV, which shows that the elimination of the floating body effect is further improved as compared with the known method. The above-mentioned decrease in the threshold voltage tends to be eliminated as the base width increases,
Even with the source low-concentration n-type diffusion layer width of 0.1 μm, a decrease of 0.04 V is observed as compared with the conventional structure. That is, in this semiconductor device structure, the source low-concentration n-type diffusion layer width is 0.1.
It is desirable that it is not more than μm.

The results of FIG. 6 relate to the forward characteristic of applying a positive voltage to the channel region SOI substrate. It was carried out numerical analysis with regard reverse characteristics of a positive voltage is applied to the n-type high concentration region, between the current in the analysis results to -3V 1/10 ¹³ in the computing error range of 1/10 ¹⁵ A The value did not differ from that of the normal structure. This result shows that even if the same structure as in the source is constructed in the drain,
This indicates that problems such as an increase in the black current do not occur.

The above hole current is proportional to the cross-sectional area of the hole annihilation region viewed from the side of the channel region SOI substrate. Therefore,
When the SOI layer is so thin as to define the junction depth of the source / drain high-concentration diffusion layer, the hole annihilation effect is limited. For example, when the SOI layer has a thickness of 50 nm, the source / drain high-concentration diffusion layer has a junction depth of 40 nm, and the hole annihilation region has a thickness of 10 nm, the increase component of the source hole current is larger than that of the normal structure. It is just over one digit at most. In the ultra-thin SOI substrate structure as described above, if the hole extinction region is formed as a p-type diffusion layer, the efficiency of the hole extinction effect is further improved, and a sufficient hole extinction effect can be expected. As shown in the equivalent circuit diagram of FIG. 7, the above is a parasitic pnp bipolar transistor in which the p-type substrate region immediately below the channel is the emitter, the low-concentration n-type diffusion layer region is the base, and the hole annihilation region is the p-type collector. This is equivalent to forming a transistor, and by using the p-type collector for the hole extinction region, the hole extraction effect is further enhanced as compared with the structure in which the hole extinction region is a low concentration n-type region. FIG.
Is a structure in which the hole extinction region is composed of a p-type diffusion layer.
The high-concentration type region is set to the ground potential, and the hole current flowing when a positive voltage is applied to the p-type low-concentration SOI substrate is obtained as a parameter of the distance between the recombination center region and the channel region SOI substrate by numerical analysis. Show. Where SOI
The layer thickness is 50 nm, the source / drain high-concentration diffusion layer has a junction depth of 40 nm, and the hole annihilation region has a thickness of 10 nm. From the figure, it can be seen that the hole annihilation effect, that is, the substrate floating effect, can be sufficiently solved even in the case where the SOI layer has an extremely thin structure of 50 nm.

The semiconductor device according to the present invention has a symmetrical structure with respect to the source and the drain, and is also effective for a so-called transfer MOS or the like in which the drain and the source are exchanged for bidirectional operation depending on the circuit operating conditions. is there. Further source
The presence of the recombination center region in the drain and drain does not affect the capacitance between the drain and the substrate, and the conventional S
The effect of reducing the parasitic capacitance by the thick buried oxide film, which is the greatest feature of OI-MOS, is maintained. Further, the present invention is effective regardless of the conductivity type of the semiconductor device, and therefore, the SOI / CM
It is effective in eliminating the substrate floating effect of the OS. According to the present invention, it is possible to solve the problems such as the transient fluctuation of the threshold voltage due to the substrate floating effect, the abnormal current / voltage characteristic, and the source / drain breakdown voltage reduction, which have been the greatest drawbacks of the conventional SOI / MOS. You can Introducing new semiconductor device manufacturing equipment such as a dedicated ion implanter for semiconductor devices that can operate at high speed by taking advantage of the original characteristics of SOI-MOS such as low parasitic capacitance and reduction of the number of manufacturing processes. It can be provided at a low price without doing.

As another method of the present invention, a region having a small diffusion potential difference formed between the p-type substrate region immediately below the channel and the source diffusion layer, that is, an n-type diffusion layer region having a sufficiently low concentration is formed as a source high concentration. It is provided adjacent to the diffusion layer. Further, a metal or metal silicide film that acts as a recombination center for holes is provided adjacent to the n-type low-concentration diffusion layer region to extinguish the holes injected into the n-type low-concentration diffusion layer region. . FIG. 9 is an energy band diagram near the source of the present semiconductor integrated circuit device when the drain voltage is the ground voltage. In FIG.
The energy band of the conventional source structure portion by the high concentration source diffusion layer is shown by a solid line, and the energy band of the n-type low concentration diffusion layer region portion is shown by a broken line. In the structure of the present invention, it is clear that the diffusion potential difference for holes in the n-type low-concentration diffusion layer region portion is lower than that in the high-concentration source diffusion layer portion. The impurity concentration of the n-type low concentration diffusion layer is preferably as low as 1 × 10 ¹⁵ / cm ³ or more as long as the conductivity type does not change.
It is preferably 10 ¹⁸ / cm ³ or less. A Schottky barrier is formed between the n-type low concentration diffusion layer and the metal or metal silicide film, but the barrier does not serve as a diffusion barrier for holes, and the holes reach the metal or metal silicide film, It will disappear promptly.

In order to quickly inject holes generated in the vicinity of the drain and accumulated in the substrate into the source diffusion layer, p
It is an essential condition that the diffusion potential difference formed between the mold substrate region and the source diffusion layer is small, but in the process of forming the metal silicide film, the metal silicide film formed on the high concentration source diffusion layer is There is a possibility that the n-type impurities diffuse very quickly to the surface of the n-type low-concentration diffusion layer region through the intervening region, increasing the concentration of the surface portion. The higher concentration increases the diffusion potential difference with respect to holes, making it difficult to inject holes into the source region. From the above viewpoint, making the surface of the n-type low-concentration diffusion layer region where the holes should be injected into the metal silicide film p-type is also very effective in eliminating the substrate floating effect. The p-type conversion step can be realized by ion-implanting p-type ions (for example, B) from the contact hole for connecting to the source electrode. Another means for solving the problem of rapid diffusion of n-type impurities through the metal silicide film is to use a refractory metal film such as W instead of forming the metal silicide film as the hole recombination center. In this case, high-speed diffusion of impurities does not occur, and the p-type conversion step on the surface of the n-type low-concentration diffusion layer region can be omitted.

In the source region of the structure of the present invention, it is necessary to form a high concentration diffusion layer and a low concentration diffusion layer under the metal or metal silicide film. When the semiconductor integrated circuit device is composed of only nMOS, a mask for separating the above two types of diffusion layer regions is required. In the CMOS, if the mask for separating the diffusion layer region is an n-type ion implantation blocking mask for the pMOS region so as to cover the region where the n-type low-concentration diffusion layer is to be formed, no extra mask is required, so that the number of manufacturing steps is reduced. No increase.

According to the present invention, the presence of the n-type low-concentration diffusion layer that lowers the source junction barrier against the holes of minority carriers generated in the SOI substrate and the holes injected into the n-type low-concentration diffusion layer are promptly detected. It is characterized by a structure having a metal or metal silicide film, which has a role as a recombination center to be eliminated, in the source region. It is practically difficult to accurately align the ion implantation blocking mask with a practical mask aligner, for example, series connection n in a CMOS NAND gate.
It is practically impossible to form an n-type low-concentration diffusion layer in a minimum size region such as a MOS source / drain region where contact holes are not arranged. Therefore, the source structure of the present invention cannot be applied to the above region. In order to eliminate the substrate floating effect of the NAND gate, in the present invention, the source / drain diffusion layer bottom of the series-connected transistor portion is provided with a source / drain high-concentration diffusion layer as if it were an electrically common substrate. It is formed shallowly and the above-mentioned minority carrier disappearance mechanism is formed only in the source region of the final transistor.

A bidirectional transistor (transfer MO) in which the roles of the source and the drain are reversed depending on the operation timing.
In S), the minority carrier annihilation mechanism according to the present invention is also formed in the drain region. In the drain, the drain voltage is applied to the n-type low-concentration diffused layer together with the n-type high-concentration region. Is negligible, and there is no hindrance to the operation of the NOS transistor.

[0034]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in more detail by way of examples. In order to facilitate understanding, the drawings are used for the description, and the main parts are shown in a larger scale than the other parts. It is needless to say that the material, conductivity type, manufacturing conditions and the like of each part are not limited to those described in the present embodiment, and many modifications are possible.

Embodiment 1 FIGS. 10 to 12 are sectional views showing a sequence of manufacturing steps of a semiconductor device according to a first embodiment of the present invention, and FIG. 1 is a completed sectional view thereof. A 500 nm thick silicon oxide film (hereinafter simply referred to as an oxide film) 2 on a supporting substrate 1 made of single crystal Si having a diameter of 12.5 cm, an n conductivity type of 200 nm thick, and a resistivity of 0.
An SOI substrate composed of a single crystal Si layer 3 having a surface orientation (100) of 5 Ωcm (impurity concentration of 1 × 10 ¹⁶ / cm ³ ) was used to form an element isolation insulating film 4 or 5 nm thick by a known MOS field effect transistor manufacturing method. A gate oxide film 5, a gate electrode 6 made of an n-type low resistance polycrystalline Si film, and a gate protective insulating film 7 were formed. Prior to the formation of the gate oxide film 5, B ions were selectively implanted into the gate electrode formation planned region 32 of the single crystal Si layer 3 so that the threshold voltage value became 0.1V. The ion implantation may be carried out after the gate oxide film 5 is formed. The gate length is 200 nm. In this state, the gate protective insulating film 7 and the gate electrode 6 are used as an injection blocking mask to accelerate energy of 25 keV and dose of 3 ×.
Ion implantation of As and subsequent heat treatment were performed under the conditions of 10 ¹⁵ / cm ² to form a high-concentration n-type diffusion layer source 91 and a drain 101. In each of the above n-type impurity ion implantations, the single crystal Si layer 3 maintained single crystallinity (FIG. 1).
0).

From the state of FIG. 10, a depositing insulating film having a thickness of 200 nm is formed on the entire surface, and the insulating film is selectively left only on the gate side wall portion by anisotropic dry etching to obtain the gate side wall insulation. The film 8 was formed. Regarding the film thickness conditions of the gate side wall insulating film 8, the minimum film thickness is 20 nm and the maximum film thickness is 0.5 μ.
A semiconductor device according to this example in which the distance from m to m was changed at intervals of 10 to 100 nm was also separately manufactured. Subsequently, the high dose n-type diffusion layer source 91 and the low dose n-type substrate region 3 left under the drain 101 have a dose amount of 3 × 10 ¹⁵ / cm 3 as the concentration becomes maximum at the interface of the oxide film 2. Ar under the condition ²
Ion implantation was performed. 800 after the above ion implantation
Heat treatment was performed at 10 ° C. for 10 minutes. As a result of observing a cross section of a sample separately manufactured under the same conditions with a transmission electron microscope, it was revealed that a crystal defect region 11 made of polycrystal with a fine grain size was formed near the interface of the oxide film 2. In the ion implantation of Ar, the acceleration energy may be set so that the maximum concentration is within the oxide film 2. Further, as a result of another experiment, the ion implantation for forming the crystal defect region 11 does not have to be Ar as an ion species, and a rare gas element such as Ne,
Halogen elements such as F and Cl, and 1 such as Si, C and Ge
It was found that the same effect can be obtained even with a Group 4 element. However, it has been found that ion implantation of an element that constitutes the n-conductivity type in Si single crystal such as P has no effect as described later. (FIG. 11).

From the state shown in FIG. 11, a W film 12 having a thickness of 150 nm was selectively deposited on the exposed Si surface by a chemical vapor reaction for the purpose of reducing the source resistance. The W film 12
May be formed by depositing the entire surface by sputtering and patterning so as to cover at least the surfaces of the high-concentration n-type regions 91 and 101. After that, the wiring protection insulating film 13 was deposited with a silicon oxide film to which phosphorus was added (FIG. 12).

From the state shown in FIG. 12, an opening is formed in a desired portion of the wiring protection insulating film 13 based on a known semiconductor device manufacturing method.
Further, a wiring including a source electrode 14, a drain electrode 15 and the like was formed by vapor deposition of a wiring metal and its patterning.
(FIG. 1).

The source-drain breakdown voltage of the semiconductor device according to this embodiment manufactured through the above manufacturing process is 4.7V.
In comparison with the conventional structure SOIMOS of the same size in which the crystal defect region 1 in the source is not formed,
It has been possible to secure a withstand voltage value equivalent to that of a MOS of the same size normally manufactured on a semiconductor substrate. Also, in the current / voltage characteristics, abnormal knot-like characteristics called kink characteristics were not observed, and the characteristics were normal. Furthermore, in terms of source / drain current / gate voltage characteristics, conventional SOI / MOS
The presence of a leak current at the low gate voltage observed in 1. was not observed. Further, the leak current and the threshold voltage value were not found to change even if the drain voltage was changed.
From these characteristics, it has been clarified that the semiconductor device according to the present embodiment has been completely eliminated from the characteristics associated with the substrate floating effect. It was also found that the current / voltage characteristics of the semiconductor device according to this example showed normal characteristics, and that the crystal defect region 11 formed inside the source and the drain had no adverse effect. In the semiconductor device manufactured by changing the film thickness of the gate sidewall insulating film 8 according to this embodiment, the substrate floating effect according to this embodiment can be eliminated by ion implantation p for threshold voltage control from the edge of the crystal defect region 11. The interval to the mold region 32 was observed from 500 nm or less to 20 nm, but no variation in characteristics was observed, and it became clear that a sufficient substrate floating effect can be obtained if the interval is 500 nm or less. In addition, in the sample in which the crystal defect region 11 was formed based on the ion implantation of P, the substrate floating effect was hardly found to be eliminated.

The semiconductor device according to this embodiment is SOIMO.
Since S is effective in eliminating the substrate floating effect, it was speculated that the polycrystallinity of the crystal defect region 11 formed in contact with the oxide film 2 sufficiently acts as the recrystallization center of the injected holes.

In the semiconductor device according to the present embodiment, the single crystal Si layer 3 is relatively thick as 200 nm, and the depletion layer and the neutral region exist in the substrate region under the channel region even when the gate voltage above the threshold voltage is applied. This is a so-called partially depleted structure. The partially depleted structure operates at a low voltage and at a high speed, and is slightly lower than the fully depleted structure, but can be easily manufactured under the conventional manufacturing conditions using a semiconductor substrate. In the semiconductor device according to this embodiment, the partially depleted structure M is inexpensive.
It shows that the OS floating board countermeasure can be provided.

Embodiment 2 FIG. 13 is a sectional view showing a manufacturing process of a semiconductor device according to another embodiment of the present invention, and FIG. 14 is a completed sectional view thereof. In this embodiment, the n-conductivity type single crystal Si layer 3 in the first embodiment is used.
Instead, an SOI substrate having a p-conductivity type and a resistivity of 10 Ωcm and other specifications having a single crystal Si film 30 under the same conditions was used. Based on the first embodiment, the element isolation insulating film 4, the gate
The formation of the gate oxide film 5, the gate electrode 6, and the gate protective insulating film 7 was carried out. However, prior to the formation of the gate oxide film 5, the maximum impurity concentration of the single crystal Si film 30 was 2 × at the surface portion. 10 ¹⁷ / c
Ion implantation of B was performed at m ³ . From this state, the bottom reaches the oxide film 2 and the maximum impurity concentration is 1 × 10 ¹⁷
Ion implantation of P to form the n-type low-concentration diffusion layer 33 of / cm ³ was performed using the gate protection insulating film 7 and the gate electrode 6 as an implantation blocking mask. Subsequently, according to the first embodiment, a high-concentration n-type diffusion layer source 91 and a drain 101 are formed by As ion implantation using the gate protection insulating film 7 and the gate electrode 6 as an implantation blocking mask and subsequent activation heat treatment. Was formed. Each of the above ion-implanted regions was heat-treated to be single-crystallized (FIG. 13).

A silicon nitride film having a thickness of 100 nm is deposited on the entire surface from the state shown in FIG. 13, and the gate sidewall insulating film 8 is formed by selectively leaving the silicon nitride film only on the gate electrode sidewall by anisotropic dry etching. And Next, using the gate side wall insulating film 8, the gate protective insulating film 7 and the gate electrode 6 as an implantation blocking mask, Si ion implantation is performed at a dose amount of 1 as the concentration becomes maximum at the interface of the oxide film 2. It was carried out under the condition of × 10 ¹⁵ / cm ² . After the ion implantation, heat treatment was performed at 900 ° C. for 10 minutes, but the crystal defect region 11 of polycrystalline fine grain size was left in the single crystal Si film 30 near the interface of the oxide film 2 even after the heat treatment. The crystal defect region 11 was formed in the high-concentration n-type diffusion layer source 91 and the n-type low-concentration diffusion layer 33 in the lower region of the drain 101, but the high-concentration n-type diffusion layer formed above it. Source 91 and drain 10
1, and the n-type low-concentration diffusion layer 33 on the side thereof was single-crystallized. After the above heat treatment, a single crystal Si film 30 is formed by sputtering a Ti film having a thickness of 80 nm and heat treatment thereafter.
After the Ti silicide film 121 was selectively formed on the exposed portion, the unreacted Ti film in the region other than the above-mentioned portion was selectively removed. Subsequently, the selectively silicified Ti silicide film 121 is heat-treated to reduce its resistance, and then the wiring protection insulating film 13 is deposited according to the first embodiment, the openings are formed at desired locations, the wiring metal film is vapor-deposited, and the pattern thereof is formed.
A wiring including the source electrode 14, the drain electrode 15 and the like was formed by the annealing (FIG. 14).

The single crystal Si layer 30 used in the semiconductor device according to this embodiment manufactured through the above manufacturing process is used.
By forming the n-type low-concentration diffusion layer 33 by ion implantation regardless of the conductivity type and the resistivity, the phenomenon associated with the floating body effect due to the SOI structure is eliminated as in the semiconductor device of the first embodiment. I was able to.

Embodiment 3 FIG. 15 is a completed sectional view of a semiconductor device according to another embodiment of the present invention. In this embodiment, an ultra-thin SOI substrate in which the single crystal Si film 30 used in the second embodiment has a thickness of 70 nm is used. A semiconductor device was manufactured on the single crystal Si film 30 according to the second embodiment. In the present embodiment, 5 × 10 ¹³ / is formed in the Si ion implantation planned region prior to Si ion implantation.
A cm ² dose amount of B ions was implanted to form a p-conductivity type crystal defect region 111. The B ion implantation may be performed in any dose amount as long as it is a dose amount that compensates the conductivity type of the n-type low-concentration diffusion layer 33 in which the crystal defect region is formed and makes it the opposite conductivity type. .

In the semiconductor device according to the present embodiment manufactured through the above manufacturing steps, the characteristics associated with the substrate floating effect are not observed, and the normal SOIMOS characteristics are obtained, like the semiconductor devices according to the first and second embodiments. I was able to get

In the semiconductor device according to the present embodiment, the single crystal Si layer 3 is extremely thin at 70 nm.
Due to the limitation of the amount of charge within 0, the neutral region does not exist in the single crystal Si layer 30 in the channel region under the gate voltage condition of the threshold voltage or more, and the single crystal Si layer 30 is in a fully depleted state. This is capable of effectively inducing mobile charges in the channel, which is a current drive source, and is suitable for increasing the current. That is, it is suitable for low voltage and high speed operation. In the semiconductor device according to the present embodiment, the above fully depleted SOIMO is produced without the substrate floating effect.
S can be provided at a low price only by the conventional semiconductor device manufacturing method.

Embodiment 4 FIGS. 16 to 17 are sectional views showing a manufacturing process of a semiconductor device according to another embodiment of the present invention, and FIG. 18 is a completed sectional view thereof. In this example, an SOI substrate having the same specifications as the single crystal Si film 30 used in Example 2 was used. According to the second embodiment, after the manufacturing process is advanced to the formation of the element isolation insulating film 4, the gate oxide film 5, the gate electrode 6, and the gate protective insulating film 7, the gate electrode 6, And high-concentration ion implantation with low acceleration energy of 2 keV of As using the gate protection insulating film 7 as a mask, and a shallow junction n-type high concentration with a junction depth of 10 nm and a surface impurity concentration of 1 × 10 ²¹ / cm ^3. Diffusion layer 95,
And 105 were formed. Then, according to the second embodiment, 1
A gate side wall insulating film 8 having a thickness of 00 nm is formed, high-concentration ion implantation of P is performed using the gate side wall insulating film 8 as a mask, and a low resistance source diffusion layer 91 having a junction depth of 100 nm and a low resistance source diffusion layer 91 are formed. A resistance drain diffusion layer 101 was formed (FIG. 16).

From the state shown in FIG. 16, a wiring protection insulating film 13 was deposited and an opening was formed at a desired position based on a known semiconductor device manufacturing method. Ion implantation of P is performed from the above opening,
An n-type low-concentration diffusion layer 9 having a minimum impurity concentration of 1 × 10 ¹⁶ / cm ³ was formed in contact with the lower portion of the low-resistance source diffusion layer 91 so as to reach the underlying oxide film 2. In the above process, the n-type low concentration diffusion layer 10 is simultaneously formed on the bottom of the drain diffusion layer. After performing heat treatment for activating the n-type low-concentration diffusion layers 9 and 10 and adjusting the diffusion depth, a deposition film 131 made of a different material for the wiring protection insulating film 13 is formed on the side surface of the opening by a dry etching method. And left it selectively. It is significant that the opening sidewall insulating film 131 has a film having a constant film thickness from the opening and serving as an ion implantation mask on the sidewall portion, and even if it exists on the opening bottom portion, no problem occurs in the next process. From this state, high energy ion implantation of Si using the opening side wall film 131 as a mask is performed under the conditions of the second embodiment, and the crystal defect region 11 is formed in the n-type low concentration diffusion layer 9 near the interface of the oxide film 2. Formed. In the above manufacturing process, the method of using the opening sidewall film 131 for adjusting the distance from the edge of the crystal defect region 11 to the junction of the n-type low concentration diffusion layer 9 has been described. It may be based on a method of adjusting by. In this case, the step of forming the opening sidewall film 131 can be omitted (FIG. 17).

From the state shown in FIG. 17, the source electrode 14, the electrode including the drain electrode 15 and the wiring layer made of the wiring metal material were formed based on a known method for manufacturing a semiconductor device. Although FIG. 16 shows a cross-sectional view of the semiconductor device according to the process of removing the opening side wall film 131 and then forming the wiring material, there is no problem even if the opening side wall film is left as it is. (FIG. 18).

In the semiconductor device according to the present embodiment manufactured through the above manufacturing steps, the characteristics associated with the substrate floating effect are not observed and the normal partial depletion is observed as in the semiconductor devices according to the first and third embodiments. Type SOIMOS characteristics could be obtained. Further, in the semiconductor device according to the present embodiment, the elimination of the substrate floating effect can be realized only in the contact hole region, so that there are no restrictions on the source and drain diffusion layer shapes in the vicinity of the gate electrode end that determine the transistor characteristics. Does not happen. Therefore, according to this embodiment, desired transistor characteristics can be realized without the influence of the substrate floating effect.

In this embodiment, a diagram for studying the optimum condition of the interval Wb from the edge of the crystal defect region 11 to the junction of the n-type low concentration diffusion layer 9 and the maximum impurity concentration Nb of the n-type low concentration diffusion layer 9 is shown. In the state of 16, the dose amount of P ion implantation and the film thickness of the opening side wall film 131 were changed variously. The maximum impurity concentration Nb of the n-type low concentration diffusion layer 9 is 1 × 10 ¹⁶ / cm.
³ to 1x10 ²⁰ / cm ^3, the interval Wb was varied from 20nm to 500 nm. Maximum impurity concentration Nb is 1x
SO rises from 10 ¹⁹ / cm ³ to 1 × 10 ²⁰ / cm ³
Almost no sign of elimination of the substrate floating effect was observed, probably because the barrier against hole injection from the I substrate 30 becomes high. The maximum impurity concentration Nb is 1 × 10 ¹⁸ / cm ³ to 1 × 10 ¹⁹
/ Cm ³ , the elimination of the substrate floating effect was observed when the distance Wb was 100 nm or less, and became more remarkable as the distance Wb was narrowed. At the maximum impurity concentration Nb of 1 × 10 ¹⁶ / cm ³ , the elimination of the substrate floating effect was observed regardless of the distance Wb, but in the sample with the distance Wb of 50 nm or less, about 10 ¹² A under the condition of the drain voltage of 2V. A slight leak current of the source and drain was observed. The above leak current does not pose a problem in digital circuit applications, but must be used carefully in analog circuits. When the above results are summarized as numerical values, the maximum impurity concentration Nb and n from the end of the crystal defect region 11 are n.
The product Nb × Wb of the distance Wb to the low-concentration diffusion layer 9 junction is 1 × 10 ¹³ / cm ² or less, preferably 1 × 10 ¹² / cm ^2.
Desirably.

Embodiment 5 FIG. 19 is a sectional view showing a manufacturing process of a semiconductor device according to another embodiment of the present invention, and FIG. 20 is a completed sectional view thereof. In Example 1, the single crystal Si layer 30 has a thickness of 500 nm.
After separating the active regions of the single-crystal Si film 30 from each other by forming the inter-element isolation insulating film 4 using the SOI substrate having the thickness of, the conductivity type is changed and the threshold voltage is changed in a part of the active region according to the desired circuit configuration. A low-concentration n-type region 31 is formed by performing voltage-controlled ion implantation. In the other active regions, B ion implantation with threshold voltage control was performed. The gate oxide film 5, the gate electrode 61, and the gate protective insulating film 7 were formed on the low-concentration n-type region 31 and the low-concentration p-type region 3 according to the second embodiment.
In this embodiment, a W film is used as the gate electrode 61. From this state, according to the second embodiment, the gate electrode 61
Was used as a mask for ion implantation. In the low-concentration p-type region 30, the above-mentioned ion implantation is P ion implantation for forming the low-concentration n-type diffusion layers 9 and 10 and As for forming the high-concentration n-type diffusion layers 91 and 101 according to the above embodiment. Ion implantation is performed, and in the low-concentration n-type region 31, the low-concentration p-type diffusion layers 90 and 100 are formed by B ion implantation and the high-concentration p-type diffusion layer 90 is formed.
The mold diffusion layers 92 and 102 were formed. Low-concentration n-type diffusion layers 9 and 10 and low-concentration p-type diffusion layers 90 and 10
0 was formed as it reached the oxide film 2, and its maximum impurity concentration was set so as to finally reach 1 × 10 ¹⁷ / cm ³ . After each ion implantation and the subsequent activation heat treatment,
A silicon nitride film was selectively left in the nMOS formation region, and a 100 nm-thick gate sidewall insulating film 8 of a silicon nitride film was formed only on the sidewall portion of the nMOS gate by anisotropic dry etching. Similarly, an oxide film is selectively left in the pMOS formation region, and pM is formed by anisotropic dry etching.
A 200 nm-thick gate sidewall insulating film 8 of an oxide film was formed only on the sidewall portion of the OS gate. The pMOS and n
The gate side wall insulating film 8 of the MOS may have the same film thickness and the same material if desired. After that, the gate electrode 6
1. Using the gate sidewall insulating film 8 as a mask, Ar ions with a dose amount of 5 × 10 ¹⁵ / cm ³ are ion-implanted as they reach the interface of the oxide film 2, and low concentration n-type diffusion layers 9 and 10 and low concentration Inside the p-type diffusion layers 90 and 100, the high-concentration n-type diffusion layer 91,
The crystal defect region 11 was buried in a region isolated from the 101 and the high-concentration p-type diffusion layers 92 and 102. The crystal defect region 11 may be formed not by Ar ion implantation but by Si ion implantation or the like as in the second embodiment. Due to the influence of the underlying oxide film 2, in the crystal defect region 11, the region in contact with the underlying oxide film 2 was not single-crystallized even by the recrystallization heat treatment, and a polycrystalline crystal defect region was retained. The formation of the crystal defect region 11 has a role as a recombination center of minority carriers injected into the source region, and it does not need to become amorphous at the time of ion implantation, and heat treatment up to the final manufacturing process is performed. It is only necessary to obtain the condition that the crystal defects formed by the above are not completely recovered. From the above viewpoint, the ion implantation amount is preferably at least about 10 ¹⁴ / cm ² . Furthermore, defect formation by ion implantation of light elements such as He, H, and F is also effective (FIG. 19).

From the state shown in FIG. 19, according to the first embodiment, the wiring protective insulating film 13 is deposited and an opening is formed at a desired position, the wiring metal film is vapor-deposited, and the patterning thereof is performed to ground potential line 17, output terminal 18, and power supply. Wiring including the voltage line 19 was formed (FIG. 20).

In the semiconductor device, CMOS, according to the present embodiment manufactured through the above manufacturing steps, pMOS, nM
It was not possible to observe any symptom due to the floating effect of the substrate with any of the OSs. Furthermore, the SOI CM generated between the ground potential line 17 and the power supply voltage line 19 due to the negative fluctuation of the nMOS threshold voltage value and the positive fluctuation of the pMOS threshold voltage value.
No through-current due to the floating substrate effect peculiar to the OS was also observed. The substrate floating effect was not observed in the pMOS because electrons, which are minority carriers generated in the channel portion single crystal Si film 31, move in the low concentration p-type diffusion layer 100 and recombination centers in the crystal defect region 11. It is thought that it will disappear due to. In the semiconductor device according to the present embodiment, the substrate floating effect of nMOS and pMOS can be eliminated by the same ion implantation process, and the high performance of CMOS can be achieved at low cost without complicating the manufacturing process. I was able to.

In this embodiment, the gate side wall insulating film 8 for determining the distance between the crystal defect region 11 acting as a recrystallization center and the low concentration p-type region 3 under the channel or the low concentration n-type region 31. The film thicknesses of nMOS and pMOS are different. The above is the low concentration p-type diffusion layers 90 and 1.
No. 00 and the low-concentration n-type diffusion layers 9 and 10 have different junction depths for the purpose of correction.

In this embodiment, the low concentration p-type diffusion layer 90 is used.
And 100, and the maximum impurity concentration of the low-concentration n-type diffusion layers 9 and 10 is preferably 1 × 10 ¹⁵ / cm ³ or more and 1 × 10 ¹⁸ / cm ³ or less, and particularly 1 × 10 ¹⁶ to 5 × 10 5.
It is preferably in the range of ¹⁷ / cm ³ . This is 5x1
At 0 ¹⁷ / cm ³ or less, elimination of the substrate floating phenomenon is particularly remarkable, while at 1 × 10 ¹⁶ / cm ³ or less, p
A minute current of about 1/10 ¹² A is generated in the reverse characteristic of the n-junction, which may cause a leak current of the transistor.

Further, the ion implantation step for forming the crystal defect region 11 may be performed once even in the CMOS, and the ion implantation element is also the low concentration p-type diffusion layers 90 and 100 and the low concentration n.
Any material that does not change the conductivity type in the type diffusion layers 9 and 10 may be used, such as Si, Ge, C, and the like of Group 14 elements, and halogen elements such as F and Cl, and He, Ne, Ar, and the like. A rare gas element or the like is desirable.

Embodiment 6 FIG. 21 is a sectional view showing a manufacturing process of a semiconductor device according to another embodiment of the present invention, and FIG. 22 is a completed sectional view thereof. In this example, a semiconductor device was manufactured based on Example 5, but a fully depleted complementary MOS field effect transistor was manufactured by using an ultrathin SOI substrate having a single crystal Si film 30 with a thickness of 100 nm. In this embodiment, the junction depth of the source high-concentration n-type diffusion layer 91 and the high-concentration p-type diffusion layer 102 is set to about 50 nm. The bottoms of the low-concentration n-type diffusion layer 9 and the low-concentration p-type diffusion layer 90 are formed on the base oxide film 2.
The maximum impurity concentration is 1 × 10 ¹⁶
Was set to 2 × 10 ¹⁷ / cm ³ . nMO
In the low-concentration n-type diffusion layer 9 adjacent to the lower part of the S source high-concentration n-type diffusion layer 91, and in the pMOS, the source high-concentration p
In the low-concentration p-type diffusion layer 90 adjacent to the lower portion of the type diffusion layer 102, a recombination center region 11 made of a crystal defect layer was formed by the Si ion implantation process according to the fifth embodiment so as to be in contact with the underlying oxide film 2. In the present embodiment, prior to the Si ion implantation step, as in the maximum concentration depth of Si ion implantation, in the lower region of the nMOS source high concentration n-type diffusion layer 91, B ions of pMOS source high concentration are formed. P ions were selectively ion-implanted in the lower region of the p-type diffusion layer 102. The above B and P ion implantations have a maximum concentration of 1 × 10
^The dose amount was set to be ¹⁸ / cm ³ (Fig. 2
1).

From the state shown in FIG. 21, the wiring protection insulating film 13 is formed according to the fifth embodiment, and an opening is formed at a desired position.
Further, the wiring including the ground potential line 17, the output terminal 18, and the power supply voltage line 19 was formed by vapor deposition of the wiring metal film and its patterning (FIG. 22).

In the semiconductor device, CMOS, according to the present embodiment manufactured through the above manufacturing steps, pMOS, nM
Similar to the fifth embodiment, no symptom caused by the substrate floating effect was observed in any of the OSs, but in the semiconductor device according to the present embodiment, the single crystal Si layer 3 is extremely thin, 100 nm, and the channel The substrate impurity concentration in the region is also set low. Therefore, due to the limitation of the amount of electric charge in the single crystal Si layer 3, the neutral region does not exist in the single crystal Si layer 3 in the channel region under the gate voltage condition equal to or higher than the threshold voltage, and the single crystal Si layer 3 is completely depleted. This is capable of effectively inducing mobile charges in the channel, which is a current drive source, and is suitable for increasing the current. That is, it is suitable for low voltage and high speed operation. In the semiconductor device according to the present embodiment, the above fully depleted SOIMO is produced without the substrate floating effect.
S can be provided at a low price only by the conventional semiconductor device manufacturing method.

Embodiment 7 FIGS. 23 to 24 are sectional views showing the steps of manufacturing a semiconductor device according to a seventh embodiment of the present invention, and FIG. 25 is a completed sectional view thereof. FIG. 26 is a circuit diagram showing a NAND gate circuit to which this embodiment is applied, and FIGS. 25, 23 and 24 are structural sectional views of the nMOS region surrounded by a dotted line in the figure. 5 on a supporting substrate 1 made of single crystal Si having a diameter of 12.5 cm
00nm thick silicon oxide film (simply called oxide film)
2 and 200 nm thick n conductivity type, resistivity 0.5 Ωcm
(Impurity concentration 1 × 10 ¹⁶ / cm ³ ), plane orientation (100)
On the SOI substrate composed of the single crystal Si layer 3 of the above, the element isolation insulating film 4, the gate oxide film 5 with a thickness of 5 nm, the n-type low resistance polycrystalline S by the known method for manufacturing a MOS field effect transistor.
Gate electrodes 60, 61 and 62 made of the i film and a gate protective insulating film 7 were formed. Prior to the formation of the gate oxide film 5, a threshold voltage value of 0.1 V is formed on the surface region of the gate electrode formation planned region 30 of the single crystal Si layer 3, and a punch through stop is formed on the lower region. B ion implantation for P was selectively performed by a resist mask. The gate length is 200 nm. The ion implantation is performed on the gate oxide film 5
You may carry out after formation of. PMOS (not shown)
The single crystal Si layer 3 in the region has p conductivity type and impurity concentration of 1 × 1.
Ion implantation was separately and separately performed so as to reach 0 ¹⁶ / cm ³ . From this state, the resist mask 12 covering a part of the pMOS structure region and a part of the nMOS source region, the gate protection insulating film 7, and the gate electrode 6 are used as an injection blocking mask to accelerate the acceleration energy of 15 keV and the dose amount. 5 × 10 ¹⁴ / cm ²
Under the above conditions, As ion implantation and subsequent heat treatment were performed to form a shallow junction first n-type high-concentration diffusion layer source and a drain 90 (FIG. 23).

From the state of FIG. 23, a 100 nm-thick deposition insulating film is formed on the entire surface, and the above-mentioned insulating film is selectively left only on the gate side wall portion by anisotropic dry etching to form the gate side wall insulation. The film 8 was formed. Again, a resist mask 1 for covering the pMOS structure planned region and a part of the nMOS source region.
2 and the gate protective insulating film 7 and the gate electrode 6 are used as implantation blocking masks, the second n-type high concentration diffusion layer sources 9 and 91 and the drain 10 are implanted with P ions and the resist mask is removed. It was formed by activation heat treatment. The junction depth of the second n-type high-concentration diffusion layer sources 9 and 91 and the drain 10 was finally about 100 nm. After that, B ions are implanted in the pMOS region using a resist mask to form a p-type high concentration diffusion layer source and a drain (not shown). Subsequently, a Ti film having a thickness of 30 nm is formed on the entire surface by sputtering, and then at 750 ° C. for 6 hours in a nitrogen atmosphere.
A heat treatment was performed for a short time of 0 second to selectively form the Ti silicide film 11 only on the exposed Si surface. After removing the unreacted Ti film on the oxide film with hydrogen peroxide solution, a heat treatment for reducing the resistance of the Ti silicide film 11 is performed at 850 ° C. in an Ar atmosphere.
It carried out for 60 seconds (FIG. 24).

From the state of FIG. 24, the wiring protection insulating film 13 is deposited by a silicon oxide film to which phosphorus is added, and the wiring protection insulating film 13 is opened to a desired position based on a known semiconductor device manufacturing method, and further, a wiring metal is formed. A wiring including the source electrode 14, the drain electrode 15 and the like was formed by vapor deposition and patterning thereof. (FIG. 25).

The source-drain breakdown voltage of the semiconductor integrated circuit device according to the present embodiment including the NAND circuit shown in the circuit diagram of FIG. 26 manufactured through the above manufacturing process is 4.7V.
In comparison with a conventional structure SOIMOS of the same size in which the p-type diffusion layer 11 in the source is not formed, the voltage is improved by about 1.5V.
It has been possible to secure a withstand voltage value equivalent to that of a MOS of the same size normally manufactured on a semiconductor substrate. Also, in the current / voltage characteristics, abnormal knot-like characteristics called kink characteristics were not observed, and the characteristics were normal. Furthermore, in terms of source / drain current / gate voltage characteristics, conventional SOI / MOS
The presence of a leak current at the low gate voltage observed in 1. was not observed. Further, the leak current and the threshold voltage value were not found to change even if the drain voltage was changed.
From these characteristics, the semiconductor integrated circuit device according to the present embodiment completely eliminates the characteristics associated with the floating body effect. Furthermore, the presence of the high melting point silicified film in the source region
The series resistance was reduced, and an SOI semiconductor integrated circuit device operating at high current with high current could be realized.

In each of the series-connected nMOS transistors of the NAND circuit according to this embodiment, the minority carrier elimination mechanism is not formed in the source region, but since the substrate has a common structure, the source of the end transistor is formed. Due to the functions of the minority carrier disappearance mechanisms 3 and 11 in the region, the phenomenon caused by the substrate floating effect could be eliminated.

In the semiconductor integrated circuit device according to the present embodiment, the single crystal Si layer 3 is relatively thick as 200 nm, and in the substrate region below the channel region, the depletion layer and the neutral region are applied even if the gate voltage above the threshold voltage is applied. Is a so-called partially depleted structure. Although the partially depleted structure is operated at a low voltage and at a high speed and is slightly lower than the fully depleted structure, it can be easily manufactured under the condition using the conventional semiconductor substrate in the manufacturing condition without increasing the number of manufacturing steps. In the semiconductor integrated circuit device according to this embodiment, it is possible to inexpensively provide the substrate floating countermeasure for the partially depleted structure MOS.

Embodiment 8 FIGS. 27 to 28 are sectional views showing the sequence of manufacturing steps of a semiconductor integrated circuit device according to another embodiment of the present invention, and FIG. 29 is its completed sectional view. In Example 7, after the formation of the element isolation insulating film 4, pMOS forming region 31 is p-type conductivity, an impurity concentration of 1 × 10 ¹⁶ / cm ³ to as comprising an ion implantation and heat treatment of the single-crystal Si layer 3 of B Applied to. Then, the single crystal S under the gate electrode formation planned region of the nMOS is formed.
As the threshold voltage value becomes 0.1 V in the surface region of the i layer 30,
Further, B ion implantation for punch-through stop was selectively applied to the lower region by a resist mask. pMO
In the single crystal Si layer 32 below the S gate electrode formation planned region, P ion implantation is performed in the surface region and the punch-through stop is performed in the lower region as the threshold voltage value becomes -0.1V. P ion implantation was selectively performed using a resist mask. Subsequently, the gate oxide film 5 and the gate electrode 6
0 and 62, formation of the gate protective insulating film 7 was carried out in the same manner as in the seventh embodiment.
PMOS formation planned area and nMOS after manufacturing according to
Of the source mask and the nMOS gate electrode 60 and the gate protection insulating film 7 are used as an injection blocking mask, and a low acceleration energy of 2 keV of As and a high concentration of ions. Injection, resist film 1
By the activation heat treatment performed after the removal of 2
A shallow junction n-type high-concentration diffusion layer 90 having a surface impurity concentration of 1 × 10 ²¹ / cm ³ was formed (FIG. 27).

From the state shown in FIG. 27, the resist mask 12, the pMOS gate electrode 62, and the gate protective insulating film 7 which are arranged so as to cover the nMOS formation planned region and a part of the pMOS source region, serve as an injection blocking mask. Ion implantation using BF ₂ as an implantation source and heat treatment after the removal of the resist film 12 are performed to form the first p-type high-concentration diffusion layers 100 and 10 having an extremely shallow junction.
1 was formed. Then, according to the first embodiment, 100n
After forming the gate side wall insulating film 8 of m thickness, pMOS is formed again.
A resist mask 12 is provided so as to cover the region and a part of the nMOS source region.
A gate electrode 60 of S, a second n-type high-concentration source diffusion layer 90 having a junction depth of 100 nm, and a high-concentration drain by P ion implantation using the protective insulating film 7 as an implantation blocking mask and subsequent heat treatment. The diffusion layer 92 was formed. Furthermore, nMOS
The resist mask 12 arranged so as to cover the region and a part of the pMOS source region is provided again, and the resist mask and p
A second p-type high-concentration source diffusion layer 102 having a junction depth of 100 nm is formed by ion implantation of BF _{2 using} the MOS gate electrode 62, the gate protection insulating film 7 as an implantation blocking mask, and subsequent heat treatment, and A high concentration drain diffusion layer 105 was formed (FIG. 28).

The n-type low concentration S exposed from the state of FIG.
i layer 3, n-type high-concentration source diffusion layer 90, n-type high-concentration drain diffusion layer 92, p-type high-concentration drain diffusion layer 105, p
A W film 111 having a thickness of 80 nm1 was selectively deposited on each surface of the high-concentration type source diffusion layer 102 and the p-type low-concentration Si layer 31. The W film 111 may be formed not by the selective deposition method, but may be patterned by, for example, selectively depositing it at a desired location after the entire surface deposition. Furthermore, the W film 11
1 is another metal film such as Ti, Ta, Mo, Al, or T
It may be a low resistance metal compound such as iN or WN. Finally, an electrode including a ground potential line 14, an output terminal 18, and a power supply potential line 15 made of a wiring metal material after the wiring protection insulating film 13 is deposited and an opening is formed at a desired position based on a known semiconductor device manufacturing method. , And a wiring layer were formed (FIG. 2
9).

In the semiconductor integrated circuit device according to the present embodiment manufactured through the above manufacturing steps, no characteristic associated with the floating body effect was observed, and normal partial depletion type SOIMOS characteristics could be obtained. In particular, in the semiconductor integrated circuit device of this embodiment, the W film 111 has an n-type or p-type impurity of the n-type high-concentration source diffusion layer 90 or the p-type high-concentration source diffusion layer 1.
It is not imported from 02. The minority carrier injection barrier due to the accumulation of the high-concentration non-impurity layer at the interface between the n-type low-concentration Si layer 3 or the p-type low-concentration Si layer 31 and the W film 111 is not formed, and the substrate is more efficient than that in the first embodiment. I was able to eliminate the floating effect.

Embodiment 9 FIG. 30 is a completed sectional view of a semiconductor device according to another embodiment of the present invention. In this embodiment, the semiconductor integrated circuit device was manufactured according to the second embodiment, but the silicide film of the refractory metal was formed in the same manner as in the seventh embodiment instead of the W film 111 in the eighth embodiment. In this embodiment, the tungsten silicide film 111 is formed on the exposed single crystal Si layer by the thermal reaction of the W film entirely deposited. After that, the wiring protection insulating film 13 was deposited and an opening was formed at a desired position. However, B ions were selectively implanted into the connection opening to the tungsten silicide film 111 on the nMOS source, and the subsequent heat treatment was performed to remove tungsten. The p-type diffusion layer 10 is formed in the p-type low-concentration Si region 3 on the bottom surface of the silicide film 111.
3 was formed. Then, according to the second embodiment, an electrode including the ground potential line 14, the output terminal 18, and the power supply potential line 15 and a wiring layer made of a wiring metal material were formed. B above
In the formation of the p-type diffusion layer 103 by ion implantation, the n-type impurity from the high-concentration n-type diffusion layer adjacent to the surface of the n-type low-concentration region 3 is diffused through the metal silicide film 111 to increase the n-type concentration. For the purpose of compensating for a low concentration of n
Even a mold diffusion layer can be used (FIG. 30).

In the semiconductor integrated circuit device according to the present embodiment manufactured through the above manufacturing steps, the characteristics associated with the floating body effect are not observed, and the semiconductor integrated circuit device according to the present embodiment does not have a normal characteristic. It was possible to obtain SOIMOS characteristics. Particularly, the effect of eliminating the substrate floating effect is remarkable as compared with the first embodiment, and the reproduction yield of the reduction of the leak current at the low gate voltage is further improved. This is because the n-type impurities from the high-concentration n-type diffusion layer in which the barrier between the metal silicide film 111 and the n-type diffusion layer 3 is adjacent to each other in Example 7 are increased in n-type concentration by diffusion through the metal silicide film 111. The tendency to increase the hole injection barrier, that is, the degree to which the substrate floating effect is eliminated is present depending on the manufacturing conditions such as further increasing the concentration of the n-type high-concentration source diffusion layer 9. In the structure of this embodiment, the existence of the p-type diffusion layer 103 for holes injected into the n-type low-concentration region 3 does not depend on the manufacturing conditions of the n-type high-concentration source diffusion layer 9, etc. Silicized film 1
It is considered that this is to lower the barrier between the n-type diffusion layer 3 and the n-type diffusion layer 3 and promptly promote injection / recombination into the metal silicide film 111.

Embodiment 10 FIG. 31 is a diagram showing the structure of a semiconductor device according to another embodiment of the present invention. The present embodiment is an example applied to a random writing / reading type memory device (referred to as DRAM) configured by the semiconductor device according to the present invention described in the first to ninth embodiments. In the figure, a memory cell, which is one memory unit, is composed of one semiconductor device according to the present invention and one capacitive element Cs connected in series as shown in the figure below. The bit line is a data transmission line and the input / output control word. -Connected to the power line. The occasional write / read type memory device is composed of a memory cell array in which memory cells are arranged in a matrix and a control peripheral circuit, and the peripheral circuit is also composed of the semiconductor device of the present invention. In order to reduce the number of address signal terminals for memory cell selection, the column address signal and the row address signal are shifted and multiplexed and applied. RAS and CAS are pulse signals, respectively, which control the clock generators 1 and 2 to output address signals to the row decoder.
It is distributed to the liner and the line recorder. An address buffer, which is a buffer circuit, selects a specific word line and bit line according to the address signals distributed to the row decoder and the column decoder. A sense amplifier, which is a flip-flop type amplifier, is connected to each bit line and amplifies the signal read from the memory cell. The pulse signal WE controls the switching between writing and reading by controlling the writing clock generator. D is a write and read signal.

Since each of the semiconductor devices constituting the semiconductor device of this embodiment is the semiconductor device according to the present invention described in claims 1 to 5, the access time can be reduced by 30% or more as compared with the conventional one, and high speed performance can be realized. . Furthermore, the refresh characteristic is 0.
The time was 5 seconds, which was about 10 times higher than the conventional one.
It is considered that the above-mentioned high-speed operation is due to the parasitic capacitance reducing effect of the SOI structure and the large current according to the sixth embodiment. It is considered that the improvement of the refresh characteristic is based on the reduction of the junction area due to the SOI structure and the elimination of the threshold voltage fluctuation due to the elimination of the substrate floating effect.

Embodiment 11 FIG. 32 is a diagram showing the structure of a semiconductor device according to another embodiment of the present invention. The present embodiment is an example applied to a constant write / read type memory device (referred to as SRAM) configured by the semiconductor device according to the present invention described in the first to ninth embodiments. In the figure, a memory cell, which is one storage unit, is composed of two sets of complementary MOSs according to the present invention and two MOSs (referred to as transfer MOSs) for controlling signal input / output as shown in the figure below. This SRAM is composed of a memory cell array in which memory cells are arranged in a matrix and a peripheral circuit for control, and the peripheral circuit is also composed of the semiconductor device of the present invention. The configuration of this embodiment is basically the same as that of the tenth embodiment, but an address transition detector is provided in order to achieve high speed and low power consumption of SRAM, and the internal circuit is generated by the pulse generated by the address transition detector. Are in control. Furthermore, in order to speed up the circuit from the address buffer to the decoder, the row decoder is composed of two stages, a predecoder and a main decoder. Chip select is signal CS and WE
Is a circuit for avoiding contention of data at the time of writing and reading information, and making the write cycle time and the read cycle time almost the same to enable high speed operation.

By using the semiconductor device according to the present invention described in Embodiments 1 to 9 as each semiconductor device constituting the semiconductor device of this embodiment, the power supply voltage is changed from 3.5V to 2.0V.
It was possible to reduce the access time and reduce the access time by 30% or more compared with the conventional one, thus realizing high speed. It is considered that the above is due to the parasitic capacitance reducing effect of the SOI structure. Further, it is considered that the fluctuation of the threshold voltage due to the elimination of the substrate floating effect is eliminated, and the operation range of the sense amplifier is reduced to enable the speedup.

Embodiment 12 FIG. 33 is a diagram showing the structure of a semiconductor device according to another embodiment of the present invention. The present embodiment is an example applied to a logic circuit device constituted by the semiconductor device according to the present invention described in the first to ninth embodiments. Although the figure shows an example of a composite gate circuit, the semiconductor device according to the present invention is used to form a NAN in the composite gate circuit.
It was applied to a logic circuit including a D circuit and a NOR circuit. The composite circuit shown in the figure is a circuit for performing a logical operation of Vout = V ₁ × V ₂ + V ₃ × V ₄ , and the number of transistors can be reduced to half compared to the case where the above operation is configured by a combination of a NAND circuit and a NOR circuit.

Since each of the semiconductor devices constituting the semiconductor device of this embodiment is the semiconductor device according to the present invention according to claims 1 to 5, the delay time is reduced by 20% or more as compared with the conventional logic circuit device. Was given. It is considered that the above is due to the parasitic capacitance reducing effect of the SOI structure, the increase in the current based on the fourth embodiment, and the drastic improvement of the drain conductance at a low voltage.

Embodiment 13 FIG. 34 is a diagram showing the structure of a semiconductor device according to another embodiment of the present invention.

The present embodiment relates to a signal transmission processing device constituted by the semiconductor device according to the present invention described in the first to ninth embodiments, and in particular, an asynchronous transmission system (called an ATM switch).
It is a signal transmission processing device. In FIG. 34, an information signal transmitted at a high speed in series by an optical fiber is converted into an electric signal (O / E conversion) and is parallelized (S / P conversion) through a device. It was introduced into an integrated circuit (BFMLSI) composed of the semiconductor device according to the present invention described in Examples 1 to 9. The electric signal subjected to the addressing process in the integrated circuit is serialized (P / S conversion) and converted into an optical signal (E / O conversion) and output through the optical fiber. The BFMLSI is a multiplexer (MUX), a buffer memory (B
FM) and a separator (DMUX). The BFM LSI is controlled by a memory control LSI and an LSI having an empty address allocation control function (empty address FIFO memory LSI). This signal transmission processing device is a device having a function of a switch for transmitting an ultra high speed transmission signal sent to a desired address at an ultra high speed regardless of an address to be transmitted. Since the operation speed of BFMLSI is significantly slower than the transmission speed of the input optical signal, the input signal cannot be directly switched, the input signal is temporarily stored, and the stored signal is switched and then converted into an ultra-high-speed optical signal. A method of transmitting to a desired address is used. If the operation speed of the BFMLSI is slow, a large storage capacity is required. In the ATM switch according to the present embodiment, the BFMLSI is composed of the semiconductor device according to the present invention described in the first to ninth embodiments, so that the operating speed is three times as high as that of the conventional BFMLSI and the cost is low. Therefore, the storage capacity of the BFMLSI can be reduced to about 1/3 of the conventional one.
As a result, the manufacturing cost of the ATM switch could be reduced.

Embodiment 14 Another embodiment will be described with reference to the computer block diagram of FIG. The present embodiment is an example in which the semiconductor device of the present invention is applied to a high-speed large-scale computer in which a plurality of processors 500 for processing instructions and operations are connected in parallel. In this embodiment, the semiconductor device according to the present invention has a higher degree of integration and is less expensive than a conventional integrated circuit using bipolar transistors. Therefore, the processor 500 for processing instructions and operations, the system controller 501, and the main memory 502. Etc. are formed by the semiconductor device of the present invention having one side of 10 to 30 mm.

Processor 5 for processing these instructions and operations
00, a system controller 501, and a data communication interface 503 composed of a compound semiconductor device are mounted on the same ceramic substrate 506. Further, the data communication interface 503 and the data communication control device 504 are mounted on the same ceramic substrate 507. The ceramic substrate on which these ceramic substrates 506 and 507 and the main memory device 502 are mounted is mounted on a substrate having a side of about 50 cm or less, and the central processing unit 5 of the computer is mounted.
08 was formed. The data communication in the central processing unit 508, the data communication between a plurality of central processing units, or the data communication between the data communication interface 503 and the board 509 on which the input / output processor 505 is mounted is performed. Communication was performed via an optical fiber 510 indicated by double-ended arrow lines in the figure.

In this computer, semiconductor devices according to the present invention, such as a processor 500 for processing instructions and operations, a system controller 501, and a main memory 502, operate in parallel and at high speed, and data communication is performed optically. Since it is performed on a medium, the number of instruction processings per second can be significantly increased.

[0085]

According to the present invention, the fluctuation of the threshold voltage due to the substrate floating effect, which is the greatest drawback of the semiconductor device formed on the SOI substrate, and the occurrence of the abnormal bump-up characteristic in the current-voltage characteristic are occupied. An inexpensive semiconductor device can be manufactured by an existing semiconductor device manufacturing device without increasing the area and using an unstable ion source such as Ge ion implantation in the source and requiring a dedicated device. be able to. Further, according to the present invention, pMO on an SOI substrate, which has heretofore been impossible, is obtained.
The substrate floating effect of S can be solved by an inexpensive manufacturing method. Therefore, according to the present invention, the floating body effect can be completely eliminated by a low-cost manufacturing method for the CMOS on the SOI substrate. This allows low voltage,
It is possible to provide an ultra-high speed semiconductor device with no power consumption and a system configured by the semiconductor device.

[Brief description of the drawings]

FIG. 1 is a completed sectional view of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view of a conventional semiconductor device.

FIG. 3 is an energy band diagram for explaining a substrate floating effect elimination mechanism in a conventional semiconductor device.

FIG. 4 is a sectional view of a source diffusion layer for explaining a substrate floating effect eliminating mechanism in a semiconductor device of the present invention.

FIG. 5 is an energy band diagram for explaining a substrate floating effect elimination mechanism by the semiconductor device of the present invention.

FIG. 6 is an analysis result regarding a substrate floating effect elimination mechanism by the semiconductor device of the present invention.

FIG. 7 is an equivalent circuit diagram illustrating a substrate floating effect eliminating mechanism in the semiconductor device of the present invention.

FIG. 8 is an analysis result regarding a substrate floating effect elimination mechanism by the semiconductor device of the present invention.

FIG. 9 is a sectional view of a source diffusion layer for explaining a substrate floating effect eliminating mechanism in a semiconductor device of the present invention.

FIG. 10 is a sectional view showing a sequence of manufacturing steps for a semiconductor device according to the first embodiment of the present invention.

FIG. 11 is a sectional view showing a sequence of manufacturing steps for a semiconductor device according to the first embodiment of the present invention.

FIG. 12 is a cross-sectional view showing the sequence of manufacturing steps for a semiconductor device according to the first embodiment of the present invention.

FIG. 13 is a sectional view showing the sequence of manufacturing steps for a semiconductor device according to the second embodiment of the present invention.

FIG. 14 is a completed sectional view of a semiconductor device according to a second embodiment of the present invention.

FIG. 15 is a completed sectional view of a semiconductor device according to a third embodiment of the present invention.

FIG. 16 is a sectional view showing the sequence of manufacturing steps for a semiconductor device according to the fourth embodiment of the present invention.

FIG. 17 is a sectional view showing the sequence of manufacturing steps for a semiconductor device according to the fourth embodiment of the present invention.

FIG. 18 is a completed sectional view of a semiconductor device according to a fourth embodiment of the present invention.

FIG. 19 is a sectional view showing the sequence of manufacturing steps for a semiconductor device according to the fifth embodiment of the present invention.

FIG. 20 is a completed sectional view of a semiconductor device according to a fifth embodiment of the present invention.

FIG. 21 is a sectional view showing the sequence of manufacturing steps for a semiconductor device according to the sixth embodiment of the present invention.

FIG. 22 is a completed sectional view of a semiconductor device according to a sixth embodiment of the present invention.

FIG. 23 is a sectional view showing a sequence of manufacturing steps for a semiconductor device according to a seventh embodiment of the present invention.

FIG. 24 is a sectional view showing a sequence of manufacturing steps for a semiconductor device according to a seventh embodiment of the present invention.

FIG. 25 is a completed sectional view of the semiconductor device according to the seventh embodiment of the present invention.

FIG. 26 is a circuit diagram of a semiconductor device according to a seventh embodiment of the present invention.

FIG. 27 is a sectional view showing the sequence of manufacturing steps for a semiconductor device according to the eighth embodiment of the present invention.

FIG. 28 is a sectional view showing a sequence of manufacturing steps for a semiconductor device according to an eighth embodiment of the present invention.

FIG. 29 is a completed sectional view of a semiconductor device according to an eighth embodiment of the present invention.

FIG. 30 is a completed sectional view of a semiconductor device according to a ninth embodiment of the present invention.

FIG. 31 is a block diagram of an occasional write / read memory device for explaining a tenth embodiment of the present invention.

FIG. 32 is a configuration diagram of a constant write / read storage device for explaining an eleventh embodiment of the present invention.

FIG. 33 is a configuration diagram of a logic circuit device for explaining a twelfth embodiment of the present invention.

FIG. 34 is a configuration diagram of an asynchronous transmission mode system for explaining a thirteenth embodiment of the present invention.

FIG. 35 is a computer configuration diagram for explaining the 14th embodiment of the present invention.

[Explanation of symbols]

1 ... Support substrate, 2 ... Oxide film, 3 and 30 ... Single crystal Si
Layers, 4 ... Element isolation insulating film, 5 ... Gate oxide film, 6 ... Gate electrode, 7 ... Gate protective insulating film, 8 ... Gate sidewall insulating film, 9 and 10 ... Low concentration n Mold diffusion layers, 11 and 111 ...
Recombination center region, 12 ... W film, 13 ... Wiring protection insulating film,
14 ... Source electrode, 15 ... Drain electrode, 16 ... SiG
e eutectic layer, 17 ... Ground potential line, 18 ... Output terminal, 19 ...
Power supply voltage line, 31 ... N-type region, 32 ... P-type region, 33 ...
n type low concentration diffusion layer, 90 and 100 ... p type diffusion layer, 91
And 101 ... high-concentration n-type diffusion layer, 92 and 102 ... high-concentration p-type diffusion layer, 110 ... n-type diffusion layer, 121 ... silicide layer, 500 ... processor, 501 ... system control device, 502 ... main memory device, 503 Data communication interface, 504 Data communication control device, 505 Input / output processor, 506 Ceramic board, 507 Ceramic board, 508 Central processing unit, 509 Input / output processor mounting board, 510 Optical fiber for data communication.

Claims (24)

[Claims] 1. A semiconductor device in which at least a MOS field effect transistor is provided in a single crystal semiconductor layer separated from a support substrate by an insulating film, wherein a source diffusion layer of the first conductivity type of the transistor is a source diffusion layer. -A first diffusion layer connected to the electrode, and a second diffusion layer in a low impurity concentration region adjacent to at least a lower region of the first diffusion layer, and inside the second diffusion layer Is a semiconductor device having a region having a recombination center mechanism for electric charges. 2. The semiconductor device according to claim 1, wherein the region having the recombination center mechanism has a second conductivity type. 3. A semiconductor device according to claim 1, wherein a minimum distance Wb between a region of the second conductivity type immediately below the gate electrode of the transistor and a region having the recombination center mechanism, and the minimum distance. A semiconductor device, wherein the product Wb × Nb of the maximum impurity concentration Nb of the second diffusion layer forming the space is 1 × 10 ¹³ / cm ² or less. 4. A semiconductor device in which a first conductivity type MOS field effect transistor and a second conductivity type MOS field effect transistor are provided in a single crystal semiconductor layer separated from a supporting substrate by an insulating film. The source diffusion layer of the first conductivity type of the one conductivity type MOS field effect transistor is adjacent to the first diffusion layer connected to the source electrode and at least the lower region of the first diffusion layer. The second diffusion layer in the low impurity concentration region,
A semiconductor device, wherein a region of the first conductivity type or a second conductivity type having a recombination center mechanism for electric charges is provided inside the second diffusion layer. 5. The semiconductor device according to claim 4, wherein the source diffusion layer of the second conductivity type of the second conductivity type MOS field effect transistor has a third diffusion connected to a source electrode. A layer and a fourth diffusion layer in a low impurity concentration region adjacent to at least a lower region of the third diffusion layer, and having a recombination center mechanism for charges inside the fourth diffusion layer,
A semiconductor device having a region of the first conductivity type or the second conductivity type. 6. A step of forming an element isolation insulating film on a single crystal semiconductor layer separated from a support substrate by an insulating film to form a group of single crystal semiconductor layer regions electrically isolated from each other; -Type MOS field effect transistor forming the single-crystal semiconductor layer region group, a second conductivity type impurity is formed at a desired portion, and the second-conductivity-type MOS field-effect transistor forming group is formed. Of the first conductivity type impurities at desired locations of the gate electrode, a step of forming a gate insulating film and a gate electrode, and a first conductivity type MOS using the gate electrode as a mask. -Type field-effect transistor forming a single-crystal semiconductor layer region group on the surface of which a first-conductivity-type high-concentration impurity region and a second-conductivity-type MOS field-effect transistor forming group are formed. Second conductivity type on the surface of Forming a high-concentration impurity region, forming a second-conductivity type region in the first-conductivity-type low-impurity-concentration region adjacent to the first-conductivity-type high-concentration impurity region, and An ion implantation step of forming a crystal defect region that acts as a recombination center so as to be adjacent to the insulating film on the support substrate inside the region of the second conductivity type. 7. The method of manufacturing a semiconductor device according to claim 6, wherein a step of forming a second conductivity type region adjacent to the first conductivity type high concentration impurity region and in a region below the region is performed. A method for manufacturing a semiconductor device, characterized by not performing. 8. The method of manufacturing a semiconductor device according to claim 6, wherein the first-conductivity-type high-concentration impurity region and the second-conductivity-type high-concentration impurity region are formed on the surface of the single crystal semiconductor layer region group. And a step of forming a first-conductivity-type low-concentration impurity region adjacent to the first-conductivity-type high-concentration impurity region and in a region below the region. Manufacturing method. 9. The method of manufacturing a semiconductor device according to claim 6, wherein after the step of forming the second-conductivity-type high-concentration impurity region, the second-conductivity-type high-concentration impurity region is formed. Adjacent to, and a step of forming a second-conductivity-type low-concentration impurity region in one region below the region, and then re-forming in the second-conductivity-type low-concentration impurity region reaching the insulating film on the supporting substrate. A method of manufacturing a semiconductor device, comprising performing the ion implantation step of forming a crystal defect region acting as a bonding center. 10. The method of manufacturing a semiconductor device according to claim 9, wherein, prior to the step of forming a crystal defect region acting as the recombination center, a region adjacent to the second-conductivity-type high-concentration impurity region and below the region is formed. A method for manufacturing a semiconductor device, comprising the step of converting one region into a region of a second conductivity type, which is to be a crystal defect region acting as a recombination center in a low-concentration impurity region, into a first conductivity type. 11. The method of manufacturing a semiconductor device according to claim 6, wherein the crystal defect region acting as a recombination center is formed by any one of a Group 14 element, a halogen element and a rare gas element. A method for manufacturing a semiconductor device, which is formed by ion implantation of an element. 12. The method of manufacturing a semiconductor device according to claim 11, wherein the ion implantation is performed by using a gate sidewall insulating film as an implantation blocking mask. 13. The method of manufacturing a semiconductor device according to claim 11, wherein the ion implantation is performed by using a contact hole for a source electrode to the source diffusion region as an implantation hole. Manufacturing method. 14. A semiconductor device in which a MOS field effect transistor is provided in each of a plurality of single crystal semiconductor layers separated from a supporting substrate by an insulating film and separated from each other, wherein a source region of the transistor is a first region. One conductivity type first diffusion layer, a first conductivity type low impurity concentration region adjacent to at least a lower region of the diffusion layer, the first diffusion layer, and the first conductivity type low impurity concentration region A semiconductor device comprising a refractory metal film or a refractory metal silicide film on the surface. 15. The semiconductor device according to claim 14, wherein
The transistor has a plurality of MOs in the same single crystal semiconductor layer.
The source region of the transistor connected in series with the S-type field effect transistor is a first conductivity type first diffusion layer and a refractory metal film on the surface of the first diffusion layer, or a refractory metal. A semiconductor device comprising a silicide film. 16. A first group and a second group of single crystal semiconductor layers separated from the supporting substrate by an insulating film and separated from each other, wherein the first group of single crystal semiconductor layers have a first conductivity type. MOS
Type field effect transistor, wherein the second conductivity type MOS field effect transistor is provided in the second group of single crystal semiconductor layers, the source of the first conductivity type MOS field effect transistor is
The first region is a first conductivity type first diffusion layer, a first conductivity type low impurity concentration region adjacent to at least a lower region of the diffusion layer, the first diffusion layer, and the first conductivity type A semiconductor device comprising a refractory metal film or a refractory metal silicide film on the surface of a low impurity concentration region. 17. The semiconductor device according to claim 14, wherein the refractory metal film or the refractory metal silicide film has the first conductivity type impurity region in one bottom region thereof. A semiconductor device characterized by being connected to a conductive type low impurity concentration region. 18. A semiconductor device according to any one of claims 1 to 5 or 14 to 17, wherein a capacitive element is connected to a node at one end of a MOS field effect transistor to form a unit of memory device. Semiconductor device. 19. A semiconductor device according to any one of claims 1 to 5 or 14 to 17, wherein a first transistor and a second transistor are connected to each other to form a pair, and two pairs form a unit storage device. A semiconductor device having a structure. 20. A semiconductor device comprising a semiconductor device according to any one of claims 1 to 5 or 14 to 17 as a logic circuit device. 21. A semiconductor device, characterized in that an asynchronous transmission mode device is constituted by the semiconductor device according to any one of claims 1 to 5 or 14 to 17. 22. A semiconductor device comprising a processor device comprising the semiconductor device according to any one of claims 1 to 5 or 14 to 17. 23. A single crystal semiconductor layer provided on an insulating film, first and second impurity doped regions having a first conductivity type and provided in the semiconductor layer so as to be separated from each other, A semiconductor having a gate insulating film provided on the single crystal semiconductor layer between the first and second impurity doped regions, and a gate electrode formed on the gate insulating film. In the device, a third conductive layer that is connected to the first impurity doped region, has a first conductivity type, and has a lower concentration than the first impurity doped region.
Connected to the single crystal semiconductor layer below the gate electrode via the impurity doped region of the gate electrode and mainly through the third impurity doped region, and the single crystal semiconductor below the gate electrode. A recombination region having a recombination rate higher than a generation rate of minority carriers generated in the layer, the semiconductor device further comprising: 24. A single crystal semiconductor layer provided on an insulating film, first and second impurity doped regions having a first conductivity type and provided in the semiconductor layer so as to be separated from each other, A semiconductor having a gate insulating film provided on the single crystal semiconductor layer between the first and second impurity doped regions, and a gate electrode formed on the gate insulating film. In the device, a third impurity doping region having a first conductivity type and having a concentration lower than that of the first impurity doping region is provided, and the third impurity doping region is provided in contact with the third impurity doping region. A semiconductor device further comprising a crystal defect layer.