JPH09135279A - Demodulator - Google Patents

Abstract

PROBLEM TO BE SOLVED: To detect and eliminate disturbance or distortion component by selecting a distortion elimination algorithm with a switching signal in response to a state of an input, signal to a waveform equalization circuit. SOLUTION: A 64QAM signal wave whose gain is automatically controlled is received from an input terminal 101 and subjected to orthogonal phase detection by an orthogonal synchronization circuit 102. In-phase axis I and orthogonal Q demodulation signals multiplexed in this orthogonal relation are outputted respectively to A/D converter circuits 103, 105 and DF circuits 104, 106. Then a waveform equalization circuit 107 selects the distortion elimination algorithm based on a changeover signal received from a switching signal terminal 110 to detect and eliminate disturbance or distortion component and I/Q axis 3-bit digital data signals are outputted from output terminals 108, 109. Thus, in the case of demodulating an orthogonal amplitude modulation wave, proper waveform equalization is applied to each state of the input signal given to the waveform equalization circuit and disturbance and distortion component caused on the way of transmission line is stably and effectively compensated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a demodulation device for demodulating an amplitude modulation wave or a quadrature amplitude modulation wave, and more particularly to waveform equalization for stably and effectively compensating for an interference or distortion component that occurs in the middle of a transmission path. The present invention relates to a demodulation device including a circuit.

[0002]

2. Description of the Related Art Generally, a demodulator for demodulating a quadrature amplitude modulated wave has a waveform equalizing circuit for compensating for a disturbance or distortion component generated in the middle of a transmission path. Various methods have been proposed for this distortion removal algorithm for waveform equalization. For example, IEE Transactions on Communications, VOL. CMO-28, N.O. 11 (November 1980)
Pages 1867 to 1875 (IEEE T
RANSACTIONS ON COMMUNICAT
IONS, VOL. COM-28, NO. 11, NOV
EMBER1980 PP1867-1875) self-recovering equalization and carrier tracking in two-dimensional
Data Communication Systems (Self-
Recovering Equalization a
nd Carrier Tracking in Tw
o-Dimensional Data Commun
ication Systems) and I / E / E / Transactions on Signal Processing, VOL. 40, N.O. 6 (1
June 992) Pages 1383 to 1398 (IEEE TRANSACTIONS ON SIG)
NAL PROCESSING, VOL. 40, NO.
6, JUNE 1992 PP1383-1398) Joint blind equalization, carrier recovery, and timing recovery fore high-order QAM signal constellations (Joint Blind Equ)
alignment, Carrier Recover
y, and Timing Recovery for
High-Order QAM Signal Co
nstellations),
In these documents, as a typical distortion removal algorithm,
CMA (Constant Modulus Algo)
rithm) and DD (Decision-Direct)
ed Algorithm) is introduced. Table 1 shows these operating principles.

[0003]

[Table 1]

CMA is a processing method based on the distance from the center of a coordinate plane composed of an in-phase axis and a quadrature axis.
Is a processing method with reference to a position on a coordinate plane composed of an in-phase axis and an orthogonal axis. The CMA can operate even if the carrier phase is uncertain, but the DD does not operate normally. Further, in the state where the carrier wave phase is normally locked, the distortion removal capability of the DD tends to be higher than that of the CMA.

[0005]

As described above, the distortion elimination algorithms have their respective advantages and disadvantages. Therefore,
There is a problem that the removal operation may not normally converge depending on the demodulation state of the quadrature amplitude modulation wave.

An object of the present invention is to demodulate a quadrature amplitude modulation wave when the states of the input signals input to the waveform equalization circuit are different, for example, the state where carrier wave reproduction is not locked and the state where carrier wave reproduction is locked. The optimum waveform equalization is performed for each state of.

[0007]

In order to achieve the above object, the present invention is a demodulator for demodulating a quadrature amplitude modulated wave, wherein the quadrature amplitude modulated wave is quadrature phase demodulated, and the quadrature axis and the quadrature axis are respectively used. Demodulation means for outputting first and second signals and the first signal and the second signal are input, interference and distortion components are removed from the first signal, and quadrature modulation is performed on the modulation side. A third signal including the first main demodulation signal and a fourth signal including the second main demodulation signal quadrature-modulated on the modulation side are output by removing interference and distortion components from the second signal. Waveform equalizing means, arithmetic means for controlling the waveform equalizing means using the first signal, the second signal, the third signal and the fourth signal, and input to the arithmetic means And a control means for controlling the calculation method of the calculation means according to the switching signal. That.

The demodulating means outputs the first and second signals from the in-phase axis side and the quadrature axis side which are in an orthogonal relationship.

The waveform equalizing means receives the first signal and the second signal, removes interference and distortion components from the first signal, and includes a first main demodulation signal quadrature-modulated on the modulation side. Interference and distortion components are removed from the third signal and the second signal, and a fourth signal including the second main demodulation signal quadrature-modulated on the modulation side is output.

The arithmetic means uses the first signal, the second signal, the third signal and the fourth signal to control the waveform equalizing means.

The control means controls the calculation method of the calculation means by the switching signal inputted to the calculation means.

In the first state of the switching signal, the arithmetic means is
A first distortion removal algorithm (CMA) and a second distortion removal algorithm (D) different from the first waveform equalization operation in the second state of the switching signal different from the first state.
Perform D).

Further, an evaluation signal indicating whether or not the sync signal can be detected is used as a switching signal. When the sync signal cannot be detected, the first state is set. When the sync signal is detected, the second state is set. State.

Alternatively, an evaluation signal indicating whether or not the reproduced carrier signal can be reproduced is used as a switching signal,
The first state is when the reproduced carrier signal cannot be reproduced, and the second state is when the reproduced carrier signal can be reproduced.

Alternatively, an evaluation signal indicating whether or not a code error amount is detected above a certain reference amount or not is used as a switching signal, and when an error above a certain reference amount is detected, the first state is set, When the error is less than a certain reference amount, the second state is set.

Since the control method for waveform equalization is switched as described above, the waveform equalization operation can be effectively performed.

[0017]

Embodiments of the present invention will be described below.

The embodiment shown in FIG. 1 is a demodulator for 64QAM which is one of multi-valued quadrature amplitude modulated waves. In FIG. 1, 101 is a 64QAM signal wave input terminal, 102 is a quadrature synchronous detection circuit, 103 and 105 are analog-digital conversion circuits (hereinafter abbreviated as A / D conversion circuits), 104 and 1.
Reference numeral 06 is a digital filter circuit (hereinafter abbreviated as DF circuit), 107 is a waveform equalizing circuit, and 108 and 109 are 64.
QAM demodulation digital data data output terminal, 110 is a switching signal input terminal.

From the input terminal 101, the A / D conversion circuit 1
A 64QAM signal wave whose automatic gain control is performed so that the optimum level is obtained by the input of 03 and 105 is input. 64QAM
The signal wave is quadrature-phase detected by the quadrature synchronous detection circuit 102,
In-phase axes that were multiplexed in an orthogonal relationship (hereinafter abbreviated as I axis)
Side demodulation signal and the orthogonal axis (hereinafter abbreviated as Q axis) side demodulation signal are output to the A / D conversion circuits 103 and 105, respectively. The A / D conversion circuits 103 and 105 convert the input analog signals into digital signals and use them as D.D. F. Output to the circuits 104 and 106. D.
F. The circuits 104 and 106 have frequency characteristics that extract the transmission band of digital data and block the other bands, and do not cause intersymbol interference in the output digital signal. D. F. The output signals of the circuits 104 and 106 are input to the waveform equalization circuit 107. The waveform equalization circuit 107 detects an interference or distortion component generated in the middle of the transmission path or the like from the demodulated signal and removes it. Waveform equalization circuit 107
From each output data bus of
Digital data of 3 bits on the axis side and 3 bits on the Q axis side are obtained from output terminals 108 and 109, respectively. A switching signal is input from the switching signal input terminal 110, and the distortion removal algorithm of the waveform equalization circuit 107 is switched by this signal.

FIG. 2 shows an embodiment of the waveform equalization circuit 107. 201 is D.I. on the I-axis side. F. An input terminal of the output signal of the circuit 104, 202 is a D.D. F. Input terminals for the output signal of the circuit 106, 203, 204, 205 and 206 are transversal filter circuits (hereinafter abbreviated as TRF circuits), 207, 208, 209 and 210 are addition circuits and 2
11 is a signal output terminal after distortion removal on the I-axis side, 212 is a signal output terminal after distortion removal on the Q-axis side, 213 is a buffer circuit, and 214 is a central control circuit (hereinafter abbreviated as CPU circuit). .

The TRF 203 receives the signal on the I-axis side from the input terminal 201. The TRF 204 has an input terminal 20.
The signal on the Q-axis side is input from 2. The adder circuit 207 is
The I-axis side signal from the input terminal 201 and the output signal of the TRF 203 are input and addition processing is performed. This removes the distortion component included in the signal on the I-axis side and caused by the reflection of itself. After that, the addition circuit 208 receives the output signal of the addition circuit 207 and the output signal of the TRF 204, and performs addition processing. As a result, the crosstalk component included in the signal on the I-axis side and generated by the signal on the Q-axis side is removed.

Similarly, the TRF 206 has an input terminal 202.
The signal on the Q-axis side is input from. The TRF 205 receives the I-axis side signal from the input terminal 201. Addition circuit 2
09 is a signal on the Q-axis side from the input terminal 202 and TRF2
The output signal of 06 is input and addition processing is performed. As a result, the distortion component caused by the reflection of itself included in the signal on the Q-axis side is removed. Then, the adder circuit 210
Receives the output signal of the adder circuit 209 and the output signal of the TRF 205 and performs addition processing. As a result, the crosstalk component included in the signal on the Q-axis side and generated by the signal on the I-axis side is removed.

The output signal of the adder circuit 208 is output from the output terminal 211 as a signal after distortion removal on the I-axis side. Similarly, the output signal of the adder circuit 208 is output from the output terminal 212 as a signal after distortion removal on the Q-axis side.

TRF circuits 203, 204, 205, 20
6 is a CPU circuit 214 via a buffer circuit 213.
Is given the tap coefficient values calculated using the distortion removal algorithm.

The CPU circuit 214 has a switching signal input terminal 1
A switching signal from 10 switches the distortion removal algorithm.

Next, the operation of the CPU circuit 214 is shown in the flow chart of FIG.

First, on the main processing side, an initial reset is applied when the power is turned on, etc., and initial settings of hardware and software are performed. After this, the state of waiting for an interrupt is entered.

On the other hand, on the interrupt processing side, after the software initialization as the interrupt processing side is performed, it is determined whether or not to switch the processing.

When the process switching is not performed (NO), the tap coefficient is calculated and set by the first distortion removal algorithm after the data is captured, and the process switching determination is returned again.

When the processing is switched (YES), the intermediate processing is cleared and the main processing side is interrupted.

When the main processing side receives an interrupt, after the data is taken in, the tap coefficient is calculated and set by the second distortion removal algorithm. After this, a convergence judgment is made as to whether or not the distortion removal has been sufficiently performed, and if it is judged to be insufficient (in the case of NO), the tap coefficient is calculated again by the second distortion removal algorithm after the data acquisition. If it is set and judged to be sufficient (in the case of YES), it shifts to the monitoring mode. In the monitoring mode, the distortion amount is monitored, and the distortion removal operation using the second distortion removal algorithm is started again when the distortion amount increases due to some influence.

According to the embodiments shown in FIGS. 1, 2 and 3, since the optimum distortion removal algorithm can be selected by the switching signal, waveform equalization can be performed stably and effectively depending on the situation.

FIG. 4 shows an embodiment of a circuit for generating a switching signal input to the input terminal 110 in FIG. 1, and FIG. 5 shows a transmission format required therefor. In FIG. 4, 401 is an input terminal for 3-bit digital data I2, I1, I0 on the I-axis side, and 402 is 3-bit digital data Q on the Q-axis side.
2, Q1 and Q0 input terminals, 403 is a data conversion circuit,
Reference numeral 404 is a parallel-serial conversion circuit (hereinafter, abbreviated as P / S circuit), 405 is a synchronization signal detection circuit, 406 is a digital signal processing circuit, 407 is an output terminal of processed data, and 408 is a synchronization signal detection circuit 405. This is the output terminal for the switching signal that is created.

I-axis and Q-axis digital data are input from the input terminals 401 and 402 and output to the data conversion circuit 403. The data conversion circuit 403 performs processing such as differential decoding and gray-natural code conversion on the input digital data, and outputs it to the P / S conversion circuit 404. The P / S conversion circuit 404 converts the input digital data into serial data. This serial data is structured as shown in FIG. A synchronization signal (denoted as Sync in FIG. 5) and a main data string (denoted as data in FIG. 5) form one frame, and the frames are continuous. The sync signal detection circuit 405 detects this sync signal and outputs a timing signal to the digital signal processing circuit 406. The digital signal processing circuit 406 extracts a main data string from the serial data with the timing signal as a reference, performs processes such as deinterleaving and error correction, and outputs it to the output terminal 407.

On the other hand, the sync signal detection circuit 405 produces a kind of lock detector signal indicating whether or not the sync signal could be detected from the serial data, and the output terminal 408.
Output to

Now, if the digital data is located at a point different from the normal discrimination point due to some influence, the serial data output through the data conversion circuit 403 and the P / S conversion circuit 404 is a regular signal sequence. Therefore, the sync signal cannot be detected. As a result, the synchronization signal detection circuit 405 outputs a lock detector signal to the output terminal 408, which indicates that the synchronization signal could not be detected.

As described above, the lock detector signal of the synchronizing signal can be used to judge whether the identification point of the digital data is normal. That is, the lock detector signal of the synchronization signal can be used as a switching signal for switching the distortion removal algorithm.

In the case of the lock detector signal indicating that the sync signal could not be detected, the NO side of the process switching judgment of FIG. 3 is selected. If the first distortion removal algorithm is the CMA shown in Table 1, since the average of the distances from the centers of all signal points is used as a reference, the waveform equalization operation does not become unstable.

In the case of the lock detector signal indicating that the synchronization signal has been detected, YES in the judgment of the process switching in FIG.
Choose the side. At this time, since the digital data is a normal identification point, if the second distortion removal algorithm is DD shown in Table 1, effective distortion removal can be performed based on the identification point.

According to the embodiment of FIG. 4, by utilizing the lock detector signal of the synchronizing signal, the switching signal to be input to the input terminal 110 can be obtained with a simple configuration without specially configuring the switching signal generating circuit. be able to.

FIG. 6 shows another embodiment of the present invention, 64QA.
A demodulator for M is shown. In FIG. 6, 601 is a carrier recovery circuit.

The carrier wave recovery circuit 601 receives a digital signal from the data bus, calculates the phase error between the 64QAM signal wave input from the input terminal 101 and the reproduced carrier wave used for quadrature synchronous detection, and quadratures the phase error signal. Output to the synchronous detection circuit 102. The quadrature synchronous detection circuit 102 uses the phase error signal to control the reproduced carrier so as to cancel the phase error between the 64QAM signal wave and the reproduced carrier, and performs the quadrature synchronous detection.

On the other hand, the carrier wave reproduction circuit 601 produces a kind of lock detector signal indicating whether the carrier wave reproduction is normally performed or not, and outputs it to the waveform equalization circuit 107.

When the carrier wave reproduction is not normally performed,
The identification point of the digital data rotates around the center of all signal points. At this time, N of the process switching judgment of FIG.
If the O side is selected and the first distortion removal algorithm is CMA shown in Table 1, the waveform equalization operation does not become unstable because the average of the distances from the centers of all signal points is used as a reference.

When the carrier wave reproduction is normally performed, the YES side of the process switching judgment of FIG. 3 is selected. At this time, since the digital data is a normal identification point, if the second distortion removal algorithm is DD shown in Table 1, effective distortion removal can be performed based on the identification point.

According to the embodiment of FIG. 6, by using the lock detector signal for carrier recovery, the switching signal can be obtained with a simple structure without specially configuring the switching signal generating circuit.

FIG. 7 shows an embodiment of a circuit for generating a switching signal input to the input terminal 110 in FIG. In FIG. 7, 701
Is an error measuring circuit, and 702 is an output terminal of a switching signal generated by the error measuring circuit 701.

I-axis and Q-axis digital data are input from the input terminals 401 and 402 and output to the data conversion circuit 403. The data conversion circuit 403 performs processing such as differential decoding and gray-natural code conversion on the input digital data, and outputs it to the P / S conversion circuit 404. The P / S conversion circuit 404 converts the input digital data into serial data. The synchronization signal detection circuit 405 detects the synchronization signal and outputs the timing signal to the digital signal processing circuit 406.
Output to The digital signal processing circuit 406 extracts the main data string from the serial data with reference to the timing signal, performs processing such as deinterleaving and error correction,
Output to the output terminal 407. The above is the same operation as in FIG.

On the other hand, the digital signal processing circuit 406 is
The number of errors calculated when performing error correction is output to the error measurement circuit 701. The error measurement circuit 701 determines whether the number of input errors is larger or smaller than a certain set value, and outputs the result to the output terminal 702.

If the digital data is located at a point different from the normal identification point due to some influence, the serial data output via the data conversion circuit 403 and the P / S conversion circuit 404 is a regular signal string. Therefore, the error number shows a remarkably large value. Error measuring circuit 70
1 judges this.

From the above, the judgment of the error number measurement can be used to judge whether or not the identification point of the digital data is normal. That is, the determination of the error number measurement can be used as a switching signal for switching the distortion removal algorithm.

When the number of errors is extremely large, the NO side of the process switching judgment of FIG. 3 is selected. If the first distortion removal algorithm is the CMA shown in Table 1,
Since the average of the distances from the centers of all signal points is used as a reference, the waveform equalization operation does not become unstable.

If the number of errors is less than a certain set value,
The YES side of the determination of the process switching is selected. At this time, since the digital data is a normal identification point, if the second distortion removal algorithm is DD shown in Table 1, effective distortion removal can be performed based on the identification point.

According to the embodiment of FIG. 7, it is possible to obtain the switching signal to be input to the input terminal 110 with a simple structure by not judging the size of the number of errors and without specially configuring the switching signal generating circuit. it can.

It should be noted that all the explanations from FIG. 1 to FIG. 7 are 64
Although QAM is used, it is needless to say that waveform equalization can be similarly performed when this is another quadrature amplitude modulation.

[0056]

According to the present invention, in the case of demodulating an amplitude modulation wave or a quadrature amplitude modulation wave, when the states of the input signals input to the waveform equalization circuit are different, for example, carrier wave reproduction is not locked. Since the optimum distortion removal algorithm can be used for each state such as the locked state and the locked state, a demodulation device capable of stably and effectively compensating for a disturbance component and a distortion component generated in the middle of a transmission path or the like is provided. Can be provided.

[Brief description of the drawings]

FIG. 1 is a block diagram of a demodulation device according to an embodiment of the present invention.

FIG. 2 is a block diagram of a main part of a demodulation device according to an embodiment of the present invention.

FIG. 3 is a flowchart of the operation of the demodulation device according to the embodiment of the present invention.

FIG. 4 is a block diagram of a main part of a demodulation device according to a second embodiment of the present invention.

5 is an explanatory diagram of a data string used in the demodulator of FIG.

FIG. 6 is a block diagram of a demodulation device according to a second embodiment of the present invention.

FIG. 7 is a block diagram of main parts of a demodulation device according to a third embodiment of the present invention.

[Explanation of symbols]

101 ... 64QAM signal wave input terminal, 102 ... Quadrature synchronous detection circuit, 103, 105 ... Analog-digital conversion circuit, 104, 106 ... Digital filter circuit, 107 ... Waveform equalization circuit, 108, 109 ... 64QAM demodulated digital data data output Terminal, 110 ... Switching signal input terminal.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Moriyoshi Akiyama 292 Yoshida-cho, Totsuka-ku, Yokohama, Kanagawa, Ltd. Hitachi, Ltd. multimedia system development headquarters (72) Inventor Tsutomu Noda Yoshida, Totsuka-ku, Yokohama, Kanagawa 292, Machi Co., Ltd. Hitachi, Ltd. Multimedia System Development Headquarters (72) Inventor Nao Suzuki, 292, Yoshida-cho, Totsuka-ku, Yokohama, Kanagawa

Claims (8)

[Claims] 1. A demodulation device for demodulating a quadrature amplitude modulation wave, the demodulation means for quadrature phase demodulating the quadrature amplitude modulation wave and outputting first and second signals from an in-phase axis and a quadrature axis, respectively. A first signal and the second signal are input, interference and distortion components are removed from the first signal, and a third signal including a first main demodulation signal that is quadrature-modulated on the modulation side; Waveform equalizing means for removing interference and distortion components from the second signal and outputting a fourth signal including the second main demodulation signal quadrature-modulated on the modulation side, the first signal and the second signal. Signal, the third signal, and the fourth signal are used to control the calculation method of the calculation means by the calculation means for controlling the waveform equalization means and the switching signal input to the calculation means. A demodulator provided with a control means. 2. The waveform equalizing means according to claim 1, wherein the first and third transversal filter means receive the first signal, and the second and third transversal filter means receive the second signal. Fourth transversal filter means, first adding means that receives the first signal and the output signal of the first transversal filter means, the output signal of the first adding means, and the second Second adder means for inputting the output signal of the transversal filter means and the output signal as the third signal, and a second input means for receiving the output signals of the second signal and the third transversal filter means. Demodulation device comprising three adding means, and a fourth adding means for receiving the output signal of the third adding means and the output signal of the fourth transversal filter means as the fourth signal. Place. 3. The arithmetic unit according to claim 1 or 2, wherein the computing means performs a first waveform equalizing operation in the first state of the switching signal, and a switching signal of the switching signal different from the first state. In the second state, the second waveform different from the first waveform equalizing operation is used.
Demodulator that performs the waveform equalization operation of. 4. The first processing method according to claim 3, wherein the first waveform equalizing operation is a first processing method based on a distance from a center of a coordinate plane formed by the in-phase axis and the orthogonal axis. A demodulation device in which the second waveform equalization operation is a second processing method with reference to a coordinate plane position composed of the in-phase axis and the orthogonal axis. 5. The CMA algorithm for the first waveform equalizing operation and the D for the second waveform equalizing operation according to claim 3.
Demodulator with D algorithm. 6. The processing unit according to claim 3, 4, or 5, which outputs a processed signal obtained by processing the first and second main demodulation signals, and detects a synchronization signal from the processed signal, A synchronization signal detecting unit that outputs an evaluation signal indicating whether or not the synchronization signal can be detected is provided, the evaluation signal is used as the switching signal, and the case where the synchronization signal cannot be detected is the first state. age,
A demodulation device that sets the second state when the synchronization signal is detected. 7. The evaluation signal according to claim 3, 4 or 5, which reproduces a reproduced carrier signal synchronized with the carrier signal of the quadrature amplitude modulated wave and indicates whether the reproduced carrier signal can be reproduced or not. Is provided, the evaluation signal is used as the switching signal, the case where the reproduced carrier signal cannot be reproduced is the first state, and the case where the reproduced carrier signal can be reproduced is the second state. Demodulator in the state of. 8. A processing unit for outputting a processed signal obtained by processing the first and second main demodulated signals, and detecting a code error from the processed signal, and further comprising: A code error detection means for outputting an evaluation signal indicating whether or not the amount of code error is detected with a certain reference amount or more is provided, and the evaluation signal is used as the switching signal, and an error with a certain reference amount or more is detected. In this case, the demodulator is set to the first state in the above case, and is set to the second state in the case where the error is less than a certain reference amount.