JPH09135268A - Data exchange - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a data exchange capable of simplifying circuit constitution and reducing a delay time with respect to input. SOLUTION: The serial bit string of inputted m-bits is shifted within a shift register 1, a flag detection part 2 monitors this to detect a synchronizing flag by one-stage operation corresponding to the synchronous pattern of a bit code within a time in which the bit code is shifted based on an inputting transmission speed. At the time of the detection, an address latch part 3 pulls-in the serial bit string of n-bits at a prescribed position following this synchronous flag as an addressing address and store-latches it until detecting the next synchronous flag and an n-stage address selective switch 4 corresponding to the n-bit of the addressing address uniquely selects the output channel of the address by one-stage operation corresponding to the bit code of the addressing address latched by the address latch part 3.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention has a synchronization flag having a predetermined fixed bit length m placed before and after, and a destination address having a predetermined fixed bit length n following the synchronization flag and data following the destination address. The present invention relates to a data exchange device that inputs a frame composed of a serial bit string that is configured and outputs the frame to an output channel corresponding to the destination address, and particularly to detection and output of a frame pattern such as a synchronization flag and a destination address. The present invention relates to a data exchange device having a simplified circuit configuration for selecting a channel.

[0002]

2. Description of the Related Art Conventionally, in a data exchange device of this type, as shown in FIGS. 4 and 5, a latch unit 91 for inputting data of a serial bit string converts the input serial data into a synchronization bit number "m =". 8 "to parallel data and latches the same, and at the same time, the synchronization signal detection unit" 1 "to
It is sent to the frame synchronization signal detector 92 having "8". The frame sync signal detector 92 is latched (2
The sync signal detection units "1" to "8" detect a match with a predetermined bit pattern from the m-1 = 15) bit codes, and send the bit code of the subsequent destination address to the identification information detection unit 93. The identification information detection unit 93 normally detects the destination from the n-bit destination address by a logic circuit,
Notify the data separation unit 94. The data separation unit 94 sends the bit code extracted from the latch unit 91 to the output channel based on the notified destination.

Techniques for frame synchronization include, for example,
It is described in JP-A-1-233845. In this method, when receiving a frame synchronization signal (synchronization flag) and an identification signal (destination address) that are n-multiplexed and transmitted serially, the serial signal received by the latch unit 91 in FIG. 4 is converted into a parallel signal. Then, the frame synchronization signal detection unit 92 detects any one of the n frame multiplexed frame synchronization signals from the signals at the positions sequentially different by 1 bit in the latched signal. After detection, the identification information detection unit 9
3 detects this identification signal, and the data separation unit 94 separates the received signal into the corresponding output channel based on the detected frame synchronization signal and identification signal.

In this system, by detecting one of the frame synchronization signals in the n-multiplexed signal, the synchronization signal detection unit is prevented from increasing by the number of frame patterns corresponding to the multiplexing, and the circuit scale is increased. Has achieved the purpose of not increasing the size of.

[0005]

In the above-mentioned conventional data exchange apparatus, as described in the above publication, the frame pattern can be detected at a low speed.
A bit string transmitted serially is converted into m-bit parallel to secure a latch time m times the transmission time interval of each bit, and the corresponding output channel is detected from the bit string input subsequently. ing. This configuration requires conversion means for converting the input serial bit string into parallel and m stages or m times of detection means for holding the latched bit code for m times and detecting the pattern, and these means are configured. There is a problem that the logic circuit is complicated and the delay time due to the operation is long.

The object of the present invention is to eliminate the conversion and to provide means for carrying out the detection and selection in a single stage operation,
It is an object of the present invention to provide a data exchange device capable of simplifying a circuit configuration in detecting a frame pattern and selecting an output channel and shortening a delay time due to an operation.

[0007]

In a data exchange apparatus according to the present invention, a synchronization flag having a predetermined fixed bit length m is arranged before and after, and a destination having a predetermined fixed bit length n is provided at a predetermined position following the synchronization flag. A data exchange device that inputs a frame composed of a serial bit string composed of an address and data following the destination address and outputs the frame to an output channel corresponding to the destination address monitors the input m-bit serial bit string. , When the synchronization flag is detected in a one-step operation according to the bit code within a time period in which the bit code is shifted according to the input transmission speed,
A serial bit string at a predetermined position following the synchronization flag is fetched as the destination address, latched until the next synchronization flag is detected, and a destination output channel is selected by one-step operation according to the bit code of the latched destination address. By doing so, the input frame is output as the serial bit string.

Further, one of the concrete means of the data exchange apparatus according to the present invention has a storage area of at least the total number of bits of both the synchronization flag and the destination address,
A shift register that shifts a bit string of an input frame based on a bit transmission rate, and a flag detection unit that outputs a latch instruction when a predetermined synchronization flag is detected by monitoring m consecutive bit strings of the shift register. And an address for latching and outputting the read bit code until the next latch instruction is received when n bit strings following the bit string monitored by the flag detection unit are read and a latch instruction is received from the flag detection unit. It has a latch unit and an n-stage destination selection circuit that selects an output destination based on n binary bit codes output from the address latch unit, and selects a bit string input from the shift register from the destination. A destination selection switch that outputs to a unique output channel through the n stages of the circuit.

[0009]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a functional block diagram showing an embodiment of the present invention. The data exchange apparatus shown in FIG. 1 is different from FIG. 4 shown as a conventional example, in which a shift register 1, a flag detection section 2, an address latch section 3, a destination selection switch 4, an output buffer 5, and an operation clock generator 6 are provided. Is equipped with. Here, it is assumed that the frame is sandwiched by a sync flag of m bits before and after, and is composed of a destination address of n bits following the sync flag and data.

The shift register 1 has a bit storage area for the total number of bits "n + m" of the synchronization flag and the destination address, stores and stores the bit code of the input serial bit string one bit at a time in the order of arrival, and stores the next one bit. Is sequentially shifted in the direction from the entrance to the exit, and finally output to the destination selection switch 4. Therefore, the speed of the bits passing through the shift register 1 is the same as the transmission speed of the input serial bit string, and the bit code does not change.

The flag detection unit 2 fetches and monitors the leading m bits at the exit side of the shift register 1, and sends a latch instruction to the address latch unit 3 when detecting a predetermined synchronization flag pattern. To do. As shown in FIG. 2, the flag detection unit 2 is closed by the bit code “0” stored in the shift register 1 or “1”.
It is assumed that m switches, which do not have a buffer function of two kinds of one circuit and two contacts, which are closed at 1, are connected in series in order to detect a synchronization flag having an m-bit length. It is assumed that the m switches have a structure in which they are connected in series in such an order that all the switches are closed when they match the bit string of the synchronization flag pattern. When it is closed, a latch instruction is output.

For example, the synchronization flag pattern is "100.
In the case of "1", a switch that is closed by the code "1", a switch that is closed by the code "0", a switch that is closed by the code "0", and a switch that is closed by the code "1" are in this order. Four
Two switches are connected in series, and when the bit string of the shift register is lined with “1001” from the beginning, all the switches of the flag detection unit 2 are closed and a latch instruction is output.

The address latch unit 3 includes a shift register 1
N bits subsequent to the first m bits on the exit side of are captured and monitored. When a latch instruction is received from the flag detection unit 2, the n bit codes being captured are stored and latched, and at the same time n bits are acquired. Simultaneously display the code for destination selection switch 4
Output to The n bit codes that are latched are the destination address and are held until the next latch instruction.

The destination selection switch 4 has a structure in which n stages of switches without buffer function of one circuit and two contacts are connected in a tree shape. The maximum number of switches in each stage is from the entrance to the exit, from "2 of 0" to "2 (n-
1) Address latch unit 3
, N bit code storage areas and destination addresses are connected in this order. When a latch instruction is issued, the n bit codes are simultaneously received from the address latch unit 3 in each of the n stages to open / close the switch, form a unique path according to the bit pattern of the destination address, and output one output. Select a channel.

For example, if the destination address is a succession of n "1" s, the bit output X of the shift register 1 appears on the output channel shown at the top, as shown in FIG.

The output buffer 5 is a temporary storage circuit connected to each output of the destination selection switch 4 and includes the destination selection switch 4
It adjusts the output timing of the bit received from.

The operation clock generator 6 generates and sends out a clock signal which gives an operation timing to the above-mentioned constituent circuits, and it is assumed that the operation clock generator 6 generates a clock signal having a transmission speed which is 7 times as high as the data bit.

Next, referring to FIGS. 1 and 2 together with FIG. 3, an operation procedure of the functional blocks shown in FIG. 1 will be described. As described above, the series of operations follows the timing based on the clock signal generated by the operation clock generator 6.

First, in the shift register 1, it is assumed that the data bits are shifted to the head position in the order of bit [1], bit [2], ... At the data bit transmission rate. This shift timing is generated every 7th time based on a clock signal having a transmission rate which is 7 times the data bit output from the operation clock generator 6, and the register latch period of the shift register 1 is generated between the pulses of this shift timing. Yes, each bit in the shift register 1 is stored and latched. The flag detection period of the flag detection unit 2 is
It starts or ends with a delay of one clock signal with respect to the register latch period.

Here, in the shift register 1, bits [1] [2] to [m] [m + 1] to [m] in order from the head position.
+ N] are stored and latched, and bits [1] [2] to [m]
Is a synchronization flag pattern, the flag detection unit 2
Are bits [1] [2] to [m] in the shift register 1.
Is taken in, so this is detected as a synchronization flag. In this case, under the above assumption, the next succeeding bit [m +
1] to [m + n] are destination addresses.

As a result, the flag detection unit 2 sends the latch instruction to the address latch unit 3 until the end of the flag detection period. Therefore, the address latch unit 3 fetches bits [m + 1] to [m + n] from the shift register 1. ] Is latched by a clock signal delayed by one and is output to the destination selection switch 4 as a destination address. The address latch period in which the destination address is latched by the address latch unit 3 ends simultaneously with the output of the next latch instruction, and the output of the destination address also stops at the same time.

When receiving the bits [m + 1] to [m + n] of the destination address, the destination selection switch 4 operates each switch based on each bit code value as the destination address is determined by the clock signal delayed by one. The switch confirmation period due to this operation disappears with the disappearance of the input of the destination address, and the switch operation is restored.

At the same timing as the start of this switch determination period, the shift register 1 starts the first bit [1].
The output buffer 5 which receives the output bit of the destination selection switch 4 while starting the output from the latching circuit latches the bit received based on the clock signal delayed by one from the output start of the shift register 1 by the data bit length and sends it to the output channel. doing.

In the above description, the shift register has a storage area of (m + n) bits in order to minimize the size of the shift register, but the number may exceed this number. Further, if the position for the synchronization flag is fixed, the position of the destination address does not have to be limited to the position following the synchronization flag. What is necessary is that the element of the one-circuit two-contact switch of the flag detection unit and the destination selection switch can be opened / closed by following the data bit transmission time based on the bit code value “0/1”. It may be an element. In addition, the destination selection switch is "2 of 0"
Although it has been described as a one-circuit two-contact switch from "1" to "2", switches for patterns not included in the address may be deleted.

[0026]

As described above, according to the present invention, while the input m-bit serial bit string is being shifted in the shift register, it is monitored by the flag detector and the bit code is shifted based on the input transmission speed. When the synchronization flag is detected in the one-stage operation according to the synchronization pattern of the bit code within the time period, the address latch unit pulls in the serial bit string at a predetermined position of n bits following the synchronization flag as the destination address, and performs the next synchronization. The data is latched until the flag is detected, and the n-stage destination selection switches corresponding to the n bits of the destination address uniquely set the destination output channel by one-stage operation according to the bit code of the destination address latched in the address latch unit. The data exchange device of choice is obtained.

With this configuration, the input frame is output to the output channel as it is as the serial bit string, and the synchronization flag detection and the destination selection are simultaneously performed by the one-stage operation based on the bit code value. Therefore, the circuit for parallel conversion is performed. It is possible to obtain a data exchange apparatus which can eliminate the need for the above, minimize the transmission delay including the switch operation, and can simplify the complicated circuit of the synchronization flag and the destination selection into a simple configuration.

[Brief description of the drawings]

FIG. 1 is a functional block diagram showing an embodiment of the present invention.

FIG. 2 is a functional explanatory diagram showing one form of partial details of FIG.

FIG. 3 is a waveform diagram showing one mode of operation based on FIG.

FIG. 4 is a functional block diagram showing an example of the related art.

5 is an explanatory conceptual diagram showing an example of the synchronization signal detection of FIG.

[Explanation of symbols]

 1 shift register 2 flag detection unit 3 address latch unit 4 destination selection switch 5 output buffer 6 operating clock generator

Claims (3)

[Claims] 1. A synchronization flag having a predetermined fixed bit length m is arranged before and after, and is composed of a destination address having a predetermined fixed bit length n at a predetermined position following the synchronization flag and data following the destination address. In a data exchange device for inputting a frame composed of a serial bit string and outputting the frame to an output channel corresponding to the destination address, the time for monitoring the input m-bit serial bit string and shifting the bit code according to the input transmission speed. When the synchronization flag is detected in a one-stage operation according to the bit code, the serial bit string at a predetermined position following the synchronization flag is pulled in as the destination address and latched until the next synchronization flag is detected, and then latched. By selecting the output channel of the destination in one-step operation according to the bit code of the destination address A data exchange device which outputs the input frame as a serial bit string as it is. 2. The circuit for detecting a synchronization flag according to claim 1, wherein m two-contact circuits that operate based on a binary code “0/1” of a bit are provided in series to form a predetermined synchronization flag. A data exchange device which outputs a latch instruction for latching the bit code of the address by a combination of the bit codes. 3. A serial bit string composed of a destination address having a predetermined fixed bit length n following the synchronization flag and data following the destination address, wherein a synchronization flag having a predetermined fixed bit length m is arranged before and after the synchronization flag. In a data exchange device for inputting a frame, inputting the frame, and outputting the frame to an output channel corresponding to the destination address, the data exchange device has a storage area of at least the total number of bits of both the synchronization flag and the destination address, and inputs the same. A shift register that shifts a bit string of a frame based on a bit transmission rate; a flag detection unit that outputs a latch instruction when a predetermined synchronization flag is detected by monitoring continuous m bit strings of the shift register; The n bit strings that follow the bit string monitored by the flag detection unit are read, and the When receiving the H instruction, the address latch unit that latches and outputs the read bit code until receiving the next latch instruction, and outputs based on the n binary bit codes output from the address latch unit A destination selection switch having n stages of destination selection circuits for selecting a destination, and outputting a bit string input from the shift register to a unique output channel via the n stages of the destination selection circuit. Data exchange device.