JPH09134596A - Ccd register - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent a phase at the output side of a CCD register from being influenced by a transmission delay of the CCD register and easily adjust a phase of a phase reset pulse at the output side, by providing a driving pulse feed part for the CCD register properly. SOLUTION: A signal charge is output to an output terminal 6 through a floating diffusion amplifier 1 via an output gate electrode from a first and a second charge transmission electrodes 2, 3 of a predetermined count. The floating diffusion amplifier 1 is an amplifier circuit formed at the output side of a transmission channel of a CCD register. Driving pulses P1 , P2 are fed to an electric path at the B side of the first and second charge transmission electrodes 2, 3 from a driving pulse generation circuit 4. Moreover, driving pulses P1 , P2 are also fed to the electrodes 2, 3 from an opposite electric path A. Since the driving pulses are fed in parallel from both sides, a resistance and a parasitic capacity of a power feed line are reduced to half, and a time constant of the power feed line is smaller, whereby a transmission delay of the driving pulses P1 , P2 is reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CCD register having a floating diffusion amplifier in an output circuit used for a delay line, a linear sensor, a horizontal register of an image sensor and the like.

[0002]

2. Description of the Related Art Conventionally, a CCD register as shown in FIG. 2 having a floating diffusion amplifier 1 in an output circuit has been used as a horizontal register of a CCD image sensor. In FIG. 2, reference numerals 2 and 3 denote first and second charge transfer electrodes which are sequentially and repeatedly arranged in one direction on a transfer channel forming a CCD formed on a semiconductor substrate. The drive pulse generating circuit 4 applies a drive pulse P of two phases having a predetermined phase to the second charge transfer electrodes 2 and 3.
₁ and P ₂ are supplied respectively so that a well-known two-phase CCD register is constructed.

The first and second charge transfer electrodes 2 and 3
The output gate electrode 5 is provided at the output side end of the, and the signal charges transferred from the CCD register from the output gate constituted by the output gate electrode 5 are output to the output terminal 6 via the floating fusion amplifier 1 as an output circuit. The output signal is derived.

In this floating diffusion amplifier 1, a MOS FET 1a forming an amplifier circuit is formed on the same semiconductor substrate as the CCD register, and this MOS F 1 is formed.
The gate of ET1a is connected to the floating diffusion, and this operation supplies a reset pulse to the reset gate 1b to close the gate, sets the potential of the floating diffusion to the potential of the power supply 1c, and then the reset gate 1b. In the off state, signal charges are injected into the floating diffusion through the output gate (the lower part of the output gate electrode 5), the change in the signal potential is detected, and amplified by the MOS FET 1a to obtain the output signal at the output terminal 6. I am doing it.

When such a floating diffusion amplifier is used as an output circuit, there is an advantage that the output capacitance can be reduced and a high output voltage can be obtained.

[0006]

However, in such a conventional CCD register, as shown in FIG. 2, drive pulses P ₁ and P ₂ for charge transfer are supplied to the output side B of the CCD register of the semiconductor substrate.
On the opposite side A, that is, on the side opposite to the side where the floating diffusion amplifier 1 is arranged, power is supplied from the charge transfer electrodes 2 and 3 side, and the capacity of this CCD register and the drive pulses P ₁ and P The drive pulses P ₁ and P ₂ are affected by the propagation delay due to the distributed constant due to the resistance of the transmission line _{2 and} the drive pulses P ₁ and P ₂ are supplied to the power supply side A and the output side of the CCD register. Since there is a phase difference with B (the longer this CCD register is, the greater this effect is), there is the inconvenience that the phase on the output side of this CCD register is affected by this propagation delay, and this CCD register This propagation delay amount and its variation are taken into consideration in synchronizing the phase on the output side with the phase of the reset pulse supplied to the reset gate 1b of the floating diffusion amplifier 1. That there has been a disadvantage that there is a need.

In view of this point, the present invention prevents the phase on the output side of the CCD register from being affected by the propagation delay of the CCD register and easily matches the phase of the phase reset pulse on the output side of the CCD register. The purpose is to be able to.

[0008]

The CCD register of the present invention is, for example, a CCD register having a floating diffusion amplifier 1 as shown in FIG. 1. In this CCD register, the power supply portion for driving pulses P ₁ and P ₂ for driving the CCD register is floated. It is provided on both the diffusion amplifier 1 side and the side opposite to the floating diffusion amplifier 1 side.

According to the present invention, the driving pulses P ₁ and P ₂ for driving the CCD register are supplied from both the floating diffusion amplifier 1 side and the side opposite to the floating diffusion amplifier 1 side.
This means that the power supply line is connected in parallel to the power supply unit, the resistance value of this power supply line becomes 1/2, and the time constant of the power supply line becomes small, so the propagation delay of the drive pulses P ₁ , P ₂ is small. On the floating diffusion amplifier 1 side, that is, on the output side of the CCD register, the drive pulses P ₁ and P ₂ are not affected by the propagation delay, and the phase of the signal on the output side of the CCD register is affected by the propagation delay. In addition, since the drive pulses P ₁ and P ₂ on the output side of the CCD register are not affected by the propagation delay,
The phases of the drive pulses P ₁ and P ₂ on the output side of the register and the reset pulse supplied to the reset gate 1b of the floating diffusion amplifier 1 can be easily synchronized.

[0010]

BEST MODE FOR CARRYING OUT THE INVENTION The present invention C with reference to FIG.
One embodiment of the CD register will be described. In FIG. 1, parts corresponding to those in FIG. 2 are designated by the same reference numerals.

Even in the example of FIG. 1, the CCD is the same as in FIG.
In the example of a horizontal register of an image sensor (not shown), first and second charge transfer electrodes 2 and 3 are sequentially and repeatedly arranged in one direction on a transfer channel forming a CCD formed on a semiconductor substrate, The predetermined number of first and second charge transfer electrodes 2 and 3 are supplied with a predetermined phase of 2 from the drive pulse generation circuit 4.
The phase drive pulses P ₁ and P ₂ are supplied respectively so as to form a well-known two-phase CCD register.

An output gate electrode 5 is provided at the output side ends of the first and second charge transfer electrodes 2 and 3 arranged in a predetermined number, and the CCD register is transferred from the output gate constituted by the output gate electrode 5. The received signal charge is led to the output terminal 6 via the floating diffusion amplifier 1 as an output circuit so that an output signal is obtained.

The floating diffusion amplifier 1 is formed on the output side of the transfer channel of the CCD register. The gate of the MOS FET 1a forming the amplifier circuit is connected to the floating diffusion and the reset pulse is supplied to the reset gate 1b. The gate 1b is closed, the potential of the floating diffusion is set to the potential of the power supply 1c, and the signal charge is output with the reset gate 1b turned off (output gate electrode 5
(Below the bottom of the) and injected into the floating diffusion, the change in the signal potential is detected, and this is detected by the MOS F
The signal is amplified by ET1a and obtained as an output signal at the output terminal 6.

In this example, the drive pulses P ₁ and P ₂ from the drive pulse generation circuit 4 are used for the CCD of a predetermined number of first and second charge transfer electrodes 2 and 3 which form a CCD register.
Power is supplied from the output side of the register, that is, the side B where the floating diffusion amplifier 1 is arranged, and the drive pulses P ₁ and P ₂ are supplied from the charge transfer electrodes 2 and 3 on the opposite side A. It is a thing.

According to this example, the drive pulses P ₁ and P ₂ for driving the CCD register are supplied from the floating diffusion amplifier 1 side and the side opposite to the floating diffusion amplifier 1 side. Since the power supply lines are connected in parallel, the resistance value of this power supply line becomes 1/2, and the parasitic capacitance also becomes 1/2, and the time constant of this power supply line becomes smaller than that of the conventional one. The propagation delay of the drive pulses P ₁ and P ₂ is reduced accordingly.

Further, according to this embodiment, the driving pulses P ₁ and P ₂ are supplied from the charge transfer electrodes 2 and 3 on the floating diffusion amplifier 1 side B of the CCD register, so that the floating diffusion amplifier 1 side is provided. That is, on the output side of the CCD register, the drive pulses P ₁ and P ₂ are not affected by the propagation delay, and the phase of the output signal obtained at the output side of the CCD register is not affected by the propagation delay. since the drive pulse P ₁ of the CCD registers in the output side, P ₂ is not affected by the transmission delay in the driving pulses P _1, P ₂ and the floating diffusion amplifier 1 on the output side of the CCD register
There is an advantage that the phase with the reset pulse supplied to the reset gate 1b can be easily synchronized.

In the above embodiment, an example in which the present invention is applied to a two-phase CCD register has been described.
Of course, it can be applied to CCD registers of more than one phase. Further, the present invention is not limited to the above-mentioned embodiments, and it goes without saying that various other configurations can be adopted without departing from the paper of the present invention.

[0018]

According to the present invention, there is an advantage that the phase of the output signal obtained at the output side of the CCD register is not affected by the propagation delay, and the drive pulses P ₁ and P at the output side of the CCD register are provided. There is an advantage that the phase of ₂ and the reset pulse supplied to the reset gate 1b of the floating diffusion amplifier 1 can be easily synchronized.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing an embodiment of a CCD register of the present invention.

FIG. 2 is a configuration diagram showing an example of a conventional CCD register.

[Explanation of symbols]

1 Floating diffusion amplifier, 2, 3
Charge transfer electrodes, 4 drive pulse generation circuits, 5 output gate electrodes, 6 output terminals

Claims (2)

[Claims] 1. A CCD register having a floating diffusion amplifier, characterized in that a driving pulse feeding section for driving the CCD register is provided on both the floating diffusion amplifier side and the side opposite to the floating diffusion amplifier side. CCD register. 2. A CCD register having an output circuit for receiving a reset pulse and performing a reset operation, wherein a driving pulse feeding section for driving the CCD register is provided on both the output circuit side and the opposite side of the output circuit. A CCD register, which is provided in the.