JPH09130236A - Pll oscillator and communication equipment - Google Patents

Abstract

PROBLEM TO BE SOLVED: To avoid fluctuation in the transmission characteristics of a phase locked loop(PLL) by using an even higher harmonic wave mixer with a built-in antiparallel diode pair, for which two diodes of inverse polarities are parallelly connected, as a phase comparator. SOLUTION: The even higher harmonic wave mixer is used as the phase comparator for outputting an error signal responded to phase difference between a reference oscillated wave fin and a feedback signal wave fm. The higher harmonic wave noise of this error signal is attenuated by a loop filter 4 and based on the error signal passed through the loop filter 4, an output wave fout is outputted from a voltage controlled oscillator 5. In this case, a high frequency signal and a locally oscillated wave are applied through a branching filter circuit 31 to an antiparallel diode pair 32, for which two diodes 32a and 32b of inverse polarities are parallelly connected, and a base band signal BB is extracted. Thus, the even-number order higher harmonic wave of LO and the odd-number order higher harmonic wave of conductance can be suppressed only by balancing the diode pair.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase-locked oscillator and a communication device that output an output wave synchronized with a reference oscillation wave input from the outside.

[0002]

2. Description of the Related Art FIG. 21 shows, for example, "Frequency Synthesizers".
ers), 3rd edition, pp. 379-380, Badim.
Manner Switte (Vadim Manassewi
t), published by John Willy & Sons (Joh)
n Wiley & Sons) "is a configuration diagram showing a conventional phase-locked oscillator, in which 1 is a phase-locked oscillator (hereinafter referred to as PLL). Reference numeral 2 is an input terminal for inputting the reference oscillation wave fin from the outside, 3 is a phase comparator for outputting an error signal according to the phase difference between the reference oscillation wave and the feedback signal wave fm from the multiplier 6, and 4 is the error A loop filter 5 for reducing high frequency noise of the signal is an output wave fout based on the error signal passed through the loop filter 4.
Voltage controlled oscillator (hereinafter referred to as VCO) that outputs
Is a multiplier for multiplying the frequency of the output wave of the VCO 5 by N, and 7 is V
It is an output terminal for outputting the output wave of CO5.

Next, the operation will be described. In FIG. 21, when the reference oscillation wave fin is input from the outside to the input terminal 2, the output terminal 7 outputs the output wave fin / N whose frequency is divided into 1 / N. To explain this operation in detail, the reference oscillation wave fin is fed to the phase comparator 3 by V
The output wave fout of the CO 5 is phase-compared with the feedback signal wave fm multiplied by N in the multiplier 6. The error signal Vout corresponding to the phase difference φ between the reference oscillation wave fin and the feedback signal wave fm is output from the phase comparator 3, further amplified by the loop filter 4, filtered, and then VCO 5 as a frequency control voltage.
Is applied to

The PLL 1 stabilizes the synchronization when the frequencies of the reference oscillation wave fin and the feedback signal wave fm match. Therefore, fin = fm = N · fout∵fout = fin / N (1) Thus, it is understood that the frequency of 1 / N of the reference oscillation wave fin is output from the PLL1 and the PLL1 operates as a frequency divider.

An advantage of operating the PLL1 as a frequency divider is that the PLL1 operates as if it were a narrow band pass filter with respect to the reference oscillation wave fin. Generally, assuming that the open loop gain of the PLL is G (s), FIG.
The transfer gain H (s) between the input and output terminals of the PLL1 is H (s) = G (s) / [N · {1 + G (s)}] G (s) = N · Kv · Kp · F (s ) / S (2). Here, Kv is the sensitivity of the VCO 5, Kp is the sensitivity of the phase comparator 3, F (s) is the gain of the loop filter 4, and s
Is the angular frequency at s = j ω.

From the equation (2), the pass characteristic of the PLL is as shown in FIG. In the figure, the loop band is | G (s) | =
The frequency is 1, and the loop band is the pass band with respect to the center frequency. Therefore, as shown in FIG.
When an input wave containing noise is input to the PLL, the noise component is attenuated in the output wave. Thus, since the frequency divider having the PLL configuration has not only a simple frequency dividing function but also a filtering function, for example, in satellite communication in which the line noise is at a high level,
It is used for reproducing the reference frequency from the pilot signal.

A general diode balanced mixer shown in FIG. 24 has been reported as a phase comparator used in such a frequency divider having a PLL structure. In FIG. 24, 11 is a ring diode composed of four diodes 11a to 11d, 12a and 12b are baluns, 13 is an input terminal, 14 is a multiplier side terminal, and 15 is an output terminal. The balun 12 causes the input wave fin and the output wave N of the multiplier 6
-Fout is fed to the ring diode 11. The input wave fin and the output wave N · fout are analog-multiplied by the non-linearity of the diodes 11a to 11d.
The mixed wave | fin−N · fout | of fin and N · fout generated by this analog multiplication is combined by the balun 12 and output to the output terminal 15. On the other hand, fin and N
The balun 12 cancels out with fout and is not output to the output terminal 15. Since the mixed wave | fin−N · fout | can be taken out without using a filter in this way, there is an advantage that a small phase detector can be constructed, and it is generally used.

In such a phase comparator, the "mixers as phase detector (Mixers as
Phase detector), Volume 5, 1978
1 published by WJ, Inc., diode 1
When the characteristics of 1a to 11d are not uniform, each diode 1
The rectified currents in 1a to 11d are not canceled out, resulting in a DC offset. This is the diode 1 shown in FIG.
1a to 11d DC characteristic mismatch, or balun 12
This is due to the imbalance of a and 12b.

When operated as a PLL, as shown in FIG. 26, in the original ideal state, the DC gain of the loop filter is sufficiently high, so that the detection voltage Vpc is near 0 V and the phase difference φ is near 0 degrees. Is the operating point. However, a PL using a phase comparator with a DC offset
At L, the operating point moves to cancel the DC offset Vdc. At this time, the detected voltage Vp with respect to the phase difference φ
The sensitivity Kp of the phase comparator given by the differential coefficient of c is lower than the sensitivity when the phase difference φ = 0. That is, the operating point and sensitivity K of the phase comparator are determined by the value of the DC offset voltage Vdc.
p changes, and as a result, the transfer characteristics G (s), H of the PLL
(S) changes.

Generally, this DC offset voltage Vdc
Varies depending on the mixer and even the same mixer changes depending on the temperature, so that the transfer characteristic of the PLL becomes unstable. For example, as shown in FIG. 27, at high temperature, the DC offset voltage Vdc increases due to the increase of the rectified current, which lowers the detection sensitivity Kp and lowers the transfer characteristic G (s) as apparent from the equation (2). It will be a gain. As a result, when the temperature is high, the loop band becomes narrow as shown in FIG. 28, and the noise suppression characteristic fluctuates. Further, in the PLL having the conventional configuration, as shown in FIG. 29, the output of the multiplier 6 requires the filter 20 for suppressing the spurious component, and the device becomes large in some cases.

[0011]

Since the conventional phase-locked oscillator is constructed as described above, the characteristics of the diodes 11a to 11d used in the phase comparator are not uniform, variations in the mixer, and the like. Since the DC offset voltage Vdc changes due to the temperature change, the transfer characteristics of the PLL become unstable, the loop band becomes narrow, and the noise suppression characteristics fluctuate. Further, the output of the multiplier 6 requires the filter 20 for suppressing the spurious component, and there is a problem that the device becomes large in some cases. Further, when the multiplication number N increases, the number of the multipliers 6 increases, so that the size of the device becomes large and the cost becomes high.

The present invention has been made to solve the above problems, and an object thereof is to obtain a phase-locked oscillator that suppresses fluctuations in transfer characteristics due to a DC offset voltage and reduces the number of filters and multipliers. And It is another object of the present invention to obtain a communication device that is compact and suppresses fluctuations in noise characteristics.

[0013]

A phase-locked oscillator according to a first aspect of the present invention uses an even harmonic mixer having a built-in anti-parallel diode pair in which two diodes of opposite polarities are connected in parallel as a phase comparator. It was what I had.

The phase-locked oscillator according to a second aspect of the present invention uses, as the phase comparator, an even harmonic mixer having a ring diode and a balanced / unbalanced conversion circuit built therein.

According to the third aspect of the present invention, the phase-locked oscillator uses a reference oscillation wave from the outside as a high frequency signal of the even harmonic mixer and outputs the voltage controlled oscillator as a local oscillation wave of the even harmonic mixer. It uses waves.

According to a fourth aspect of the present invention, a phase locked oscillator uses an output wave from a voltage controlled oscillator as a high frequency signal of an even harmonic mixer, and a reference oscillation from the outside as a local oscillation wave of the even harmonic mixer. It uses waves.

According to the fifth aspect of the present invention, the phase-locked oscillator has a frequency divider connected between the voltage controlled oscillator and the even harmonic mixer.

According to the sixth aspect of the present invention, the phase-locked oscillator has a multiplier connected between the voltage controlled oscillator and the even harmonic mixer.

According to a seventh aspect of the phase-locked oscillator of the present invention, a limiter is provided between at least one of the voltage controlled oscillator and the even harmonic mixer and / or the input side of the reference oscillation wave of the even harmonic mixer. It is connected.

According to the eighth aspect of the present invention, in the phase locked oscillator, a filter is provided on at least one of the voltage controlled oscillator and the even harmonic mixer and / or the input side of the reference oscillation wave of the even harmonic mixer. It is connected.

According to the ninth aspect of the present invention, the phase-locked oscillator has a termination resistance of more than 50 ohms connected to the output side of the even harmonic mixer.

A communication device according to a tenth aspect of the invention is
A transmission signal of a wireless or wired line is input as a reference oscillation wave to the phase comparator of the phase locked oscillator according to any one of claims 1 to 9.

[0023]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below. Embodiment 1 FIG. In FIG. 1, reference numeral 1 is a phase-locked oscillator (hereinafter referred to as PLL). 2 is the reference oscillation wave f from the outside
An input terminal 3 for inputting in is a phase comparator that outputs an error signal according to the phase difference between the reference oscillation wave fin and the feedback signal wave fm. In this embodiment, an even harmonic mixer is used. There is. 4 is a loop filter for reducing high frequency noise of the error signal, 5 is a voltage controlled oscillator (hereinafter referred to as VCO) that outputs an output wave fout based on the error signal passed through the loop filter 4, and 7 is an output wave of the VCO 5. Is an output terminal for outputting.

Next, the operation will be described. The even harmonic mixer 30 is generally referred to as a "harmonic mixing with anti-parallel diode pair (Harm
onic mixing with an antip
arallall diode pair), 197
5 years, published by IEEE, IEEE Transon Microweb Theory and Techniques Vol. Emity-23 No. 8 667 to 673 (IEEE Trans. Microvav
e theory and techniques, vo
l. MTT-23, No. 8, p677-p673) "
2 has the configuration shown in FIG.

In FIG. 2, 31 is a demultiplexing circuit, 32 is an anti-parallel diode pair (hereinafter referred to as APDP).
And APDP32 is a diode 32a, 3 of opposite polarity.
2b are connected in parallel, and this APD is generally used.
A high frequency signal (hereinafter referred to as RF) and a local oscillation wave (hereinafter referred to as LO) are added to P32 via the branching circuit 31, and an intermediate frequency signal (hereinafter referred to as IF) is taken out. In this embodiment, a baseband signal (hereinafter referred to as BB) is taken out instead of this IF.

When LO is added to this even harmonic mixer 30, as shown in FIG.
Since a and 32b are turned on and a current flows, conductance increases every half cycle. Therefore, there are only odd harmonics of LO and even harmonics of conductance. And these two diodes 32a, 32b
Since the even harmonics of LO and the odd harmonics of conductance can be suppressed only by the balance of, it is possible to suppress much higher than that of a normal balanced mixer that depends on the characteristics of the balun. By the way, in the case of microwaves, the suppression is about 25 dB in a normal balanced mixer, but in the even harmonic mixer 32, it can be suppressed by 50 dB to 60 dB. When the output frequency fout of the even harmonic mixer 30 is expressed by an equation,

Fout = | m · frf ± n · fp | (3) where m and n are integers and | m ± n | is an odd number frf is the frequency of RF and fp is the frequency of LO. Therefore, in a normally used order, fout = | frf-2fp | (4). Therefore, since it is possible to operate at half the fp, most of the references and other references are applied to microwaves, particularly millimeter-wave heterodyne transmitters / receivers.

FIG. 4 shows the frequency relationship when such an even harmonic mixer 30 is applied to a PLL receiver. As can be seen from the equation (4), f is set during phase synchronization of the PLL.
Since out = 0, LO (fp) is RF (frf)
It is almost half the frequency. In other words, since it also has the function of the doubler, one multiplier is not required, and it is possible to reduce the size and cost.

When such an even harmonic mixer 30 is applied to a phase comparator of a PLL, the DC offset of the even harmonic mixer 30 is m = 0 in equation (3) and m + n = 0 in n = 0. This is strongly suppressed because it can be regarded as an even order. Moreover, as explained above, compared to a normal mixer, 2
Since it is reduced by 0 dB or more, it becomes a practically negligible value. Therefore, the fluctuation of the PLL due to the presence of the DC offset can be suppressed. Conventionally, there is no case where the even harmonic mixer 30 is applied to a phase comparator of a PLL. This time, focusing on the low DC offset characteristic of the even harmonic mixer 30, and applying this to the phase comparator of the PLL,
This is a new finding of the effect of stabilizing the phase locked loop.

Further, a concrete configuration diagram of the even harmonic mixer 30 is shown in FIGS. In FIG. 5, 34 is an open tip stub, 35 is a short-circuited stub, 36 is an RF choke,
37 is a DC cut. In the figure, the tip open stub 34 and the tip short stub 35 are a quarter at the LO frequency.
Since the wavelength and the RF frequency are halved and the terminals of the anti-parallel diode pair 32 are short-circuited or open, RF and LO can be demultiplexed. Further, RF and BB are separated by the RF choke 36 and the DC cut 37.

In FIG. 6, reference numeral 38 is a lumped constant tip open stub, and 39 is a lumped constant tip short stub. FIG.
The even harmonic mixer of is a circuit in which stubs are made lumped constants, and operates similarly by appropriately setting the values of inductors and capacitors. Even when these mixers are used as the phase detector of the PLL, the same effect can be obtained.

Thus, in this embodiment,
By using an even harmonic mixer capable of outputting a mixed wave of a doubled wave of LO and RF as the phase detector, LO can be set to 1/2 of RF. Therefore, one doubler can be dispensed with, and the size and cost can be reduced. In principle, only odd-order mixed waves are generated, so 0
The level of the DC offset, which is the next component, is extremely low, and fluctuations in the transfer characteristics of the phase-locked loop due to temperature and the like can be avoided.

Embodiment 2 FIG. Although the even harmonic mixer using the anti-parallel diode pair 32 has been described in the first embodiment, the even harmonic mixer can also be configured by using a ring diode. FIG. 7 is a block diagram showing an even harmonic mixer using a ring diode. In the figure, 40 is a balun for balanced / unbalanced conversion (balanced / unbalanced conversion circuit, 180-degree distributor), 41 is a ring diode, Reference numeral 42 is a branching circuit for RF input and BB output.

Next, the operation will be described. In this even harmonic mixer, the balun 40 for balanced / unbalanced conversion is applied to the LO input.
180 ° and distributed to the ring diode 41. Further, the ring diode 4 which can isolate the RF input wave from the LO terminal through the branching circuit 42.
1 to the orthogonal node 43. Ring diode 41
A mixed wave of the second harmonic of LO generated internally and the RF input wave is generated between the node 43 and the ground conductor, and can be taken out via the branching circuit 42. Therefore, the same operation as that of the configuration using the anti-parallel diode pair described in the first embodiment is performed, and the same effect is obtained. Further, since the LO and RF demultiplexing stubs are not used, an even harmonic mixer operating in a wide frequency band can be obtained and the size can be reduced. Therefore, the PLL can be broadened and downsized.

In the above description, the even harmonic mixer using the ordinary ring diode 41 is shown, but as shown in FIG. 8, the anti-parallel ring diode (the anti-parallel ring diode (44a to 44d) connected in a ring shape ( The ring diode) 44 may be used, and the same effect is obtained.

As described above, in this embodiment, the even harmonic mixer composed of the ring diode and the balun is used, whereby the even harmonic mixer can be downsized and the band can be widened.

Embodiment 3 In this embodiment, as shown in FIG. 9, the LO of the even harmonic mixer 30 of the first embodiment is changed.
The terminal is connected to the VCO 5 and the RF terminal is connected to the input terminal 2, and the second harmonic of the output wave fout of the VCO 5 and the input wave fi are connected.
The difference frequency component with respect to n is output from the even harmonic mixer 30. Since the PLL operates so that 2fout = fin, fout = fin / 2 is eventually obtained. Therefore, the PLL as a whole has a function as a frequency divider, and the same effects as those of the first embodiment can be obtained with respect to downsizing and stabilization of the PLL.

Embodiment 4 FIG. This embodiment is shown in FIG.
As shown in, L of the even harmonic mixer 30 of the first embodiment is
By connecting the O terminal to the input terminal 2 and the RF terminal to the VCO 5, the second harmonic wave of the external input wave fin and the output wave fout are connected.
In this configuration, the difference frequency component between and is output from the even harmonic mixer 30. Since the PLL operates so that 2fout = fin, fout = 2 · fin is eventually obtained. Therefore, the PLL as a whole has a function as a multiplier, and the same effects as those of the first embodiment can be obtained in terms of downsizing and stabilization of the PLL.

Embodiment 5 This embodiment is shown in FIG.
As shown in, L of the even harmonic mixer 30 of the first embodiment is
The O terminal is connected to the input terminal 2, and the frequency divider 50 is connected between the VCO 5 and the RF terminal of the even harmonic mixer 30 so that the second harmonic wave of the external input wave fin and the output wave fout are connected.
The difference frequency component with the N divided frequency fout / N is output from the even harmonic mixer 30. Foo as a PLL
Since the operation is such that t / N = 2fin, after all, fo
ut = 2N · fin. Therefore, the PLL as a whole has a function as a multiplier, and it is possible to reduce the size and the PLL.
The same effects as those of the first embodiment can be obtained with respect to the stabilization and the like. Further, the LO terminal and the RF terminal of the even harmonic mixer 30 shown in FIG. 11 may be exchanged, and fout = N · fin /
2, the other effects are exactly the same.

Sixth Embodiment This embodiment is shown in FIG.
As shown in, R of the even harmonic mixer 30 of the first embodiment is
The F terminal is connected to the input terminal 2, and the multiplier 51 is connected between the VCO 5 and the LO terminal of the even harmonic mixer 30 to output N-multiplied waves N · fout of the input wave fin and the output wave fout from the outside. The second harmonic 2N · fout difference frequency component is output from the even harmonic mixer 30. As the PLL operates so that 2N · fout = fin,
Eventually, fout = fin / (2N). Therefore, P
The LL as a whole has a function as a frequency divider,
With respect to downsizing and stabilization of the PLL, the same effects as those of the first embodiment are achieved. In addition, the even harmonic mixer 3 in FIG.
The LO terminal and RF terminal of 0 may be exchanged, and fout
= 2 · fin / N, but other effects are exactly the same.

Embodiment 7 FIG. Fig. 13 shows even harmonic mixer 3
The conversion loss with respect to the local oscillation power of 0 is shown. A normal fundamental mixer exhibits a saturation characteristic and a stable conversion loss can be obtained with respect to the locally oscillated power, but the even harmonic mixer 30 is not stable.
This is because when the local oscillation power is increased in the anti-parallel diode pair 32, the time during which both the diodes 32a and 32b are turned on becomes longer, and finally the diode 32a,
This is a phenomenon caused by the loss of non-linearity because both 32b are turned on. Therefore, if the local oscillation power fluctuates due to temperature or the like, there is a problem that the transfer gain of the PLL fluctuates greatly. Further, the output level changes linearly with respect to the RF level input to the even harmonic mixer 30, and the transfer gain of the PLL also largely changes.

Therefore, in the PLL according to this embodiment, as shown in FIG. 14, limiters 52a and 52b are provided on both the RF and LO input terminals of the even harmonic mixer 30, and the input level to the even harmonic mixer 30 is set. It suppresses fluctuations. FIG. 15 shows a characteristic diagram of the limiters 52a and 52b.
As a result, the even harmonic mixer 30 with limiter shown in FIG.
The characteristic is that the limiters 52a and 52b respond to fluctuations in input power.
It becomes stable by the effect of. Further, since many harmonics are output from the limiters 52a and 52b, the filter 53 as shown in FIG.
May be provided to suppress harmonics. Further, although the limiters 52a and 52b are provided at both the RF and LO input terminals of the even harmonic mixer 30 in the above description, either one may have the same effect depending on the amount of signal level fluctuation.

Embodiment 8 FIG. If an unwanted wave is present in the input wave to the even harmonic mixer 30, high-order mixing is performed in the even harmonic mixer 30, so that spurious may occur in the band depending on the case. Therefore, the PLL shown in FIG.
Then, a filter 54 is provided at both the RF and LO input terminals of the even harmonic mixer 30 to suppress unnecessary waves input to the even harmonic mixer 30. Therefore, there is an effect that the level of the unnecessary wave can be suppressed even in the PLL. Further, in the above description, the filters 54 are provided at both the RF and LO input terminals of the even harmonic mixer 30, but either one may be used depending on the unwanted wave level of the input wave, and the same effect can be obtained.

Embodiment 9 When using a mixer in general, and a diode mixer in particular, as a detector,
As Phase Detector (Mixers as p
has detector), published by WJ, 1978, Tech-Note Vol. 5, No. 1 (Tech-n)
ote vol. 5, no. 1) ”, the terminal voltage Vo is output to the baseband circuit.

This is because the diode mixer configured as shown in FIG. 24 is designed assuming that each terminal is 50 ohms. However, normally, in a baseband circuit using an operational amplifier, a voltage transmission system is assumed instead of power transmission, and therefore, there is no meaning other than matching with the termination resistance Zo of 50 ohms. In addition, the even harmonic mixer 30 has a conversion loss of 1 compared to a normal mixer because the secondary harmonic is used.
It is about 3 dB higher than dB. Therefore, in the PLL even harmonic mixer 30 according to this embodiment, the terminating resistance Zo is set to 50.
The impedance is higher than ohms and the detection voltage Vo is improved.

FIG. 19 shows a PL according to the configuration of this embodiment.
The circuit of L is shown. In the figure, 55 is a terminating resistor Zo, and 56 is a buffer amplifier. FIG. 20 shows the detected voltage Vo with respect to the termination resistance Zo. Experimentally, in the case of the even harmonic mixer 30, if the voltage is increased to about 200 ohms, the voltage is approximately doubled, and in operation, the same effect as in the case where the conversion efficiency is improved is obtained. Therefore, the detection sensitivity Kp can be increased, and the PLL can be stabilized.

Embodiment 10 FIG. This embodiment is a communication apparatus using the PLL shown in the first embodiment to the ninth embodiment. A transmission signal of a wireless or wired line, for example, a pilot signal transmitted from a satellite is used as a reference signal and input to the PLL shown in the first to ninth embodiments. Then, the line noise included in the pilot signal can be suppressed by the PLL, and the reference clock having a low noise level can be output. Therefore, since the PLLs shown in the first to ninth embodiments are applied, the phase synchronization can be stabilized and the miniaturization can be achieved similarly to these embodiments.
There is an effect that the price can be reduced.

[0048]

As described above, according to the first aspect of the present invention, as the phase comparator, the even harmonic mixer having the anti-parallel diode pair in which two diodes of opposite polarities are connected in parallel is used. Since it is configured, by using the even harmonic mixer capable of outputting the mixed wave of the doubled wave of the local oscillation wave and the signal wave, one doubler can be dispensed with, and the size can be reduced and the cost can be reduced. effective. Further, since only odd-order mixed waves are generated in principle, the level of the DC offset, which is the 0th-order component, is extremely low, which has the effect of avoiding fluctuations in the transfer characteristics of the phase-locked loop.

According to the second aspect of the present invention, the even-harmonic mixer having the ring diode and the balanced / unbalanced conversion circuit built therein is used as the phase comparator.
There is an effect that the even harmonic mixer can be miniaturized and widened in band.

According to the third aspect of the invention, the reference oscillation wave from the outside is used as the high frequency signal of the even harmonic mixer, and the output wave from the voltage controlled oscillator is used as the local oscillation wave of the even harmonic mixer. With this configuration, there is an effect that the entire phase locked oscillator can operate as a frequency divider.

According to the fourth aspect of the present invention, the output wave from the voltage controlled oscillator is used as the high frequency signal of the even harmonic mixer, and the external reference oscillation wave is used as the local oscillation wave of the even harmonic mixer. With this configuration, there is an effect that the entire phase-locked oscillator can operate as a multiplier.

According to the fifth aspect of the invention, since the frequency divider is connected between the voltage controlled oscillator and the even harmonic mixer, there is an effect that the entire phase locked oscillator operates as a multiplier. .

According to the sixth aspect of the invention, since the multiplier is connected between the voltage controlled oscillator and the even harmonic mixer, there is an effect that the entire phase locked oscillator operates as a frequency divider. .

According to the invention of claim 7, the limiter is connected to at least one of the input side of the reference oscillation wave of the even harmonic mixer and between the voltage controlled oscillator and the even harmonic mixer. With this configuration, there is an effect of suppressing fluctuations in the transfer characteristic of the phase-locked oscillator due to fluctuations in the level of the input wave of the even harmonic mixer.

According to the eighth aspect of the invention, the filter is connected to at least one of the input side of the reference oscillation wave of the even harmonic mixer and between the voltage controlled oscillator and the even harmonic mixer. With this configuration, it is possible to suppress the generation of unnecessary waves in the even harmonic mixer.

According to the invention described in claim 9, since the terminating resistance exceeding 50 ohms is connected to the output side of the even harmonic mixer, the detection sensitivity is enhanced and the stability of phase synchronization is enhanced. It has the effect of suppressing noise.

According to the invention of claim 10, claim 1
Since the phase comparator of the phase-locked oscillator according to any one of claims 9 to 9 is configured to input a transmission signal of a wireless or wired line as a reference oscillation wave, the device can be downsized, and This has the effect of suppressing fluctuations in noise characteristics due to fluctuations in temperature and the like.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing a phase-locked oscillator according to a first embodiment of the present invention.

FIG. 2 is a configuration diagram showing an even harmonic mixer used in the phase locked oscillator according to the first embodiment of the present invention.

FIG. 3 is a characteristic diagram of current and conductance of an anti-parallel diode pair.

FIG. 4 is a characteristic diagram showing a frequency relationship of a phase locked oscillator.

FIG. 5 is a configuration diagram specifically showing an even harmonic mixer used in the phase locked oscillator according to the first embodiment of the present invention.

FIG. 6 is a configuration diagram specifically showing an even harmonic mixer used in the phase locked oscillator according to the first embodiment of the present invention.

FIG. 7 is a configuration diagram showing an even harmonic mixer used in the phase locked oscillator according to the second embodiment of the present invention.

FIG. 8 is a configuration diagram showing an even harmonic mixer used in the phase locked oscillator according to the second embodiment of the present invention.

FIG. 9 is a configuration diagram showing a phase-locked oscillator according to a third embodiment of the present invention.

FIG. 10 is a configuration diagram showing a phase-locked oscillator according to a fourth embodiment of the present invention.

FIG. 11 is a configuration diagram showing a phase-locked oscillator according to a fifth embodiment of the present invention.

FIG. 12 is a configuration diagram showing a phase locked oscillator according to a sixth embodiment of the present invention.

FIG. 13 is an explanatory diagram of conversion loss of the even harmonic mixer with respect to local oscillation power.

FIG. 14 is a configuration diagram showing a phase-locked oscillator according to a seventh embodiment of the present invention.

FIG. 15 is a characteristic diagram of a limiter.

FIG. 16 is a characteristic diagram of an even harmonic mixer with a limiter.

FIG. 17 is a characteristic diagram of a spectrum of a limiter output.

FIG. 18 is a configuration diagram showing a phase-locked oscillator according to an eighth embodiment of the present invention.

FIG. 19 is a configuration diagram of an output circuit of an even harmonic mixer of a phase locked oscillator according to a ninth embodiment of the present invention.

FIG. 20 is a characteristic diagram of the detection voltage with respect to the termination resistance.

FIG. 21 is a configuration diagram showing a conventional phase locked oscillator.

FIG. 22 is a characteristic diagram of transfer characteristics of a conventional phase locked oscillator.

FIG. 23 is a characteristic diagram of an output spectrum of a conventional phase locked oscillator.

FIG. 24 is a configuration diagram showing a phase comparator used in a conventional phase locked oscillator.

FIG. 25 is a characteristic diagram of static characteristics of a diode.

FIG. 26 is an explanatory diagram illustrating an influence of a DC offset.

FIG. 27 is a characteristic diagram for explaining the influence of temperature on the transfer characteristic of the phase-locked oscillator.

FIG. 28 is a characteristic diagram for explaining the influence of temperature on the transfer characteristic of the phase-locked oscillator.

FIG. 29 is a configuration diagram showing a conventional phase locked oscillator.

[Explanation of symbols]

1 phase-locked oscillator, 5 voltage controlled oscillator, 30 even harmonic mixer, 32 anti-parallel diode pair, 3
2a, 32b diode, 40 balun for balanced / unbalanced conversion (balanced / unbalanced conversion circuit), 41 ring diode, 44 anti-parallel ring diode (ring diode), 50 frequency divider, 51 multiplier, 52a,
52b limiter, 54 filter, 55 termination resistor.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Mitsuhiro Shimozawa 2-3-3 Marunouchi, Chiyoda-ku, Tokyo Sanryo Electric Co., Ltd. (72) Inventor Shigeo Yamanaka 2-3-2 Marunouchi, Chiyoda-ku, Tokyo Inside Ryo Electric Co., Ltd.

Claims (10)

[Claims] 1. A phase comparator for externally inputting a reference oscillating wave, and a voltage controlled oscillator for outputting an output wave, the phase comparator responsive to a phase difference between the reference oscillating wave and a feedback signal wave from the voltage controlled oscillator. Output the error signal from the phase comparator,
In the phase-locked oscillator that outputs an output wave synchronized with the reference oscillation wave from the voltage controlled oscillator based on the error signal, the phase comparator includes an anti-parallel diode pair in which two diodes of opposite polarities are connected in parallel. A phase-locked oscillator using an even harmonic mixer. 2. A phase comparator for externally inputting a reference oscillating wave and a voltage controlled oscillator for outputting an output wave, the phase comparator responsive to a phase difference between the reference oscillating wave and a feedback signal wave from the voltage controlled oscillator. Output the error signal from the phase comparator,
In a phase-locked oscillator that outputs an output wave synchronized with the reference oscillation wave from the voltage controlled oscillator based on the error signal, the phase comparator includes a ring diode and a balanced diode.
A phase-locked oscillator using an even harmonic mixer including an unbalanced conversion circuit. 3. A reference oscillation wave from the outside is used as a high frequency signal of the even harmonic mixer, and an output wave from a voltage controlled oscillator is used as a local oscillation wave of the even harmonic mixer. The phase-locked oscillator according to claim 1 or claim 2. 4. An output wave from a voltage controlled oscillator is used as a high frequency signal of the even harmonic mixer, and a reference oscillation wave from the outside is used as a local oscillation wave of the even harmonic mixer. The phase-locked oscillator according to claim 1 or claim 2. 5. The phase locked oscillator according to claim 1, further comprising a frequency divider connected between the voltage controlled oscillator and the even harmonic mixer. 6. The phase-locked oscillator according to claim 1, further comprising a multiplier connected between the voltage-controlled oscillator and the even harmonic mixer. 7. A limiter is connected to at least one of an input side of a reference oscillation wave of the even harmonic mixer and between the voltage controlled oscillator and the even harmonic mixer. The phase-locked oscillator according to claim 6. 8. A filter is connected to at least one of the input side of the reference oscillation wave of the even harmonic mixer and between the voltage controlled oscillator and the even harmonic mixer. Any one of claim 7
The phase-locked oscillator according to the item. 9. The phase-locked oscillator according to claim 1, further comprising a terminating resistance of more than 50 ohms connected to the output side of the even harmonic mixer. 10. A communication characterized in that a transmission signal of a wireless or wired line is input as a reference oscillation wave to the phase comparator of the phase locked oscillator according to any one of claims 1 to 9. apparatus.