JPH09128958A - Semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor memory device which avoids the increase of area and complex control, can deal with the size structure variable parametric RAM and allows easy and exact control and the reduction of current consumption at the time of writing operation. SOLUTION: A control circuit 1a detects the readout data of the dummy memory cell DMC arranged in the cell array and makes the enable signal EN inactive to control the finish of the readout operation at the time of readout. Similarly at the time of writing, it inactivates the enable signal EN based on the output of the dummy memory cell DMC to control the finish of the writing operation. By this, the installation of an exclusive pulse generator is made unnecessary and the increase of area and complex control is avoided. And since even the parametric RAM of variable size constitution can produce activated pulses in accordance with its delay, control is kept easy and exact.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device such as a static RAM (SRAM) which reads / writes data by charging / discharging a bit line to which a memory cell is connected, and more particularly, to an improvement of a write circuit. Regarding

[0002]

2. Description of the Related Art Conventionally, a dummy memory cell is used to detect the output of read data to activate a sense amplifier, or to detect the completion of sensing to deactivate a sense amplifier to read data. A memory device that terminates an operation is known. Regarding the write operation, a timing circuit for generating a write pulse is provided inside, and a memory device that terminates the write operation after a certain period of time, or a synchronous type that is widely used in ASICs and the like, connects memory cells in the first half of the clock. There is known a memory device that precharges a bit line to be written and activates a word line in the latter half to perform writing.

FIG. 11 has a circuit for detecting the output of read data using a dummy memory cell and ending the read operation, and a timing circuit for internally generating a write pulse. FIG. 10 is a conceptual diagram of a conventional example of a memory device that ends the process. Also,
FIG. 12 is a timing chart at the time of reading and writing of the device of FIG.

This memory device has memory cells arranged in rows and columns.
For example, SRAM cells are arranged and, as shown in FIG. 11, memory cells MC1k, MC2k, MC3k,
MC4k (four rows in FIG. 11) is connected to a pair of bit lines BLk, BLBk, and these bit lines BLk, BLk,
BLBk is connected to the sense amplifier SAk via column gates CGk and CGBk which are n-channel MOS (NMOS) transistors. In addition to the normal memory cell array, one column of dummy memory cells DMC1,
DMC2, DMC3, DMC4 are provided for each row. These dummy memory cells DMC1, DMC2, DM
C3 and DMC4 are a pair of dummy bit lines DBL, DBL
B of the dummy bit lines DBL, DBLB
Is connected to the dummy output determiner and the control circuit 1 through column gates DCG and DCGB. The memory cells and dummy memory cells in each row are connected to common word lines WL1, WL2, WL3, WL4, and these word lines WL1, WL2, WL3, WL4 are buffer B.
Row decoder R via F1, BF2, BF3, BF4
It is driven by DC. Also, the column gates CGk, C
The gate electrodes of GBk, DCG and DCGB are connected to the common output line of the column decoder CDC.

The write enable signal WEN generated by the write pulse generator 2 is a row decoder RD.
C, column decoder CDC and write circuit 3 are supplied. Further, the read enable signal REN which is an output control signal of the control circuit 1 is supplied to the sense amplifier SAk, the row decoder RDC and the column decoder CDC. The sense amplifier SAk is connected to the output circuit 4.

In such a structure, the procedure for ending the read and write operations is performed as follows. First,
At the time of reading, as shown in FIG. 12A, the control circuit 1 detects the read data from the dummy memory cells arranged in the cell array when the read enable signal REN which becomes high level at the beginning of the read cycle. As a result, the sense amplifier SAk is switched to the low level,
It is supplied to the row decoder RDC and the column decoder CDC. As a result, the sense amplifier SAk, the row decoder RDC, and the column decoder CDC enter the disable state, the internal read operation is completed, and the precharge for the next cycle is started.

At the time of writing, as shown in FIG. 12B, a high level write enable signal WEN is generated by the write pulse generator 2, and the row decoder RD is generated.
C, column decoder CDC and write circuit 3 are supplied. As a result, the write operation is performed by the write circuit 3, and the end control is also performed based on the level switching of the write enable signal WEN.

FIG. 13 is a circuit diagram of a conventional memory device which is synchronous and precharges a bit line to which a memory cell is connected in the first half of a clock and activates a word line in the latter half to perform writing. Further, FIG. 14 is a timing chart at the time of reading and writing of the device of FIG.

In this circuit, the memory cells MC1k, MC1m
Show an example of an SRAM cell composed of a flip-flop in which the inputs and outputs of the inverters I1 and I2 are connected, and the gate electrodes of the access transistors A1 and A2 of the memory cells MC1k and MC1m arranged in the same row are common. It is connected to the word line WL1 and the like.

At the time of writing, the row decoder RDC
, One word line WL to be selected is selected from the row address RAD. The selection signal is supplied to one input terminal of a predetermined 2-input AND gate AD1, AD2, .... Then, the clock signal CLK via the inverter INV1 is supplied to the other input terminal of the 2-input AND gate AD1 and the like. Therefore, clock signal CLK
The selected word line WL is driven to the high level only when is at the low level. Bit line pair BLk, BL
Bk, BLm, BLBm are column gates CGk, CG
The data lines D and DB are connected through Bk, CGm, and CGBm. Column gate CGk, CGBk, CG
In the column decoder CDC, only one pair of m and CGBm are controlled to be in the on state and the rest are controlled to be in the off state.

The write data Din is stored in the buffer BUF2.
Is latched in the latch circuit LTC at the timing of the fall of the clock signal CLK.
The output data of the latch circuit LTC is stored in the buffer BU.
It is propagated to the data line D via F3 and BUF4, and is propagated to the inversion data line DB via buffers BUF3, BUF5 and INV2. Also, PTk, PTBk, PT
m and PTBm are precharge transistors for bit lines, and the gate electrode receives the clock signal CLK via the buffer BUF1 to be turned on / off.

In such a structure, at the time of writing,
As shown in FIG. 14, while the clock signal CLK is at the high level, the levels of all the word lines WL are held at the low level, and all the bit lines BLk, BLBk, BLm, BLBm are set to the power supply voltage V _CC level (high level). Precharged. Then, when the clock signal CLK switches to the low level, the selected word line (WL _i ) becomes the high level, and the selected column signal CLM is held at the high level. At this time, one of the bit lines BLk and BLBk is held at the high level and the other is changed to the low level according to the value of the write data Din, and the data is written to the memory cell MC1k or the like.

Unselected bit lines BL _m , BLB
Either _m or the like is discharged to a low level through the memory cell according to the data of the memory cell MC1m or the like.
This speed depends on the capacity of the memory cell, but is usually slower than the writing speed. This discharge of electric charge is unnecessary for the writing operation itself, and wastes power. However, if this precharge is not performed, unpredictable writing to the memory cell occurs in the non-selected bit line, so that at least normally, it is necessary to precharge to a potential at which the access transistor of the memory cell is turned off.

[0014]

However, in the above-described memory device of FIG. 11, the read-related timing circuit and the write-related timing circuit are provided separately for one or both of them. There is waste such as an increase in area and complicated control. Also,
In the parametric type with variable configuration size, the read time can be generated flexibly according to the configuration by using the dummy memory cells, but it was difficult to generate the write time timing.

Further, in the writing of the synchronous precharge method of the memory device of FIG. 13, the word line is active during the latter half of the cycle, and the writing state continues during that time. Since this is a precharge type, no DC current flows because the load of the bit line is off at the time of writing, but in the bit line of the non-selected column, either one of the bit line pairs is discharged by the memory cell. This current is useless in terms of writing. Especially, when the half of the cycle time is equal to or longer than this discharge time, it becomes the maximum.

As described above, although the synchronous SRAM has no DC current, the bit line charging / discharging current is the majority of the AC current. Usually, about 2 to 16 columns are used, and only one of them is used for writing, and charging / discharging of the remaining bit lines is useless from the viewpoint of writing.

The present invention has been made in view of the above circumstances, and an object thereof is to prevent an increase in area and complication of control, and to be compatible with a parametric RAM having a variable size configuration, which is easy and accurate to control. Another object of the present invention is to provide a semiconductor memory device capable of achieving low power consumption and reducing current consumption during a write operation.

[0018]

In order to achieve the above object, the present invention provides a semiconductor memory device for controlling a memory operation based on an output of a dummy memory cell, wherein the data from the dummy memory cell is read at the time of reading. When the output is received, the read operation is completed, and at the time of writing,
It has a control means for ending the write operation when receiving the data output from the dummy memory cell.

Further, in the semiconductor memory device of the present invention, the control means terminates the write operation and performs the bit line precharge operation for the next cycle.

Further, according to the present invention, the bit line to which the memory cell is connected is precharged in the first half of the clock in the synchronous type,
In a semiconductor memory device for performing writing by activating the word line in the latter half, the write time is longer than the time required to invert the memory cell and shorter than 1/2 cycle time, and the bit line is discharged. It has a means for setting the time shorter than the dead time and activating the word line only for that time.

Further, according to the present invention, the bit line to which the memory cell is connected is precharged in the first half of the clock in the synchronous type,
A semiconductor memory device for performing writing by activating a word line in the latter half, including a dummy memory cell, and having means for detecting completion of writing to the dummy memory cell and controlling an active time of the word line.

According to the semiconductor memory device of the present invention, at the time of reading, the read delay of the dummy memory cells arranged in the cell array is detected and the end control of the read operation is performed. Similarly, also at the time of writing, the end control of the writing operation is performed based on the output of the dummy memory cell. Therefore, it is not necessary to provide a pulse generator dedicated to writing, an increase in area and complexity of control can be prevented, and an activation pulse that follows the delay can be generated even in a parametric RAM with a variable size configuration, which facilitates control. And can be accurate.

According to the semiconductor memory device of the present invention, the time for activating the word line is set longer than the memory cell time and shorter than 1/2 cycle. This reduces the amount of discharge on the bit lines in the non-selected columns,
The current consumption during writing can be reduced.

According to the semiconductor memory device of the present invention, the completion of writing to the dummy memory cell is detected, and the active time of the word line is controlled based on the result. As a result, even if there is a word line and bit line delay or process variations, writing to the memory cell can be guaranteed, and at the same time current consumption can be reduced.

[0025]

BEST MODE FOR CARRYING OUT THE INVENTION First Embodiment FIG. 1 is a block diagram showing a first embodiment of a semiconductor memory device according to the present invention. This device detects a read data output using a dummy memory cell and controls the memory operation in a semiconductor memory device,
The control signal based on the detection of the read data output from the dummy memory cell is used not only for reading but also for controlling the writing operation.

In FIG. 1, the same components as in FIG. 12 showing the conventional example are represented by the same reference numerals. That is,
This memory device has memory cells, for example, SRs, arranged in a matrix.
Memory cells MC1k in which AM cells are arranged and belong to the same column,
MC2k, MC3k, MC4k (four rows in FIG. 1) are connected to a pair of bit lines BLk, BLBk, and these bit lines BL
k and BLBk are connected to a sense amplifier SAk via column gates CGk and CGBk which are n-channel MOS (NMOS) transistors. In addition to the normal memory cell array, one column of dummy memory cells DMC
1, DMC2, DMC3, DMC4 are provided for each row. These dummy memory cells DMC1, DMC2,
DMC3 and DMC4 are a pair of dummy bit lines DBL and D
Connected to the BLB, and these dummy bit lines DBL, DB
LB is a dummy output determiner and control circuit (hereinafter referred to as a control circuit) 1 via column gates DCG and DCGB.
a. The memory cells and the dummy memory cells in each row share the common word lines WL1, WL2, W
These word lines WL1 and WL are connected to L3 and WL4.
2, WL3, WL4 are buffers BF1, BF2, BF
3, driven by the row decoder RDC via BF4. In addition, column gates CGk, CGBk, DCG, D
Each gate electrode of CGB is connected to a common output line of the column decoder CDC.

The control circuit 1a enables the enable signal EN when access is started during reading and writing.
At a high level, the sense amplifier SAk and the row decoder RD
C, the column decoder CDC and the write circuit 3 are supplied to activate these circuits, and when the dummy memory cells are read and the signals appearing on the dummy bit lines DBL and DBLB are received, the enable signal EN is switched to the low level. Sense amplifier SAk, row decoder RDC,
The column decoder CDC and the write circuit 3 are controlled to the inactive state.

Next, the operation of the above configuration will be described with reference to the timing chart of FIG. When reading
When the clock is changed or the address is changed and the access is started, as shown in FIG. 2A, the high level enable signal EN is sent from the control circuit 1a to the sense amplifier SAk,
It is supplied to the row decoder RDC and the column decoder CDC. As a result, the sense amplifier SAk, the row decoder RDC and the column decoder CDC are controlled in the active state. Then, in the row decoder RDC,
One word line WL to be selected is selected from the row address RAD, and the selected word line WL is driven to the high level. At the same time, in the column decoder CDC,
Column gates CGk, CGB based on column address
k, DCG, and DCGB are controlled to be conductive. This allows addressed memory cells, eg MC1k
A signal of a level corresponding to the data stored in the bit line BLk, BLBk appears on the sense amplifier S
It is amplified by Ak and output from the output circuit 4 as output data Dout.

When the word line WL is driven, the data of a predetermined dummy memory cell is transferred to the dummy bit line DBL /
It appears as a signal on DBLB and is input to the control circuit 1a. In the control circuit 1a, the dummy bit lines DBL / DBL
Based on the B signal input, it is detected that the data is output, and as a result, the enable signal EN is switched from the high level to the low level. Along with this, the sense amplifier SAk, the row decoder RDC, and the column decoder C
The DC is controlled to the inactive state, the internal read operation is completed, and the precharge operation is started for the next cycle.

At the time of writing, as shown in FIG.
The enable signal EN is set to a high level at the start of access by a mechanism similar to reading, and the write circuit 3, the sense amplifier SAk, the row decoder RDC, and the column decoder CDC are controlled to be in an active state. Then, in the row decoder RDC, the row address RA
One word line WL to be selected is selected from D, and the selected word line WL is driven so as to have a high level. At the same time, in the column decoder CDC, the column gates CGk, CGBk, DCG, DCG based on the column address.
B is controlled to be conductive. As a result, with respect to the addressed memory cell, the write data Din is propagated to the bit lines BLk and BLBk by the write circuit 3 and written in the memory cell of the address signal.

When the word line WL is driven, the data of a predetermined dummy memory cell is transferred to the dummy bit line DBL /
It appears as a signal on DBLB and is input to the control circuit 1a. In the control circuit 1a, the dummy bit lines DBL / DBL
Based on the B signal input, it is detected that the data is output, and as a result, the enable signal EN is switched from the high level to the low level. Along with this, the write circuit 3, the sense amplifier SAk, the row decoder RDC, and the column decoder CDC are controlled to the inactive state, and the internal write operation ends, and like the read operation described above, for the next cycle. Enter the precharge operation.

The reason why the write timing can be controlled by the read delay of the dummy memory cell is that the read time is longer than the write time. This is because the read operation is an operation in which the bit line is discharged from the small transistor of the memory cell, while the write operation is an operation in which the same bit line is discharged by the large size transistor (write buffer).

As described above, according to the first embodiment, the read delay of the dummy memory cells arranged in the cell array is detected to perform not only the read control but also the write operation control. Since it is not necessary to provide a pulse generator dedicated to writing, it is possible to prevent an increase in area and complication of control. In addition, even in a parametric RAM having a variable size configuration, an activation pulse can be generated following the delay, so that control can be performed easily and accurately.

Second Embodiment FIG. 3 is a circuit diagram showing a second embodiment of the semiconductor memory device according to the present invention. The device of FIG. 3 shows a specific circuit example of the conceptual memory device shown in FIG.
This is a synchronous memory device having a flip-flop for address input.

In this device, a normal memory cell MCk
Is constituted by an SRAM cell in which the inputs and outputs of the TFT load type CMOS inverters I1 and I2 are cross-coupled,
The coupling nodes are connected to bit lines BLk and BLBk via access transistors A1 and A2, respectively. The dummy memory cell DMC is an NMOS connected in series between the dummy bit line DBL and the ground line.
Transistors DT1 and DT2 and dummy bit line D
It is constituted by an NMOS transistor DT3 connected between BLB and the supply line of the power supply voltage V _CC . The gates of the NMOS transistors DT1 and DT3 are connected to the word line WL, and the NMOS transistor DT2
Is connected to the supply line of the power supply voltage V _CC .

An equalizing transistor E1 which is a p-channel MOS (PMOS) transistor is connected between the bit line pair BLk and BLBk. Furthermore, P
A precharge / pullup transistor P1 formed of a MOS transistor is connected between the supply line of the power supply voltage V _CC and the bit line BLk, and a precharge / pullup transistor P2 is supplied of the power supply voltage V _CC and the bit line. It is connected to BLBk. The gate electrodes of the transistors E1, P1, P2 are connected to the output line of the column selection signal COL of the column decoder CDC, like the gate electrodes of the column gates CGk, CGBk.

Similarly, the dummy bit line pair DBL, DBL
Between B, for equalization consisting of PMOS transistor
The transistor DE1 is connected. Furthermore, PMO
Precharge / pull-up tiger that is composed of S-transistor
Power supply voltage V _CCSupply line and bit line
Connected to DBL for precharge / pull-up
Transistor DP2 has power supply voltage V_CCSupply line and bit
It is connected to the output line DBLB. And Tran
The gate electrodes of the transistors DE1, DP1, DP2 are column
Like the gate electrodes of the gates DCG and DCGB, the column
To the output line of the column selection signal COL of the decoder CDC
It is connected.

The sense amplifier SAk includes PMOS transistors PS1, PS2 and PS3, and an inverter INV.
It is composed of S1. PMOS transistor PS
1 is connected between the bit line pair BLk, BLBk, and PMO
The S transistor PS2 is connected between the supply line of the power supply voltage V _CC and the bit line BLk, and the PMOS transistor PS3 is connected to the supply line of the power supply voltage V _CC and the bit line BLBk.
Is connected between. And the transistor PS1
The gate electrodes of PS3 are column gates CGk and CGB.
Similarly to the gate electrode of k, it is connected to the output line of the column selection signal COL of the column decoder CDC. The input of the inverter INVS1 is connected to the bit line BLk.

The control circuit 1a includes a PMOS transistor P
It is composed of D1, PD2, PD3, an inverter INVD1, and an RS type flip-flop FFD1. The PMOS transistor PD1 is a dummy bit line pair D
It is connected between BL and DBLB, and the PMOS transistor P
D2 is the supply line of the power supply voltage V _CC and the dummy bit line DB
It is connected between L, and is connected between the PMOS transistor PD3 is the supply line and the dummy bit line DBLB supply voltage V _CC. Then, the transistors PD1 to P
The gate electrode of D3 is connected to the output line of the column selection signal COL of the column decoder CDC, like the gate electrodes of the column gates DCG and DCGB. And
The input of the inverter INVS1 is connected to the dummy bit line DBL, and the output is connected to the reset terminal R of the flip-flop FFD1. The set terminal S of the flip-flop FFD1 is connected to the input line of the clock signal CLK, and the enable signal EN is output from the output terminal Q to the write circuit 3, the gate circuit 5, the row decoder RDC, and the column decoder CDC.

The writing circuit 3 is a delay circuit DL3.
1,3 input AND gate AD31, inverter INV3
1, INV32, INV33, and buffer BUF3
1. The input of the delay circuit DL31 is connected to the supply line of the enable signal EN,
The enable signal EN is delayed by a predetermined time and input to one input of the 3-input AND gate 31. The other two input terminals of the three-input AND gate AD31 are connected to the supply line of the enable signal EN and the output terminal Q of the flip-flop 7 which latches the write enable signal WEN in synchronization with the clock signal CLK. And gate AD3
The output of 1 is the buffer BUF31 and the inverter INV
It is connected to the positive side control terminal 33 and is also connected to the negative side control terminal via the inverter INV32. Then, the buffer BUF31 and the inverter INV33
Is connected to the input line of the write data Din, the output of the buffer BUF31 is connected to the bit line BLk, and the output of the inverter INV33 is connected to the bit line BLBk.
It is connected to the. The input of the inverter INV32 is connected to the output terminal Q of the flip-flop 7, and the output is connected to the gate circuit 5.

The gate circuit 5 includes transfer gates TG51, 2
Input AND gate AD51 and inverter INV5
1. One input / output terminal of the transfer gate TG51 is an inverter INVS of the sense amplifier SAk.
1 and the other input / output terminal is connected to the output circuit 4. And two-input AND gate AD51
One input terminal of the inverter INV of the writing circuit 3
32 is connected to the output, and the other input terminal is connected to the supply line of the enable signal EN. And Gate A
The output of D51 is an NMOS that constitutes the transfer gate TG51.
While connected to the gate electrode of the transistor,
The gate electrode of the PMOS transistor that constitutes the transfer gate TG51 is connected via the inverter INV51.

The address buffer 6 has a clock signal CL.
Flip-flops FF61 and FF62 that latch the address ADR in synchronization with K, and an inverter INV6
1, INV62. The output terminal Q of the flip-flop FF61 is connected to the input of the inverter INV61, and the output terminal Q of the flip-flop FF62 is connected to the input of the inverter INV62.

The row decoder RDC is composed of row address decode lines RAD1 to RAD4 and a plurality of 3-input AND gates ADR1, ADR2, .... The row address decode line RAD1 is connected to the output of the flip-flop FF61 of the address buffer 6, the row address decode line RAD2 is connected to the output of the inverter INV61, and the row address decode line RAD3 is connected to the output of the flip-flop FF63 of the address buffer 6. The row address decode line RAD4 is connected to the inverter IN.
It is connected to the output of V62. AND Gate ADR1
Is connected to the address decode lines RAD1 and RAD3 and the supply line of the enable signal EN, and the input terminal of the AND gate ADR2 is connected to the address decode line RA.
It is connected to the supply lines of D2, RAD3 and the enable signal EN.

The column decoder CDC is composed of a 2-input AND gate ADC and a buffer BUFC. One input terminal of the 2-input AND gate ADC is connected to the supply line of the enable signal EN, and the other input terminal is connected to the input line of the clock signal CLK via the buffer BUFC. And gate A
The output of DC is connected to the gate electrodes of the column gates CGk, CGBk, DCG, DCGB as a supply line of the column selection signal COL.

Next, the operation of the apparatus of FIG. 3 will be described with reference to the timing charts of FIGS. 4 and 5. At the time of reading, as shown in FIG. 4, when the clock signal CLK rises to the high level, the flip-flop FFD1 of the dummy control circuit 1 is set, and the enable signal EN is at the high level, the write circuit 3, the gate circuit 5, and the row decoder. It is output to the RDC and the column decoder CDC.
At this time, since the write enable signal EN is at low level, the output of the AND gate AD31 of the writing circuit 3 is held at low level, and the buffer BU31 and the inverter INV33 are held in the non-conducting state. And
Since the output of the inverter INV32 becomes high level, the output of the AND gate AD5 of the gate circuit 5 is held at high level, the transfer gate TG51 is held in the conductive state, and the signal transfer path between the sensor amplifier SAk and the output circuit 4 is held. Is established.

In this state, the row decoder RDC selects one word line WL to be selected from the row address RAD and drives the selected word line WL to the high level. At the same time, in the column decoder CDC, the column selection signal COL becomes high level based on the input of the clock signal CLK, and the column gates CGk, C
GBk, DCG, and DCGB are controlled to be conductive. This allows the addressed memory cell, eg M
A signal of a level corresponding to the data stored in C1k appears on the bit lines BLk and BLBk, this signal is amplified by the sense amplifier SAk, and the output circuit 4 outputs the output data Dout.
Is output as

When the word line WL is driven, the data of a predetermined dummy memory cell is transferred to the dummy bit line DBL /
It appears as a signal on DBLB and is input to the control circuit 1a. Here, the dummy memory cell DMC is adapted to output low level data. Therefore, when the dummy data is read, the output signal DS of the inverter INVD1 of the control circuit 1a transits to the high level, and as a result, the flip-flop FFD1 is reset and the enable signal EN switches to the low level. As a result, the AND gates ADR1 and AD of the row decoder RDC are
R2, ..., AND gate AD of column decoder CDC
C and the AND gate AD51 of the gate circuit 5 are turned off to complete the internal read operation and start the precharge operation for the next cycle.

At the time of writing, as shown in FIG. 5, when the clock signal CLK rises by a mechanism similar to that of reading, the flip-flop FFD1 of the dummy control circuit 1 is set, and the enable signal EN is at the high level, and the writing circuit 3, It is output to the gate circuit 5, the row decoder RDC, and the column decoder CDC. At this time, since the write enable signal EN is at high level, the output of the AND gate AD31 of the writing circuit 3 is held at high level, and the buffer BU31 and the inverter INV33 are held conductive. Thus, the write data D
in is propagated to the bit lines BLk and BLBk. Since the output of the inverter INV32 becomes low level, the output of the AND gate AD5 of the gate circuit 5 is held at low level, the transfer gate TG51 is held in the non-conductive state, and the sensor amplifier SAk and the output circuit 4 are connected. No signal transfer path is established.

In this state, the row decoder RDC selects one word line WL to be selected from the row address RAD and drives the selected word line WL to the high level. At the same time, in the column decoder CDC, the column selection signal COL becomes high level based on the input of the clock signal CLK, and the column gates CGk and CG.
Bk, DCG, and DCGB are controlled to be conductive. This causes the write circuit 3 to write the write data Din to the bit line BL in the addressed memory cell.
k, BLBk, and written into the memory cell of the address signal.

When the word line WL is driven, the data of a predetermined dummy memory cell is transferred to the dummy bit line DBL /
It appears as a signal on DBLB and is input to the control circuit 1a. When the dummy data is read, the output signal DS of the inverter INVD1 of the control circuit 1a transits to the high level, and as a result, the flip-flop FFD1 is reset and the enable signal EN switches to the low level. As a result, the AND gate ADR of the row decoder RDC
1, ADR2, ..., AND gate ADC of column decoder CD, and AND gate AD3 of write circuit 5
1 is turned off, the internal write operation is completed, and the precharge operation is started for the next cycle.

Since the write delay is shorter than the read delay as described above, even if the self-time circuit is constructed by using the read delay of the dummy memory cell as described above, the margin is increased and the operation is not performed. No effect.

Parametric RAM of variable size because dummy memory cells in the actual cell array are used
But you can reproduce the delay that matches the size. Further, it is desirable that the dummy memory cell is arranged at a position farthest from the row decoder in the cell array so that the worst access can be emulated.

Also in the second embodiment, the same effect as that of the above-described first embodiment can be obtained.

Third Embodiment FIG. 6 is a circuit diagram of a synchronous type memory device which precharges a bit line to which a memory cell is connected in the first half of a clock and activates a word line in the latter half of the clock to perform writing. The same components as those in FIG. 13 showing the conventional example are denoted by the same reference numerals. That is, in this circuit, the memory cells MC1k, MC1m, etc. are shown as an example of an SRAM cell composed of a flip-flop in which the input and output of the inverters I1, I2 are connected, and the memory cells MC1k, MC1k, Access transistors A1 and A2 of MC1m
Of the gate electrodes are connected to a common word line WL1 or the like.

At the time of writing, the row decoder RDC
, One word line WL to be selected is selected from the row address RAD. The selection signal is supplied to one input terminal of a predetermined 2-input AND gate AD1, AD2, .... The output signal S10 of the timing adjustment circuit 10 based on the clock signal CLK is supplied to the other input terminal of the 2-input AND gate AD1 or the like. Then, the selected word line WL is driven by the pulse having the width D from the fall of the clock signal CLK. This width is long enough to complete writing to the memory cell and is adjusted to be less than half the minimum cycle used and less than the time the bit line is discharged,
Is set.

The bit line pair BLk, BLBk, BL
m, BLBm are column gates CGk, CGBk, CG
m, CGBm to the data lines D, DB. Column gates CGk, CGBk, CGm, CGBm
In the column decoder CAD from the column address CAD, only one pair is controlled to be in the ON state, and the rest is controlled to be in the OFF state. The write data Din is stored in the buffer BUF2.
Is latched in the latch circuit LTC at the timing of the fall of the clock signal CLK.
The output data of the latch circuit LTC is stored in the buffer BU.
It is propagated to the data line D via F3 and BUF4, and is propagated to the inversion data line DB via buffers BUF3, BUF5 and INV2. Also, PTk, PTBk, PT
m and PTBm are precharge transistors for bit lines, and the gate electrode receives the clock signal CLK via the buffer BUF1 to be turned on / off.

FIG. 7 is a circuit diagram showing a configuration example of the timing adjustment circuit 10. This timing adjustment circuit 10
The delay circuit 101, the inverters 102 and 103, and the NOR gate 104 are included. Delay circuit 101
And the inverter 102 are connected in series, and the delay circuit 101
Is connected to the input line of the clock signal CLK, the output of the inverter 102 is connected to one input terminal of the NOR gate 104, and the other input terminal of the NOR gate 104 is connected to the input line of the clock signal. And
The output of NOR gate 104 is connected to the input of inverter 103. Here, as described above, the delay time of the delay circuit 10 is set so that the period for activating the word line is shorter than the time (tw) required for writing and shorter than 1/2 cycle time.

Next, the write operation with the above configuration will be described with reference to the timing chart of FIG. In such a configuration, at the time of writing, as shown in FIG. 14, while the clock signal CLK is at the high level, the levels of all the word lines WL are held at the low level, and all the bit lines B are held.
Lk, BLBk, BLm, BLBm are precharged to the power supply voltage V _CC level (high level). Then, when the clock signal CLK is switched to the low level, the word line drive time is adjusted in the timing adjustment circuit 10 based on the clock signal CLK, and the selected word line WL is changed from the fall of the clock signal CLK based on the signal S10. It is driven by the D pulse.

At this time, the selected word line (WL _i )
Becomes high level, and the selected column signal CLM is held at high level. At this time, one of the bit lines BLk and BLBk is held at the high level and the other is changed to the low level according to the value of the write data Din, and the data is written to the memory cell MC1k or the like.

Unselected bit lines BL _m not selected
The waveform of BLB _m or the like is as shown in FIG. That is, the non-selected bit line in which the word line WL becomes low level after the delay D becomes floating and the discharge is stopped,
The bit line amplitude ΔV is reduced, and the current consumption is suppressed. The waveform shown by the broken line in FIG. 8 indicates the case of the conventional device of FIG. Depending on the data of cell MC1m, etc.
Either one of them is discharged to a low level through the memory cell.

As described above, according to the third embodiment, in the synchronous SRAM, the time for activating the word line is set to be longer than the memory cell time and shorter than 1/2 cycle. It is possible to reduce the discharge amount of the bit line of the non-selected column and reduce the current consumption during writing.

Fourth Embodiment FIG. 9 is a circuit diagram showing a fourth embodiment of the semiconductor memory device according to the present invention. This device includes a dummy word line DWL and dummy bit lines DBL, D in the circuit shown in FIG.
A BLB and a dummy memory cell DMCM are provided, the completion of writing in the dummy memory cell DMCM is detected, and the active time of the word line WL1 and the like is controlled. Note that, in FIG. 9, ordinary memory cells and the like are omitted for simplification, and only essential parts are shown.

The dummy memory cell DMCM is an SRAM cell consisting of a flip-flop in which the inputs and outputs of the inverters I11 and I12 are connected to each other, like the normal memory cell, and the gate electrodes of the access transistors A11 and A12 are dummy word lines DWL. It is connected to the. And
The level of the node of this cell is inverter INV1.
3, INV14 can be taken out. Further, the dummy memory cell DMCM is configured to be reset by the clock signal CLK via the NMOS transistor NT11 and the inverter INV14. Further, the NMOS transistor NT12 is
This is a dummy transistor for guaranteeing symmetry.

Column gates CGM and CGBM are connected to the dummy bit lines DBL and DBLB, and the column gate CGM is connected to the power supply voltage V _CC through the buffer BUF11.
, And the column gate CGBM is connected to the supply line of the power supply voltage V _CC via the inverter INV16. The gate electrodes of the column gates CGM and CGBM are connected to the output of the 2-input AND gate AD12. One input terminal of the 2-input AND gate AD12 is connected to the supply line of the power supply voltage V _CC , and the other input terminal is connected to the input terminal of the clock signal CLK.

The output of the inverter INV14 is passed through the inverter INV17 to the AND gate AD12 for driving the dummy word line DWL and the normal word line WL.
It is connected to one input terminal of driving AND gates AD1, .... In other words, the signal taken out from the node connected to the dummy transistor NT12 of the dummy memory cell DMCM is WMASK so that the active time of the word line can be controlled.

Next, the write operation of the device of FIG.
This will be described with reference to the timing chart of FIG. As shown in FIG. 10, when the clock signal CLK is switched to the low level, the dummy memory cell DMCM is reset, the signal WMASK becomes the high level, the selected word line WL becomes the active high level, and at the same time, the dummy word line DWL also goes high. At this time, the column gates CGM and CGBM are rendered conductive, and as a result, the dummy bit line DBL is driven to the high level and the dummy bit line DBLB is driven to the low level. As a result, the data "1" is written through the access transistor A11 of the dummy memory cell DMCM, the writing is completed, and when the writing is completed, the signal WMASK becomes low level and the selected word line WL becomes inactive low level. At the same time, the dummy word line DWL also goes low.

In this case, the node of the dummy memory cell DMCM has a transistor NT11,
Since the NT12, the inverter 13, and the INV14 are connected, the load is large, the write time becomes longer than that of a normal memory cell, and the write time tw can be guaranteed even if there is a word line delay or a bit line delay. Become. This is advantageous when the write time tw changes due to variations in the parametric SRAM module, process, etc. that require changing the memory array configuration.

As described above, according to the fourth embodiment, since the dummy word line, the dummy bit line, and the dummy memory cell are used for the write control, the word line and the bit line delay, or the process variation. Even if there is such a case, writing to the memory cell can be guaranteed, and at the same time, current consumption can be reduced.

[0069]

As described above, according to the present invention,
Since there is no need to provide a pulse generator for writing only,
It is possible to prevent an increase in area and complicated control. In addition, even in a parametric RAM having a variable size configuration, an activation pulse can be generated following the delay, so that control can be performed easily and accurately.

In the synchronous memory device, the time for activating the word line is longer than the memory cell time,
By making the cycle shorter than 1/2 cycle, it is possible to reduce the discharge amount of the bit line of the non-selected column and reduce the current consumption during writing. By using the dummy memory cells, it is possible to guarantee writing to the memory cells even if there are word line and bit line delays or process variations, and at the same time it is possible to reduce current consumption.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of a semiconductor memory device according to the present invention.

FIG. 2 is a timing chart of the device shown in FIG.

FIG. 3 is a block diagram showing a second embodiment of a semiconductor memory device according to the present invention.

FIG. 4 is a timing chart at the time of reading by the device of FIG.

5 is a timing chart at the time of writing in the device of FIG.

FIG. 6 is a circuit diagram showing a third embodiment of a semiconductor memory device according to the present invention.

7 is a circuit diagram showing a specific example of a timing adjustment circuit of the device of FIG.

8 is a timing chart at the time of writing in the device of FIG.

FIG. 9 is a circuit diagram showing a fourth embodiment of a semiconductor memory device according to the present invention.

10 is a timing chart at the time of writing in the device of FIG.

FIG. 11 includes a circuit that detects the output of read data by using a dummy memory cell and ends the read operation, and a timing circuit that internally generates a write pulse, and ends the write operation after a fixed time. It is a conceptual diagram of the conventional example of a memory device.

12 is a timing chart at the time of reading and writing of the device of FIG.

FIG. 13 is a circuit diagram of a conventional memory device that is synchronous and precharges a bit line to which a memory cell is connected in the first half of a clock and activates a word line in the second half for writing.

14 is a timing chart at the time of writing in the device of FIG.

[Explanation of symbols]

 RDC ... Row decoder CDC ... Column decoder WL1 to WL4 ... Word line DWL ... Dummy word line BLk, BLBk, BLm, BLBm ... Bit line DBL, DBLB ... Dummy bit line MC1k to MC4k ... Memory cells DMC1 to DMC4, DMCM ... Dummy memory Cell SAk ... Sense amplifier 1a ... Dummy judging device and control circuit 3 ... Write circuit 4 ... Output circuit 5 ... Gate circuit 6 ... Address buffer

Claims (4)

[Claims] 1. A semiconductor memory device for controlling a memory operation based on an output of a dummy memory cell, wherein when the data output from the dummy memory cell is received at the time of reading, the read operation is ended and at the time of writing. A semiconductor memory device having control means for terminating a write operation when receiving data output from the dummy memory cell. 2. The semiconductor memory device according to claim 1, wherein said control means terminates the write operation and performs a bit line precharge operation for the next cycle. 3. A semiconductor memory device in which a bit line to which a memory cell is connected is precharged in the first half of a clock, and a word line is activated in the second half to perform writing, in which the write time is inverted by the memory cell. Set to a time longer than the time required for
A semiconductor memory device having means for activating a word line only during that time. 4. A semiconductor memory device that precharges a bit line to which a memory cell is connected in the first half of a clock and activates a word line in the second half to perform writing, the dummy memory cell being provided, Means for detecting the completion of writing to the word line and controlling the active time of the word line.