JPH09127219A - Superconductive circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce noise and erroneous function by interrupting source current supply to a read circuit when a comparator is making a decision whether a signal from an SQUID is present or not. SOLUTION: Output signal from an SQUID 11 is passed through a load inductance and a load resistor and inputted, as a magnetic signal, to a comparator 12 comprising a Josephson element which then outputs the variation of inductance to a read circuit 13. In this regard, the comparator 12 makes a decision whether a signal from the SQUID 11 is present or not and if a signal is present, and the circuit 13 is notified that the signal from the SQUID 11 is 1 when a source current is fed. If no signal is present, no flux is inputted even if the source current is fed and since no voltage is generated, the circuit 13 is notified that the signal from the SQUID 11 is 0. Since no source current is fed to the circuit 13 when the comparator 12 is making a decision, the comparator 12 is not susceptible to the noise generated from other circuit and thereby erroneous function is reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a superconducting circuit formed by using a superconductor, and more particularly to a superconducting circuit which has no malfunction and can be highly integrated with low noise.

[0002]

2. Description of the Related Art One method of realizing a digital SQUID is disclosed in Japanese Patent Laid-Open No. 64-21379. A method of driving a multi-channel digital SQUID magnetometer having a plurality of digital SQUIDs is disclosed in, for example, Japanese Patent Laid-Open No. 3-197885.

FIG. 4 shows a conventional digital SQ.
It is a circuit diagram which shows ID. Digital S in conventional technology
In the QUID, a superconducting quantum interference device that is a sensor is driven by an alternating current source 59, and a positive or negative pulse is output depending on the magnitude of the input magnetic flux. The magnitude of the magnetic flux to be measured can be obtained by counting the number of positive or negative pulses and feeding back a current proportional to the difference.

Next, the operation of this digital SQUID will be described with reference to FIG. Pickup coil 700
The signal magnetic flux detected in (1) is input to the SQUID by the input coil 220. SQUID is an alternating current source 59
And is composed of a Josephson junction 110 and an inductance 221. In the SQUID, a positive or negative current pulse according to the input magnetic flux corresponding to the difference between the magnetic flux signal amount from the input coil 220 and the feedback magnetic flux amount is supplied to the AND gate 80 which is also driven by the alternating current source.
1. Switching circuit 8 composed of OR gate 800
It outputs to the feedback circuit via 10. The feedback circuit consists of a superconducting loop including the inductance 223 and the Josephson junction 111, and a write gate that converts the pulses sent through the switching circuit 810 into flux quanta.
This write gate consists of another inductance 222 that is magnetically coupled to the inductance 223. The pulse passing through the write gate is converted into a flux quantum and stored in the superconducting loop including the inductance 224.

The inductance 224 is magnetically coupled 900 with the inductance 221 of the SQUID, and the magnetic flux quantum stored in the superconducting loop including the inductance 224 is fed back to the SQUID. Therefore, the feedback circuit is SQU
It is possible to measure the pulse output from the ID and feed back the magnetic flux quantum corresponding to the result to the SQUID.

[0006]

In the above-mentioned prior art, the circuits other than the SQUID used for the purpose of discriminating the magnitude of the signal from the SQUID and digitizing it use a tunnel type Josephson junction. , A latching type circuit is used. In order to reduce the noise with respect to the SQUID, it is effective to reduce the superconducting critical current of the Josephson device used in the circuits other than these SQUIDs, especially in the circuits arranged close to the SQUID. However, in the case of a latching type circuit, the superconducting critical current is generally 50 μ due to the influence of thermal noise.
If it is A or less, there is a problem that the probability of occurrence of malfunction increases. In particular, in a latching type circuit, once a malfunction occurs, an incorrect result is continuously output unless the power supply is returned to zero. For this reason, it is not possible to reduce the superconducting critical current to 50 μA or less in the conventional technique, and therefore the SQUID
It was not possible to reduce the noise given to the SQUID by the circuits other than.

SUMMARY OF THE INVENTION An object of the present invention is to solve the problems of the prior art and to provide a superconducting circuit including SQUID, which is resistant to noise, has less malfunctions, and is suitable for integration.

[0008]

A problem with the above-mentioned prior art is that at least in a superconducting circuit including an SQUID, a comparator and a readout circuit, the comparator is constructed by using an overdamping non-latch type Josephson element, and It has a function of discriminating the magnitude of the analog output signal from the SQUID, the reading circuit has a function of reading the digital output signal from the comparator, and the comparator discriminates the magnitude of the signal from the SQUID. This can be solved by configuring so that the power supply current does not flow in the reading circuit while the reading circuit is in operation.

[0009]

BEST MODE FOR CARRYING OUT THE INVENTION The present invention will be described in detail by the following examples.

As shown in FIG. 1, the superconducting circuit according to the present invention is composed of at least SQUID 11, a comparator 12 formed by using an overdamping non-latch type Josephson element, and a reading circuit 3. FIG. 2 shows a circuit diagram of the comparator according to the present invention. Comparator 2 is rfSQUID 201, and d
and cSQUID 202. SQUID
The output signal from 11 is input to the rfSQUID 201 as a magnetic signal by the load inductance 21 and the load resistance 22 provided in the SQUID 11. rfS
The change in the inductance due to the input of the signal to the QUID 201 is transmitted to the dcSQUID 202, and the change is input to the read circuit 13.

The superconducting circuit shown in this embodiment was manufactured by using Nb for the superconductor, Nb / AlO _x / Nb for the Josephson junction, and MoN _x for the resistor. The critical current value of the Josephson junction was set to 25 μA, and the inductance of SQUID1 was configured such that the product of the total critical current value and the inductance was 1 magnetic flux quantum (1Φ ₀ ). Similarly, the rfSQUID 201 and dc forming the comparator 2
The critical current value of the Josephson junctions 241 and 242 of the SQUID 202 is also 25 μA, and the inductances 231 and 232 are the Josephson junctions 24 of the respective elements.
The product of the critical current value of 1,242 and the inductance was set to be equal to one magnetic flux quantum (1Φ ₀ ).

The rfS constituting the comparator 12 is shown in FIG.
The timings at which the bias current and the power supply current of the QUID 201 and the dcSQUID 202 are passed are shown.
First, the power supply current Icp26 is passed through the rfSQUID 201. Next, the bias current Icb25 is passed. At this time, rf
The SQUID 201 discriminates the presence or absence of a signal from the SQUID, and if there is a signal current Is29 from the SQUID, r
One magnetic flux quantum is input to fSQUID201. rfS
While QUID 201 keeps that state, dcSQ
When the power supply current Icrp27 is passed through the UID 202, the terminal 2
Since 8 is in the voltage state, the signal from SQUID1
The fact that it is 1 is transmitted to the read circuit 13. on the other hand,
If there is no signal current Is29 from SQUID, rfS
Since no magnetic flux is input to QUID 201, dcSQ
Even if the power supply current Icrp27 flows through the UID 202, no voltage is generated at the terminal 28. Therefore, it is transmitted to the read circuit 13 that the signal from SQUID1 is 0. Further, while the comparator 12 is performing the above operation, no power supply current is passed through the read circuit 13. With such a configuration, the comparator is not affected by noise generated by other circuits, so that malfunction of the comparator can be reduced.

Further, in the present invention, since the circuit such as the comparator is constructed by using the non-latch type Josephson element of overdamping, even if the influence of thermal noise is exerted,
The circuit can return to its original state in a very short time. Therefore, like when using the latch type Josephson element,
Since the malfunction due to thermal noise is not stored and accumulated for a long time, the probability of malfunction is reduced. These features are not unique to this embodiment, but are general features obtained by using the configuration of the present invention. The over-damping non-latch type Josephson element may be realized by providing a shunt resistor in the tunnel type Josephson element to eliminate the hysteresis in the current-voltage characteristic. Alternatively, a non-latch type Josephson element such as a microbridge due to superconducting weak coupling may be used.

The superconducting critical current of the non-latch type Josephson device can be about 30 μA, which is smaller than 50 μA used in the conventional Josephson logic circuit. It is possible to further reduce the size to about 10 μA. Generally, it is desirable from the viewpoint of noise reduction that the superconducting critical current of the Josephson junction element used for SQUID be equal to or smaller than that. Also in this case, the value is generally about 10 μA.

In addition to the above configuration, the read circuit 1
3 is configured such that the digital output signal from the comparator 12 is repeatedly read a plurality of times and the read result with the highest appearance frequency is output as the final fixed value, so that malfunctions of the entire circuit can be further reduced. did it. Since the reading circuit 13 reads a plurality of signals from the comparator 12, even if the comparator 12 malfunctions, the output result of the entire circuit is not affected. Therefore, the critical current value of the comparator 12 can be made smaller than in the conventional case.

As described above, in the present invention, since the malfunction due to thermal noise is not stored and accumulated for a long time, the probability of malfunction is reduced, and therefore it is easy to repeatedly read and estimate the correct result. become. These features are not unique to this embodiment, but are general features obtained by using the configuration of the present invention. As a result, even if the comparator 12 and the SQUID 11 are arranged close to each other, the current flowing through the comparator 12 is small, so that magnetic mutual interference between the two can be reduced. As a result, the SQUID 11 and the comparator 12 can be stably operated, and the entire circuit can be integrated.

[0017]

As described in detail above, by constructing the superconducting circuit as in the present invention, it is possible to realize a superconducting circuit which has few malfunctions and which can be highly integrated with low noise.

[0018]

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a superconducting circuit according to the present invention.

FIG. 2 is a circuit diagram of a comparator according to the present invention.

FIG. 3 is a diagram showing an operation timing of the superconducting circuit according to the present invention.

FIG. 4 is a diagram showing a conventional example.

[Explanation of symbols]

11 ... SQUID, 12 ... Non-latching comparator
, 13 ... readout circuit, 21 ... load inductance,
22 ... Load resistance, 231, 232 ... Inductance, 2
41,242 ... Josephson junction, 25 ... Bias current, 26, 27 ... Power supply current, 28 ... Terminal, 59 ... AC current source, 320 ... Output processing circuit, terminal to display circuit, 11
0, 111 ... Josephson junction, 220 ... Input coil, 221, 222, 223, 224 ... Inductance, 320 ... Signal output terminal, 700 ... Pickup coil, 800 ... Logical sum gate, 801 ... Logical product gate
G, 810 ... Switching circuit, 900: Magnetic coupling.

Claims (3)

[Claims] 1. A superconducting circuit comprising at least an SQUID, a comparator and a readout circuit, wherein the comparator is constituted by using an overdamping non-latch type Josephson element and discriminates the magnitude of an analog output signal from the SQUID. Has the function to
The read circuit has a function of reading a digital output signal from the comparator, and a power supply current does not flow in the read circuit while the comparator discriminates the magnitude of the signal from the SQUID. And superconducting circuit. 2. The superconducting critical current of a Josephson junction element included in the comparator and the readout circuit is 3
The superconducting circuit according to claim 1, which is 0 μA or less. 3. The read circuit according to claim 1, wherein the read circuit repeatedly reads the digital output signal from the comparator a plurality of times and outputs the read result having the highest appearance frequency as a final definite value. The superconducting circuit described.