JPH0785104B2 - Superconducting quantum interference device - Google Patents

Description

DETAILED DESCRIPTION [Outline] A pulse and a triangular wave or a sawtooth wave are applied to the bias and magnetic field coupling line of the SQUID, and the value of the magnetic flux or the measured current is extracted as the number of pulses. Processing and return by superconducting circuit is possible, and it can be integrated into one chip.

[Industrial application field]

The present invention is a current or a magnetic flux that can be converted into a current, a voltage,
The present invention relates to a superconducting quantum interference device (SQUID) used for measuring resistance and the like.

[Conventional technology]

SQUIDs are high density detectors, and in particular SQUID magnetometers are denser than any other magnetometer. Fig. 15 shows a conventional magnetometer called DC SQUID. (A) is an equivalent circuit of a two-junction superconducting quantum interference device (DC SQUID), where J ₁ and J ₂ are Josephson junctions and l ₁ supplies a bias current I to a superconducting loop including J ₁ and J _2. It is a circuit to do. l ₂ is a signal line through which a signal current I _X flows, and in the case of a magnetometer, this current I _X is supplied by a pickup coil that links the magnetic flux to be measured.
The superconducting loop including the junctions J ₁ and J ₂ and the signal line l ₂ are coupled by the mutual inductance M. Josephson junction J ₁ , J ₂
Is often a junction such as a bridge junction that does not inherently have hysteresis in the IV characteristics, or a tunnel junction that has hysteresis in the IV characteristics with a resistor connected in parallel to eliminate the hysteresis (example shown). Used. IV
The characteristics are as shown in Fig. 15 (b), and the curve C ₁ is MI _X = nφ
_{If 0} , the curve C ₂ is Is the case.

In the superconducting circuit, the inductance is dominant, and in (a), this is represented by a coil symbol as shown.
When the bias current I is supplied, if the junction J ₁ side and J ₂ side have the same inductance, I / 2 flows through each. When this current I / 2 is below the critical value, the Josephson junction is in a no-voltage state, and the voltage V at the output end Out is zero. The critical value is the signal current I
_{It depends on X} , and if I _X = 0, then I _C0 . When I _X is gradually increased from zero critical value I _C is down gradually, I in MI _X = φ _0/2
Become _C1 . When I _X becomes larger, the critical value begins to rise, and MI
It becomes I _C0 at _X = φ ₀ . When it gets bigger, it starts to descend again,
The same changes are repeated thereafter. After all, MI _X = nφ ₀ (n = 0,1,
2, ...), I _C = I _C0 , MI _X = (n + 1) φ ₀ , and I _C = I _C1 , which changes periodically. Here, φ ₀ is the flux quantum, n = 0 is 0 mode, n = 1 is 1 mode, ...
, Which means that φ ₀ is 0, 1, 2, ... in the superconducting loop. When the bias current flowing in the Josephson junction exceeds a critical value, the junction is brought into a voltage state, and the voltage V is caused by I _{X along the} curves C ₁ and C ₂ or a curve between them (not shown) to be I Increase accordingly. Relationship between MI _X and V is 15th
As shown in FIG. 6C, a periodic change is shown.

In FIG. 15 (c), MI _X = 0 and V is a non-zero value V ₁
Therefore, I exceeds I _C and has a value such as I _{B in} (b). If I _X is increased in this state, the curve goes down and V becomes large, and at C ₂ , the curve goes up and the curve goes up and V goes down.
(C) shows this repetition. I _X is the change in the magnetic flux linked to the pickup coil in the case of a magnetic flux meter, and in the case of a magnetometer, I _X can be obtained by knowing V from (c).
By measuring the voltage V at the output end Out in the figure, the magnetic flux linked to the pickup coil can be known with a magnetometer. However, as shown in FIG. 15 (a), V changes periodically, so even if a certain value V ₃ is obtained, it is not clear whether MI _X is MI _X1 or MI _X2. Absent. In addition, since there is a problem that the output of the bias current source and the drift of the DC amplifier that measures the output voltage V affect the output, as shown in FIG. 16, the operating point is always V-MI _X. A method of flowing a feedback current so as to reach the minimum point of the characteristics is used.

In Fig. 16, the PC is the pickup coil described above, and the signal line
A signal current I _{X0 is} passed through l ₂ . l ₃ is a signal line through which the feedback current If flows. In this circuit, the sum of these currents I _X0 + If becomes the signal current I _X in FIG. The bias current I with I _B of (b), thus V-I _X characteristics are as view the 15 (c). OS
C is an oscillator whose output k sin ω t is a lock-in amplifier A ₃
Becomes the reference signal Ref. A ₁ and A ₂ are amplifiers, and A ₁ amplifies the voltage V at the output end Out and applies it to the lock-in amplifier A ₃ . The lock-in amplifier A ₃ has a reference signal Ref of the input voltage.
An output of the same frequency component as that of the above, but depending on the amplitude and phase is generated as a direct current (product output, + v _{1 for} in-phase, −v for anti-phase)
₂ , 0 if there is a 1/4 cycle shift), the amplifier A ₂ amplifies this and outputs it to the signal line l ₃ through the resistor R _F. The output of the oscillator OSC is also applied to the signal line l ₃ via the capacitor C, so that the feedback current If has the form I ₀ + k sin ω t.

Since the signal current has a sin ω t component of the oscillator OSC, the output voltage V also has a sin ω t component. Lock-in amplifier A ₃
Outputs a positive voltage if this is the same phase, and a negative voltage if it is the opposite phase, and this will increase or decrease the output I _{0 of} A ₂ and eventually the operating point will be the minimum voltage indicated by Min in Fig. 15 (c). Make a point. This can be simply explained as follows. That is, If the current I ₀ supplied from the amplifier A ₂ is I _O1 , If becomes I _{f1 in} FIG. 15 (b), and when it increases, V decreases, which is inverted by A ₁ and increases. Be in phase with. Therefore, the output of the lock-in amplifier A ₃ is positive and I _O1 increases. When I ₀ is I _O2
If becomes I _{f2 in} FIG. 15 (c), V increases as it increases, is inverted and decreased at A ₁ , and is in anti-phase with Ref. Therefore A
The output of ₃ becomes negative and I _O2 decreases, thus eventually reaching the Min point.

The signal current I _{X0 is set} to 0, the circuit is settled to the Min point, the output current of the amplifier A ₂ at that time (assumed to be I ₀₀ ) is obtained, and I _X0 is passed this time, and the output current of the amplifier A ₂ is I _If it becomes ₀ , the signal current I _X0 is obtained with I _X0 = I ₀₀ −I ₀ .

[Problems to be solved by the invention]

As shown in FIG. 16, the conventional SQUID has an analog output V, and in order to determine the operating point by using the analog voltage V, analogs such as low noise amplifiers A ₁ and A ₂ and lock-in amplifier A ₃ are used. Need a circuit. Since these usually operate at room temperature, thermal noise is larger than that of SQUID elements at liquid helium temperature, which causes a decrease in sensitivity.

There is an example of using a GaAs FET operating at liquid helium temperature for the first stage amplifier, but it is not easy to make an integrated circuit that integrates them because the manufacturing process is different from SQUID composed of Josephson junction.

The present invention enables the auxiliary circuit to operate on a superconducting circuit including a Josephson junction and be configured on the same chip.
Is to provide.

[Means for solving problems]

In the present invention, in order to be easily handled by a superconducting circuit including a Josephson junction, the bias of the SQUID is given as a pulse, and its output becomes a pulse (digital). The principle diagram is shown in FIG.

The equivalent circuit of FIG. 1 is not much different from that of FIG. 15 (a), but the bias current is the pulse current I _B (t) as shown in the figure, and the signal lines are l ₂ and l ₄ and l ₂ is the measured current I. _X is passed, and a triangular wave current I _C (t) is passed through l ₄ . A pulse voltage appears at the output terminal Out and is counted by the counter CTR. It is desirable that the Josephson junctions J ₁ and J _{2 in} this circuit have hysteresis, unlike FIG. 15 (a). Frequency of triangular wave current I _C (t)
f _C is set sufficiently smaller than the frequency f _B of the bias pulse current I _B (t). FIG. 2 shows threshold characteristics and operating points.

[Operation] When the bias current exceeds the threshold value, the Josephson junction enters a voltage state, but this threshold value changes depending on the signal current. In FIG. 1, the signal current is I _X + I _C , and when it becomes large in the positive and negative directions, the bias current I _B becomes a voltage state even if it is small. A curve C shows a voltage / no-voltage state boundary, and a voltage state is above the curve C and a no-voltage state is below the curve C. When the amplitude of the bias current I _B should choose as illustrated for threshold characteristic C, (if the I _C + I _X Ith or higher) at the right side of the straight line D the voltage state when the bias pulse is present, be a non-voltage when no , A pulse voltage V similar to the bias pulse is obtained from the output terminal Out, and on the left side of the straight line D (when I _C + I _X is less than Ith) there is no voltage regardless of the presence or absence of the bias pulse, and the output terminal Out is output. No pulse voltage appears.

When the pulse voltage appears at the output terminal Out, T, and the amplitude of I _C (t) is I _C0 , The number m of pulse voltages appearing in this period T is m = f _B · T,
Therefore Is. Since f _B , f _c , I _C0 and Ith are known, the measured current I _X is known when m is measured. The number of pulses m can be counted by a counter, and a digital element such as a counter can be easily constructed by a superconducting circuit including a Josephson junction.
It is easy to incorporate the accessory circuit into the same chip as D.

(Modification) The threshold characteristic may be asymmetrical, or a part of the bias current may be shunted to be flown to the signal line. Even in this case, similar operation can be obtained. The bias pulse number I _B (t) is not limited to the rectangular wave, and both I _B (t) and I _C (t) may be offset. It can be said that the control current I _C (t) swings a threshold value and searches for a point that exceeds the threshold value with the bias pulse I _B (t) having a constant peak value. Therefore, as long as it has a gradually increasing portion, it is not limited to a triangular wave but may be a sawtooth wave, a trapezoidal wave or the like, and more generally a waveform having no linear region with respect to time, for example, a sine waveform. If the nonlinearity is known, such as a sine wave, the measured current can be calculated from the output count number m.

FIG. 3 shows an example in which I _B (t) and I _C (t) have positive and negative symmetrical waveforms and the threshold characteristic is asymmetric. The threshold characteristic C in this example is a ratio of the critical currents of the Josephson junctions J ₁ and J ₂ to about 1: 3.
Can be obtained by Generally, by changing this ratio, the value of the loop inductance, and the bias current injection point into the loop, various forms of the threshold characteristic C can be obtained. Further, in this example, the bias current I _B (t) is not a rectangular wave, and steps are provided as shown in the figure to shorten the time for reaching the peak value.
This makes it less susceptible to malfunction due to thermal noise or the like that may occur when the operating point approaches the threshold value.

Also in this FIG. 3, a pulse is generated at the output terminal Out at a portion where I _C (t) + _IX exceeds the point Ith where the peak level of I _B intersects with the threshold characteristic C, and the numbers m ₁ and m ₂ are counted. Gives I _X. That is, on the positive side of I _C (t) + I _X Holds, and therefore On the negative side of I _C (t) + I _X Holds, and therefore From these equations (2) and (3), I _X is Becomes In FIG. 3, there is an advantage that the measured current I _X can be obtained without knowing the value of Ith.

The number of pulses m, m ₁ and m ₂ are several in FIGS. 2 and 3, but
Actually, increase the accuracy by setting a large number such as 100 pieces.

The threshold characteristic is made asymmetric in FIG. 3 so that only the positive wave output of the bias pulse appears on the right side of the threshold characteristic and only the negative wave output appears on the left side of the threshold characteristic. If it is made symmetrical, positive and negative waves will appear on the left and right sides, respectively, which must be processed, which is troublesome.

〔Example〕

FIG. 4 shows a circuit configuration as a magnetometer with a feedback circuit made of a superconducting circuit. Oscillator 10 for generating a sine wave of frequency f _B, 12 in JJ pulser, the pulse shown waveforms of the same frequency sine wave of a frequency f _B and the (peak period is short pulses), which bias pulse I _B (t ) Is supplied to SQUID. The output frequency f _B of the oscillator 10 is divided by the frequency divider 14 and passed through a low pass filter LPF to generate a triangular wave I _C (t) of frequency f _C.
And supply it to the signal line l ₄ . The output pulse from the output terminal Out is supplied to the up / down counter CTR, and the polarity detection circuit 18 discriminates between positive and negative waves, and the counter CTR is caused to upcount u for a positive wave and downcount d for a negative wave. Therefore, the count value of the counter CTR is the above-mentioned m ₁ -m ₂ , and this becomes the output of this magnetometer circuit. This output is also
It is added to the PID control circuit 22 to become a P (proportional) component, a D (derivative) component, and an I (integral) component of feedback control, and the sum of these components is D / A converted by a converter 24 to obtain a feedback current If. It is applied to the signal line l ₃ to control the output voltage V described in FIG. 15 to the minimum point Min.

The SQUID magnetometer of FIG. 4 is also a counter CTR, PID control circuit 2
2 and other accessory circuits are required, but these can be configured with superconducting circuits, etc., and can be integrated into a single chip with the SQUID body.
Next, a configuration example of each unit is shown.

An example of the configuration of the up / down counter CTR is shown in FIGS. The counter CTR has the same configuration as shown in FIG.
Circuits C1, C2 for stages are connected in cascade for the required number of stages, and the first stage C1 receives the clock CK, ▲ ▼ and receives the first count value.
The most significant bit (LSB) A ₁ is output. Second stage C2 is inputted to carry C1, and outputs the second bit A _2. The same applies hereinafter. FIG. 6 shows a circuit configuration for one stage.

Fig. 6 shows one dual rail type counter,
Latch circuit 30 and OR gate G _a1 etc. indicated by + and
It is composed of a logic circuit including an AND gate G _{b1 and the} like indicated by a mark. In the case of the first stage C1, the input X _n−1 , ▲ ▼ is the clock CK, ▲ ▼, and the output An of this stage is A ₁ . Output to the next stage Xn, ▲ ▼ is Is. When counting up, u = 1 and d = 0, and when counting down, d = 1 and u = 0.

FIG. 7 shows an example of the latch circuit 30. There are various types of latch circuits, but a circuit composed of three-layer power supplies # 1, # 2, # 3, three OR gates Ga and a timed inverter TI is used here. Output of AND gate G _b2 is 3-phase power supply # 1, #
It is sequentially taken into each OR gate in the phase of 2, # 3, and the output An is generated after a delay of 2π / 3. The output ▲ ▼ is output from the second OR gate through the timed inverter TI. In the Josephson junction having hysteresis, when the bias current exceeds the threshold value, it becomes a voltage state, and this voltage state is maintained until the bias current becomes zero. Each OR gate Ga of the latch circuit 30 operates in this way. When the input is 1 and the # 1 power supply rises, the first OR gate enters a voltage state (latches) when the threshold is exceeded, and the # 1 power supply is turned on. This state is maintained until it becomes 0. The second and third OR gates operate similarly. The timed inverter TI is basically an inverter, which is the output opposite to the output An of the third OR gate ▲
However, since an inverter using Josephson junction is unlikely to generate the first inverted output, a special additional circuit for this is provided. Two types of circuits are known for this, but either of them may be used.

The operation of the circuit of FIG. 6 will be described for the case of up-counting and for the first stage C1. In this case, the output Xn is X _n-1 A.
n Therefore CK ・ A ₁ , ▲ ▼ is Is. Before the first clock, X _n-1 = 0, An = 0, Xn = 0, and ▲ ▼ = 1.

When the first clock enters, X _n-1 = 1, Since An = 0 at the input of this first clock, the output of the AND gate G _b2 Is 1, this is taken into the latch 30, and after the delay, An = 1
become. The OR gate G _{a2 and the} like operate on the # 1 power supply. Further, since An = 0 at the time of inputting the first clock, the first stage output X ₁ is 0 and ▲ ▼ is 1.

When the second clock is input, the output of the AND gate _Gb2 becomes 0 because An = 1 this time, and this is taken into the latch 30, and An = 0 after the delay. At the time of inputting the second clock, An = 1, so the output X ₁ is 1. become.

When the third clock is input, since An = 0, the output of the AND gate G _b2 is 1, which is taken into the latch 30 and becomes An = 1 after the delay. The output X ₁ is 0 and ▲ ▼ is 1.

Similarly, the output An of the first stage is 0,1,0,1, ..., and the carry output Xn to the next stage is 0,0,1,0,1 .... Second stage C ₂
Counts this carry output Xn and sets A ₂ to 0,0,1,1,0,0, ...
And carry output to the next stage. Other stages C3, C4, ...
The operation of is also the same. U = 0, d when counting down
= 1, the borrow output to the next stage is become.

The JJ pulser 12 has one Josephson junction and a resistor connected in series as described in the specification of another application, and two Josephson junctions connected in series are connected in parallel to these, and a sine wave is added to them. It can be generated by a circuit having a series connection point as an output end.

FIG. 8 shows an example of the D / A converter 24. The body is the well-known R-2R
Although it is a ladder circuit, the current supplied to each node is controlled by an OR gate Ga using Josephson devices. A ₁ , A ₂ ,
...... An is each bit of the digital input. When An is 0, the gate is in a non-voltage state, and the bias current I _B all flows through the gate and is dropped to the ground. The gate If An is 1 becomes voltage state, the bias current I _B flows also to node Nn. The same applies to the gates of other bits. Each node has a form of being connected to the ground by three 2R, it flows I _B / 3 is each When the I _B supplied to each node 2R. Therefore, when An = 1, the current flowing to the output line l ₅ is Is. As for A _n-1 , 1/2 of I _B / 3 flowing to the _{N n} side flows to l ₅ , which follows, so the current I flowing to the output line l ₅ is become. This is nothing but an n-bit binary number D / A conversion output where A ₁ is LSB and An is MSB. These resistances can be replaced with superconducting inductances L and 2L as shown in FIG. The current flowing through the output line l ₅ is also expressed by the equation (5). Further, as shown in FIG. 10, a mutual inductance M may be used. In this case, the current I flowing through the output line l ₅
Is Is. PID control can be performed on the analog quantity after D / A conversion, but as shown in Fig. 11, the counter CT
The output of R can be performed by a combination of the registers 32, 34 and 36, the subtractor 38, the adder 40, and the weighting circuit 42.
That is, the proportional (P) component is the output of the register 32 as it is, the differential (D) component is the difference from the previous value of the register 34 by the subtracter 38, and the integral (I) component is the previous value of the register 36. If the sum of is added to the current value by the adder 40 and is input to the weighting adder 42, the output of the adder 42 becomes the PID control output. These adder and subtractor can be realized by a Josephson logic circuit and can be integrated into one chip.

The frequency divider 14 for generating the triangular wave of the frequency f _C may use the up-down counter CTR with u = 1 and d = 0. Of course, since u = 1 and d = 0 always, FIG. 6 can be simplified as shown in FIG. Figure 12 shows counter stages C1 and C
2, ... are cascaded in N stages and the input cycle T from the last stage C _N
The state of obtaining the output A _N with a period of 2 ^N is shown. Figure 13 shows the i-th stage of the counter, As shown in FIG. 14, the low pass filter LPF can be composed of a circuit including a superconducting transformer TR, a resistor R and an inductance L. In this circuit, if the time constant of RL is set sufficiently large, a triangular wave current will flow in the output line l ₆ when a rectangular wave enters the input terminal IN.

Although each circuit is realized by a superconducting circuit in FIGS. 4 to 14, other circuits having the same function may be used as long as they can be integrated into one chip with SQUID. Alternatively, the feedback circuit may be removed in FIG. 4 to obtain the measured current I _X from the pulse number difference. Triangular wave of frequency f _C or saw tooth I _C (t) is I _B
Instead of using the same oscillator output as (t), it may be generated separately (asynchronously). Counter CTR in Fig. 4
The output of may be further stored and processed by a superconducting circuit or the like, and may be D / A converted and output.

〔The invention's effect〕

As described above, in the present invention, since the output of the SQUID is extracted as the number of pulses, it is processed by a superconducting circuit composed of a Josephson element or the like, which is good at digital processing,
Further, a feedback circuit or the like can be configured and can be integrated on the same chip by the same process, so that a small and highly sensitive SQUID can be provided.

[Brief description of drawings]

FIG. 1 is a principle diagram of the present invention, FIGS. 2 and 3 are operation explanatory diagrams of FIG. 1, FIG. 4 is a block diagram showing an embodiment of the present invention, and FIG. 5 is a block diagram of an up-down counter. 6 is a circuit diagram for one stage of the counter, FIG. 7 is a circuit diagram and a waveform diagram of the latch, FIGS. 8 to 10 are circuit diagrams of the D / A converter, and FIG. 11 is a diagram of the PID control circuit. Block diagram, Fig. 12 is a block diagram of the frequency divider, Fig. 13 is a circuit diagram of one stage of the frequency divider, Fig. 14 is a circuit diagram of the LPF, Fig. 15 is an explanatory diagram of a conventional SQUID, Figure 16 is a circuit diagram of a conventional magnetometer. In FIG. 1, J ₁ and J ₂ are Josephson junctions, I _B (t) is a bias current, I _X is a measured current, I _C (t) is a control current, Out is an output terminal, and CTR is a counter.

Claims (3)

[Claims] 1. A superconducting quantum interference device comprising a superconducting loop including two or more Josephson junctions (J ₁ , J ₂ ), wherein a bias current (I _B (t) consisting of a repetitive pulse current is provided in the superconducting loop. ) Is supplied and the superconducting loop is excited by a control current (I _C (t)) and a signal current (I _X ) having a frequency lower than the repetition frequency of the bias current, and the bias current causes the Josephson junction to flow. A superconducting quantum interference device characterized by counting the number of pulses (m) of a pulse voltage generated by exceeding the threshold of. 2. Means (12) for supplying the bias current, and means (14, LP) for supplying the control current.
F) and means (CTR) for counting the number of pulses of said pulse voltage, part or all of these means comprising a superconducting circuit. The superconducting quantum interference device according to item 1. 3. The superconducting loop according to claim 1, wherein the superconducting loop is excited by a feedback current generated based on a result of counting the number of pulses of the pulse voltage. Conduction quantum interference device.