JPH09121351A - Image signal code amount control circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the degradation of picture quality and to improve encoding efficiency by enabling quantization corresponding to a picture pattern. SOLUTION: While using a synchronizing signal 104 delayed by a delay circuit 3, a small area dividing circuit 5 of a code amount control circuit 4 discriminates the position of an image on a screen corresponding to a DCT coefficient 103 and outputs the discriminated result as an area discrimination signal 105. According to the area discrimination signal 105, a small area characteristic analytic circuit 6 analyzes the characteristics of the picture pattern from the DCT coefficient 103 for each area and outputs the characteristic analyzed result 106. According to the characteristic analyzed result 106, a small area code amount setting circuit 7 distributes a target picture inside code amount 107 to respective small areas, allocates them and outputs an allocated code amount 108. Based on an area discrimination signal 109 delayed by a delay circuit 8, a quantizing parameter calculation circuit 9 calculates a quantizing parameter for each small area according to the allocated code amount 108.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image signal code amount control circuit, and more particularly, to a code encoding device for compressing an image in a field or a frame, in which the code amount of each screen is suppressed to a certain value or less and the code is efficiently assigned. The present invention relates to a code amount control method capable of controlling.

[0002]

2. Description of the Related Art A compression coding of an image signal is often applied to transmission and recording, but in particular, VTR (Video Ta) is used.
When used in a recording device such as a pe recorder) or a video disk recorder, it is necessary to suppress the code amount generated in each screen to a certain value or less in order to realize the editing function in each screen. Therefore, some compression encoding devices use a code amount control means.

FIG. 8 is a diagram showing the structure of a conventional compression encoding device. A conventional image signal code amount control method will be described below with reference to FIG.

Input digital video data 200
Is DCT (Discrete Cosine Tran)
sform) conversion circuit 61 performs DCT conversion processing,
The DCT transform coefficient 201 as the processing result is output from the DCT transform circuit 61 to the quantization parameter calculation circuit 62 and the quantization circuit 63.

The quantization parameter calculation circuit 62 calculates a quantization parameter 203 for each screen from the DCT transform coefficient 201 and the in-screen target code amount 202, and the quantization parameter 203 is sent to the quantization circuit 63 and the encoding circuit 64. Output.

The quantizing circuit 63 operates on the DC according to the quantizing parameter 203 from the quantizing parameter calculating circuit 62.
The DCT transform coefficient 201 from the T transform circuit 61 is quantized, and the quantized data 204 is output to the encoding circuit 64.

The encoding circuit 64 performs an encoding process such as Huffman encoding on the quantized data 204 from the quantization circuit 63, and outputs the result of the encoding process and the quantization parameter 203 necessary for decoding. It is integrated and output as compressed video data 205.

The quantization parameter calculation circuit 62 described above is
As shown in FIG. 9, a quantization circuit 65 including a division circuit 66 and a multiplication circuit 67, and a generated code amount in-screen accumulation circuit 68.
And a parameter adjusting circuit 69.

In the quantization parameter calculation circuit 62,
The DCT transform coefficient 201 is quantized with a predetermined parameter. This quantization processing is performed by the quantization circuit 65.
Done in

In the multiplication circuit 67 of the quantization circuit 65, a quantization matrix 3 which defines a predetermined initial quantization parameter 301 and a quantization coefficient of each coefficient in the DCT block.
02, and the multiplication result 303 is divided by the division circuit 6
6 is output.

The division circuit 66 divides the DCT transform coefficient 201 by the multiplication result 303, integerizes the division result, and outputs the quantized data 304 to the generated code amount in-screen accumulation circuit 68.

The generated code amount in-screen accumulation circuit 68 obtains the code amount when the quantized data 304 from the division circuit 66 is encoded, calculates the sum within the screen from the code amount, and generates the generated code amount 305. Is output to the parameter adjustment circuit 69.

The parameter adjustment circuit 69 compares the generated code amount 305 from the generated code amount in-screen accumulation circuit 68 with the in-screen target code amount 202. If the generated code amount 305 is larger than the in-screen target code amount 202, the parameter adjustment circuit 69
Since the quantization using the initial quantization parameter 301 will overflow, the value of the parameter is made larger than the initial quantization parameter 301, and control is performed so that coarse quantization is performed.

If the generated code amount 305 is smaller than the in-screen target code amount 202, the parameter adjusting circuit 69 controls the parameter value to be smaller than the initial quantization parameter 301 so that fine quantization is performed.

As described above, by setting the quantization parameter for each screen and performing quantization, the generated code amount for each screen is controlled to be equal to or less than the target code amount. The code amount control method described above is described in detail in Japanese Patent Application No. 5-138064, entitled “Image Coding Method and Apparatus”.

[0016]

In the code amount control method in the above-described conventional compression coding device, the target code amount per screen is predetermined, and the sum of the code amounts of each screen is equal to or less than that value. The quantization parameter is set as follows.

However, in the conventional code amount control method, there is one quantization parameter in one screen.
Therefore, the characteristics of the screen contents, that is, the fine pattern, the flat pattern, and the outline portion are not taken into consideration, and the same quantization parameter is applied to all the patterns.

In compression coding of an image signal, if a fine pattern portion is finely quantized in consideration of visual characteristics, and a flat pattern portion is coarsely quantized, deterioration of image quality is not conspicuous and the code is encoded. It is said that the conversion efficiency is good.

On the other hand, in the above code amount control method, since the quantization characteristic cannot be changed for a fine pattern portion or a flat pattern portion according to the pattern, efficient compression encoding cannot be performed. .

Therefore, an object of the present invention is to solve the above-mentioned problems, to carry out quantization according to a picture, to suppress deterioration of image quality and to improve coding efficiency, and to control coding amount of image signal. To provide a circuit.

[0021]

An image signal code amount control circuit according to the present invention is a compression code for outputting compressed data by quantizing and coding an orthogonal transform coefficient obtained by orthogonally transforming an image signal. Which is an image signal code amount control circuit of a digitizing device, wherein characteristic analysis means calculates the characteristic of each of a plurality of small areas into which one screen is divided in advance by analyzing the orthogonal transformation coefficient for each small area; Code amount setting means for allocating a code amount for each small region based on the characteristics of each of the plurality of small regions calculated by the means, and for each small region based on the code amount assigned by the code amount setting means And a quantizing means for quantizing the orthogonal transform coefficient using the quantizing parameter for each small area calculated by the calculating means.

In another image signal code amount control circuit according to the present invention, in addition to the above configuration, to which of the plurality of small areas the orthogonal transform coefficient belongs based on a synchronization signal added to the image signal. By specifying, the dividing unit divides the one screen into a plurality of small areas.

[0023]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First, the operation of the present invention will be described below.

Orthogonal transformation is performed on an image signal, the orthogonal transformation coefficient is quantized and coded to output compressed data, and the amount of compressed data changes the quantization characteristic when quantized. In the compression encoding device controlled by, one screen is divided into a plurality of small areas, and the characteristic of the original image signal is analyzed from the orthogonal transform coefficient for each small area.

Using these characteristics, a code amount is assigned to each small region so that the sum of the code amounts of the small regions is equal to or less than the target code amount for one screen, and each small region is calculated based on the code amount. Quantization processing is performed using the quantization parameter of the area.

As a result, even if the quantization is performed according to the picture of each small area obtained by dividing one screen, the code amount for each screen can be suppressed below the target. Therefore, the quantization according to the picture is performed.
It is possible to reduce image quality deterioration and improve coding efficiency.

Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the configuration of one embodiment of the present invention. In the figure, a compression encoding apparatus according to an embodiment of the present invention includes a synchronization detection / separation circuit 1
(Discece Cine Transform)
m) It is composed of a conversion circuit 2, delay circuits 3 and 10, a code amount control circuit 4, a quantization circuit 11, and an encoding circuit 12.

The code amount control circuit 4 includes a small area division circuit 5 and
A small area characteristic analysis circuit 6, a small area code amount setting circuit 7,
It is composed of a delay circuit 8 and a quantization parameter calculation circuit 9.

Input digital video data 100
Is the synchronization detection / separation circuit 1 and the image signal 101 and the synchronization signal 1
02 and the image signal 101 is separated into the DCT conversion circuit 2
The sync signal 102 is output to the small area division circuit 5 of the code amount control circuit 4 via the delay circuit 3.

The image signal 101 is converted to DC by the DCT conversion circuit 2.
The T-transform process is performed, and the resulting DCT transform coefficient 103 is output from the DCT transform circuit 2 to the small area characteristic analysis circuit 6 and the quantization parameter calculation circuit 9 of the code amount control circuit 4 and the delay circuit 10 Quantization circuit 1
It is output to 1.

In the code amount control circuit 4 described above, the small area division circuit 5 uses the synchronization signal 104 delayed by the delay circuit 3 to input the DCT transform coefficient 1 to the code amount control circuit 4.
It is determined which position on the screen 03 corresponds to the image, and the determination result is output to the small area characteristic analysis circuit 6 and the delay circuit 8 as the area identification signal 105.

The small area characteristic analyzing circuit 6 is a small area dividing circuit 5.
The characteristic analysis of the pattern is performed from the DCT conversion coefficient 103 for each area according to the area identification signal 105 input from the circuit, and the characteristic analysis result 106 is output to the small area code amount setting circuit 7.

The small area code amount setting circuit 7 distributes and allocates the in-screen target code amount 107 to each small area according to the characteristic analysis result 106 input from the small area characteristic analysis circuit 6, and assigns the allocated code amount 108 to the quantum. Parameter calculation circuit 9
Output to

The quantization parameter calculation circuit 9 is the delay circuit 8
Based on the area identification signal 109 delayed by, the quantization parameter for each small area is calculated according to the assigned code quantity 108 input from the small area code quantity setting circuit 7, and the quantization parameter 110 is converted to the quantization circuit 11 And output to the encoding circuit 12. Here, the quantization parameter for each small area is calculated so that the sum of them reaches the in-screen target code amount 107.

The quantizing circuit 11 quantizes the DCT transform coefficient 111 delayed by the delay circuit 10 according to the quantizing parameter 110 from the quantizing parameter calculating circuit 9,
The quantized data 112 is output to the encoding circuit 12.

The coding circuit 12 performs coding processing such as Huffman coding on the quantized data 112 from the quantization circuit 11, and the result of the coding processing and the quantization parameter 110 necessary for decoding are obtained. It is integrated and output as compressed video data 113.

FIG. 2 is a diagram showing an example of area division of a screen according to an embodiment of the present invention. In the figure, in this area division example, the screen is mechanically divided into four small areas having the same area. Here, the upper left of the screen is Z1, the upper right of the screen is Z2, the lower left of the screen is Z3, and the lower right of the screen is Z4.

FIG. 3 is a block diagram showing the structure of the small area division circuit 5 of FIG. In the figure, the small area division circuit 5 is composed of a position information acquisition circuit 21, comparison circuits 22 and 23, and an area determination circuit 24.

The position information acquisition circuit 21 uses the sync signal 104 to input the DCT transform coefficient 1 to the code amount control circuit 4.
Information on which position 03 is on the screen is acquired, and the position information 121 is output to the comparison circuits 22 and 23.

The comparison circuit 22 compares the position information 121 from the position information acquisition circuit 21 with the area information 112 indicating the horizontal size of the screen × 1/2 and determines whether the position is larger than 1/2 of the horizontal size of the screen. It is determined whether or not it is smaller, and the determination result is set as the horizontal position determination result 124 in the area determination circuit 24.
Output to

The comparison circuit 23 compares the position information 121 from the position information acquisition circuit 21 with the area information 113 indicating the vertical size of the screen × 1/2 and determines whether the position is larger than 1/2 of the vertical size of the screen. It is determined whether or not it is smaller, and the determination result is used as the vertical position determination result 125, and the area determination circuit 24
Output to

The area determination circuit 24 uses the horizontal position determination result 124 from the comparison circuit 22 and the vertical position determination result 125 from the comparison circuit 23 to determine the DCT transform coefficient 103 input to the code amount control circuit 4 on the screen. When it is determined that the position is smaller than 1/2 of the horizontal size and smaller than 1/2 of the vertical size, the data is classified into the small area Z1.

When the area determination circuit 24 determines that the DCT transform coefficient 103 input to the code amount control circuit 4 is at a position larger than 1/2 of the horizontal size of the screen and smaller than 1/2 of the vertical size, The data is classified into the small area Z2.

Further, when the area decision circuit 24 decides that the DCT transform coefficient 103 inputted to the code amount control circuit 4 is at a position smaller than 1/2 of the horizontal size of the screen and larger than 1/2 of the vertical size, The data is a small area Z3
Classify into.

Furthermore, when the area determination circuit 24 determines that the DCT transform coefficient 103 input to the code amount control circuit 4 is at a position larger than 1/2 of the horizontal size of the screen and larger than 1/2 of the vertical size. , The data is classified into the small area Z4.

The area determination circuit 24 outputs the above determination result to the small area characteristic analysis circuit 6 as an area identification signal 105.

FIG. 4 is a diagram showing an example of each component of the DCT transform coefficient according to the embodiment of the present invention. In the figure, the upper left sample F (0,0) represents a DC component, and as it goes to the right in the horizontal direction, that is, the sample F (7,0) is higher in the horizontal range than the sample F (1,0). It represents the spatial frequency component.

Further, the lower the sample is in the vertical direction, that is, the sample F than the samples F (0,1) and F (0,2).
(0, 7) represents the vertical spatial frequency component in the high frequency range. Therefore, the sample F (7,7) represents a high frequency in both the horizontal spatial frequency component and the vertical spatial frequency component.

That is, when the image of a fine pattern is DCT-converted, it has a large value up to high frequency components. On the contrary, when the image of a flat pattern is DCT-transformed, only the low frequency component or the direct current component has a large value, and the high frequency component becomes almost zero.

An image having many horizontal components such as vertical lines concentrates on horizontal spatial frequency components, and an image having many vertical components such as horizontal lines concentrates on vertical spatial frequency components. As mentioned above,
It is possible to infer characteristics such as whether the original image is a fine image or a flat image based on the distribution of the DCT transform coefficients within the block.

FIG. 5 is a block diagram showing the configuration of the small area characteristic analysis circuit 6 of FIG. In the figure, a small area characteristic analysis circuit 6 includes an AC component absolute value calculation circuit 31 and a distribution circuit 32.
, Z1 cumulative calculation circuit 33, and Z2 cumulative calculation circuit 34
And a Z3 cumulative calculation circuit 35 and a Z4 cumulative calculation circuit 36, and the AC component (AC
Characteristic analysis is performed using only the size of (component).

The AC component absolute value calculation circuit 31 performs processing for forcibly replacing the DC component of the DCT transform coefficient 103 with zero and replacing the other component, that is, the AC component with its absolute value. That is, the AC component absolute value calculation circuit 3
1 is the AC component of the DCT transform coefficient 103, the positive number is the same value as it is, the negative number is changed to a positive number by changing the sign, and A
The C component absolute value 131 is output to the distribution circuit 32.

The distribution circuit 32 is the AC component absolute value calculation circuit 3
The AC component absolute value 131 from 1 is calculated by the Z1 cumulative calculation circuit 33, the Z2 cumulative calculation circuit 34, the Z3 cumulative calculation circuit 35, and the Z4 cumulative calculation circuit 36 for each small area according to the area identification signal 105 from the small area division circuit 5. Distribute to each.

That is, the distribution circuit 32 uses the area identification signal 1
If 05 indicates the small area Z1, the AC component absolute value 131 input from the AC component absolute value calculation circuit 31 is the small area Z1.
Since it is included in 1, the small area Z1AC component absolute value 132 is output to the Z1 cumulative calculation circuit 33.

Further, the distribution circuit 32 uses the area identification signal 105.
Is a small area Z2, the AC component absolute value calculation circuit 3
Since the AC component absolute value 131 input from 1 is included in the small area Z2, it is output to the Z2 cumulative calculation circuit 34 as the small area Z2 AC component absolute value 133.

Further, the distribution circuit 32 uses the area identification signal 10
If 5 indicates the small area Z3, the AC component absolute value 131 input from the AC component absolute value calculation circuit 31 is the small area Z3.
Is output to the Z3 cumulative calculation circuit 35 as the small region Z3AC component absolute value 134.

Furthermore, if the area identification signal 105 indicates the small area Z4, the distribution circuit 32 includes the AC component absolute value 131 input from the AC component absolute value calculation circuit 31 in the small area Z4. Z4AC component absolute value 135
Is output to the Z4 cumulative calculation circuit 36.

The Z1 cumulative calculation circuit 33 calculates the sum of the AC component absolute values in the small area Z1 based on the small area Z1 AC component absolute value 132 distributed by the distribution circuit 32, and the calculation result is the Z1 cumulative value 106a. Small area code amount setting circuit 7
Output to

The Z2 cumulative calculation circuit 34 calculates the total sum of the AC component absolute values in the small area Z2 based on the small area Z2 AC component absolute value 133 distributed by the distribution circuit 32, and the calculation result is the Z2 cumulative value 106b. Small area code amount setting circuit 7
Output to

The Z3 cumulative calculation circuit 35 calculates the total sum of the AC component absolute values in the small area Z3 based on the small area Z3 AC component absolute value 134 distributed by the distribution circuit 32, and the calculation result is the Z3 cumulative value 106c. Small area code amount setting circuit 7
Output to

The Z4 cumulative calculation circuit 36 calculates the total sum of the absolute values of the AC components in the small area Z4 based on the small area Z4 AC component absolute value 135 distributed by the distribution circuit 32, and the calculated result is the Z4 cumulative value 106d. Small area code amount setting circuit 7
Output to

As described above, the cumulative value of these is the DCT.
The magnitude of the AC component in the area of the conversion coefficient is shown. That is, when there are many fine patterns in the area, the cumulative value becomes large, and when there are many flat patterns, the cumulative value becomes small.

For example, when a picture as shown in FIG. 2 is input, the cumulative value of the small area Z3 having many fine pictures is the largest, and the cumulative value of the small area Z4 having few fine pictures is the smallest. Become. In addition, Z1 cumulative value 106a and Z1
2 cumulative value 106b, Z3 cumulative value 106c, Z4 cumulative value 1
06d is output in parallel to the small area code amount setting circuit 7 as the characteristic analysis result 106.

FIG. 6 is a block diagram showing the configuration of the small area code amount setting circuit 7 of FIG. In the figure, the small area code amount setting circuit 7 includes an adding circuit 41, dividing circuits 42 to 45,
It is composed of multiplication circuits 46 to 49.

The small area code amount setting circuit 7 receives the characteristic analysis result 106 input from the small area characteristic analyzing circuit 6, that is, Z1.
Cumulative value 106a, Z2 cumulative value 106b, and Z3 cumulative value 10
6c and the Z4 cumulative value 106d, the in-screen target code amount 107 is distributed and assigned to each small area.

As described above, the fact that the cumulative value of the AC component is large means that the pattern is fine, and it is necessary to allocate a large amount of codes to suppress the image quality deterioration. On the contrary, since the cumulative value of the AC component is small, the pattern is not fine and is flat. Therefore, even if the allocation of the code amount is reduced, the deterioration of the image quality is small.

Therefore, the small area code amount setting circuit 7 uses the accumulated value of each small area to allocate a large amount of code to an area having a large accumulated value and a small amount of code to an area having a small accumulated value. , The sum of the code amounts of the small areas is made equal to the target code amount of the entire screen.

That is, in the small area code amount setting circuit 7, the addition circuit 41 determines that the Z1 cumulative value 106a and the Z2 cumulative value 1
The sum of 06b, the Z3 cumulative value 106c, and the Z4 cumulative value 106d is calculated, the cumulative value of the entire screen is calculated, and the calculated cumulative value 141 of the entire screen is output to each of the division circuits 42 to 45.

The division circuit 42 divides the Z1 cumulative value 106a by the entire screen cumulative value 141 to obtain a small area Z for the entire screen.
The cumulative ratio of 1 is calculated, and the calculation result is the small area Z.
The ratio of 1 142 is output to the multiplication circuit 46.

The division circuit 43 divides the Z2 cumulative value 106b by the entire screen cumulative value 141 to obtain a small area Z for the entire screen.
The cumulative ratio of 2 is calculated, and the calculation result is the small area Z
The ratio 143 of 2 is output to the multiplication circuit 47.

The division circuit 44 divides the Z3 cumulative value 106c by the entire screen cumulative value 141 to obtain a small area Z for the entire screen.
The cumulative ratio of 3 is calculated, and the calculation result is the small area Z.
The ratio 144 of 3 is output to the multiplication circuit 48.

The division circuit 45 divides the Z4 cumulative value 106d by the entire screen cumulative value 141 to obtain a small area Z for the entire screen.
4 is calculated, and the calculation result is the small area Z.
The ratio 145 of 4 is output to the multiplication circuit 49.

In this case, the larger the cumulative value, the larger the ratio, and the smaller the cumulative value, the smaller the ratio. For example, the cumulative value of each of the small areas Z1 to Z4 in FIG.
If the values are 0, 2000, 5000, and 1000, the ratio of each of the small regions Z1 to Z4 is 0.2, 0.
The values are 2, 0.5 and 0.1.

The multiplication circuit 46 multiplies the ratio 142 of the small area Z1 from the division circuit 42 by the in-screen target code amount 107, and calculates the quantization parameter as the small area Z1 assigned code amount 108a for the small area Z1. Output to the circuit 9.

The multiplication circuit 47 multiplies the ratio 143 of the small area Z2 from the division circuit 43 by the in-screen target code amount 107 and calculates the quantization parameter as the small area Z2 assigned code amount 108b for the small area Z2. Output to the circuit 9.

The multiplication circuit 48 multiplies the ratio 144 of the small area Z3 from the division circuit 44 by the in-screen target code amount 107 and calculates the quantization parameter as the small area Z3 assigned code amount 108c for the small area Z3. Output to the circuit 9.

The multiplication circuit 49 multiplies the ratio 145 of the small area Z4 from the division circuit 45 by the in-screen target code amount 107 and calculates the quantization parameter as the small area Z4 assigned code amount 108d for the small area Z4. Output to the circuit 9.

For example, if the intra-screen target code amount 107 is 1 megabit, the multiplication circuit 46 determines that the small area Z1
The allocation code amount 108a is 200 kilobits, the multiplication circuit 47 outputs a small area Z2 allocation code amount 108b of 200 kilobits, the multiplication circuit 48 outputs a small area Z3 allocation code amount 108c of 500 kilobits, and the multiplication circuit 49 outputs a small area. 1 as the Z4 assigned code amount 108d
00 kilobits are output respectively.

The small area Z1 assigned code amount 108a, the small area Z2 assigned code amount 108b, the small area Z3 assigned code amount 108c, and the small area Z4 assigned code amount 108d are assigned to the quantization parameter calculation circuit 9 as the assigned code amount 108. It is output in parallel.

FIG. 7 shows the quantization parameter calculation circuit 9 of FIG.
FIG. 3 is a block diagram showing the configuration of FIG. In the figure, a quantization parameter calculation circuit 9 includes a Z1 region quantization parameter calculation circuit 51, a Z2 region quantization parameter calculation circuit 52,
It is composed of a Z3 region quantization parameter calculation circuit 53, a Z4 region quantization parameter calculation circuit 54, and a selection circuit 55.

The Z1 area quantization parameter calculation circuit 51 calculates and selects the quantization parameter 151 of the small area Z1 based on the DCT transform coefficient 103 and the small area Z1 assigned code quantity 108a from the small area code quantity setting circuit 7. Output to the circuit 55.

The Z2 region quantization parameter calculation circuit 52 calculates and selects the quantization parameter 152 of the small region Z2 based on the DCT transform coefficient 103 and the small region Z2 assigned code amount 108b from the small region code amount setting circuit 7. Output to the circuit 55.

The Z3 area quantization parameter calculation circuit 53 calculates and selects the quantization parameter 153 of the small area Z3 based on the DCT transform coefficient 103 and the small area Z3 assigned code quantity 108c from the small area code quantity setting circuit 7. Output to the circuit 55.

The Z4 region quantization parameter calculation circuit 54 calculates and selects the quantization parameter 154 of the small region Z4 based on the DCT transform coefficient 103 and the small region Z4 assigned code amount 108d from the small region code amount setting circuit 7. Output to the circuit 55.

The Z1 region quantization parameter calculation circuit 51, the Z2 region quantization parameter calculation circuit 52, the Z3 region quantization parameter calculation circuit 53, and the Z4 region quantization parameter calculation circuit 54 of the quantization parameter calculation circuit 9 described above.
As in the conventional example shown in FIG. 9, each is composed of a quantizing circuit including a division circuit and a multiplying circuit, a generated code amount in-screen accumulating circuit, and a parameter adjusting circuit. Since the conversion parameter is calculated, its description is omitted here.

The selection circuit 55 selects the quantization parameter of the corresponding small area according to the area identification signal 109 delayed by the delay circuit 8 and outputs it as the quantization parameter 110 to the quantization circuit 11 and the encoding circuit 12.

That is, the selection circuit 55 outputs the area identification signal 1
If 09 indicates the small area Z1, the quantization parameter 151 of the small area Z1 input from the Z1 area quantization parameter calculation circuit 51 is output to the quantization circuit 11 and the encoding circuit 12 as the quantization parameter 110.

Further, the selection circuit 55 uses the area identification signal 109.
Indicates a small area Z2, the quantization parameter 152 of the small area Z2 input from the Z2 area quantization parameter calculation circuit 52 is output to the quantization circuit 11 and the encoding circuit 12 as the quantization parameter 110.

Further, the selection circuit 55 uses the area identification signal 10
If 9 indicates the small area Z3, the quantization parameter 153 of the small area Z3 input from the Z3 area quantization parameter calculation circuit 53 is output to the quantization circuit 11 and the encoding circuit 12 as the quantization parameter 110.

Furthermore, if the area identification signal 109 indicates the small area Z4, the selection circuit 55 uses the quantization parameter 154 of the small area Z4 input from the Z4 area quantization parameter calculation circuit 54 as the quantization parameter 110. Output to the quantization circuit 11 and the encoding circuit 12.

Therefore, the quantizing circuit 11 inputs the quantizing parameter 151 of the small area Z1 and the quantizing parameter 1 of the small area Z2, which are sequentially input from the quantizing parameter calculating circuit 9.
52 and the quantization parameter 153 of the small area Z3 and the small area Z
Delay circuit 1 according to the quantization parameter 154 of 4
DCT transform coefficient 1 of each of the small areas Z1 to Z4 delayed by 0
11 is quantized, and the quantized data 1 of each of the small areas Z1 to Z4
12 is output to the encoding circuit 12.

The encoding circuit 12 performs an encoding process on the quantized data 112 of each of the small regions Z1 to Z4 from the quantizing circuit 11, and the result of the encoding process and each small region Z1 required at the time of decoding. -Z4 quantization parameter 110 (quantization parameter 151 of small area Z1, quantization parameter 152 of small area Z2, quantization parameter 15 of small area Z3)
3 and the quantization parameter 154) of the small area Z4 are integrated and output as the compressed video data 113.

The delay circuit 3 delays the synchronization signal 102 from the synchronization detection / separation circuit 1 by the processing time in the DCT conversion circuit 2, and the delay circuit 8 delays the area identification signal 105 from the small area division circuit 5 into a small amount. The delay time is delayed by the processing time in the area characteristic analysis circuit 6 and the small area code amount setting circuit 7, and the delay circuit 10
The DCT transform coefficient 103 from the transform circuit 2 is delayed by the processing time in the code amount control circuit 4.

Although not shown, the DCT transform coefficient 103 input from the DCT transform circuit 2 to the small area characteristic analysis circuit 6 is also delayed by the processing time in the small area dividing circuit 5,
The DCT transform coefficient 103 input from the DCT transform circuit 2 to the quantization parameter calculation circuit 9 is also delayed by the processing time in the small area division circuit 5, the small area characteristic analysis circuit 6 and the small area code amount setting circuit 7.

In the above-described embodiment, the orthogonal transformation method D
Although the case of using CT has been described, other orthogonal transform methods such as Fourier transform and Hadamard transform may be used. Also, although the block size is explained as 8 × 8, it may be another size, that is, a larger block or a smaller block.

Furthermore, a TV (TV) is used as a moving image signal.
When a signal is used, either a field screen or a frame screen can be applied as a screen unit. Furthermore, in the small area division, four small areas Z having the same area are used.
Although the process of dividing into 1 to Z4 has been described, the present invention can be applied to the case where the areas are different, the area is divided into four or more fine regions, or a rectangle or another shape instead of a square. In that case, it is more effective if the boundary of the division is performed at the boundary of the block on which the DCT transform is performed.

The case where the cumulative value of the absolute value of the AC component is used as the characteristic analysis means of the small area has been described.
The present invention can also be applied to the case where the sum of sums, the average of absolute values, or the bias distribution of horizontal spatial frequency components and vertical spatial frequency components is used.

In the code amount setting of the small area, the method of calculating the allocation code amount by calculating the ratio of the characteristics of the small region to the whole has been described. For example, the allocation code amount is uniquely determined from the characteristic analysis result by table lookup or the like. It is also possible to apply a determination method or the like.

As the quantization parameter, the case of using the one that defines the quantization step width like the divisor of the division operation has been described, but a plurality of quantization characteristics having different step sizes are prepared in advance. , A parameter used to control the selection of the quantization characteristic is also applicable.

As described above, in the compression coding apparatus which quantizes and codes the orthogonal transform coefficient obtained by orthogonally transforming the image signal and outputs the compressed data, one screen is divided into a plurality of divided areas. The characteristics of each small area are calculated by the small area characteristic analysis circuit 6 by analyzing the orthogonal transformation coefficient for each small area,
A small area code amount setting circuit 7 allocates a code amount for each small area based on the calculated characteristics of each small area, and a quantization parameter calculation circuit 9 allocates each small area for each small area based on the allocated code amount. The quantization parameter of each of the small areas is calculated, and the quantization circuit 11 uses the quantization parameter of each small area to quantize the orthogonal transform coefficient. Parameters can be set. Therefore, efficient code allocation can be performed, and deterioration in image quality due to compression coding can be reduced.

Further, since the sum of the code amounts of the respective small areas becomes equal to the predetermined in-screen target code amount 107, the in-screen code amount can be suppressed to a certain value or less. Therefore,
Even when used in a recording device such as a VTR or a video disc recorder, it is possible to realize a practically useful compression encoding device with little deterioration in image quality and without impairing editing functions such as frame editing.

[0102]

As described above, according to the present invention, in the compression coding apparatus for outputting the compressed data by performing the quantization and the coding on the orthogonal transformation coefficient obtained by orthogonally transforming the image signal, The characteristics of each of the plurality of small areas into which one screen is divided in advance are calculated by analyzing the orthogonal transform coefficient of each of the small areas, and the code amount of each of the small areas is assigned based on the characteristics of each of the plurality of small areas. By calculating the quantization parameter for each small area and performing the quantization on the orthogonal transform coefficient, it is possible to perform the quantization depending on the pattern, reduce the image quality deterioration and improve the coding efficiency. The effect is that you can do it.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a diagram showing an example of area division of a screen according to an embodiment of the present invention.

3 is a block diagram showing a configuration of a small area division circuit of FIG.

FIG. 4 is a diagram showing an example of each component of a DCT transform coefficient according to an embodiment of the present invention.

5 is a block diagram showing a configuration of a small area characteristic analysis circuit of FIG. 1. FIG.

6 is a block diagram showing a configuration of a small area code amount setting circuit of FIG. 1. FIG.

FIG. 7 is a block diagram showing a configuration of a quantization parameter calculation circuit of FIG.

FIG. 8 is a block diagram showing a configuration of a conventional compression encoding device.

9 is a block diagram showing a configuration of a quantization parameter calculation circuit of FIG.

[Explanation of symbols]

 1 synchronization detection / separation circuit 2 DCT conversion circuit 3, 8, 10 delay circuit 4 code amount control circuit 5 small area division circuit 6 small area characteristic analysis circuit 7 small area code amount setting circuit 9 quantization parameter calculation circuit 11 quantization circuit 12 Encoding circuit

Claims (3)

[Claims] 1. An image signal code amount control circuit of a compression encoding device for quantizing and encoding an orthogonal transform coefficient obtained by orthogonally transforming an image signal and outputting compressed data, comprising one screen. Based on the characteristics of each of the plurality of small areas calculated by the characteristic analyzing means, and the characteristics of each of the plurality of small areas previously divided by the analysis of the orthogonal transformation coefficient for each of the small areas. A code amount setting means for allocating a code amount for each small area, a calculating means for calculating a quantization parameter for each small area based on the code amount allocated by the code amount setting means, and the calculating means. And a quantizing means for quantizing the orthogonal transform coefficient using the calculated quantizing parameter for each small area. 2. A division for dividing one screen into a plurality of small areas by designating which of the plurality of small areas the orthogonal transform coefficient belongs to based on a synchronization signal added to the image signal. 4. A means including means.
The image signal code amount control circuit described. 3. The characteristic analyzing means is configured to calculate the density of a pattern in the image signal as a characteristic of each of the plurality of small areas by analyzing the orthogonal transformation coefficient. The image signal code amount control circuit according to claim 2.