JPH09121140A - Tap coefficient memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To connect a sign spreading part to the output of a highest-order block by block-dividing a tap coefficient memory by means of an n-bit unit at every tap and removing the high-order bit memory which is occupied only by means of writing impulse response sign bits in accordance with the length of sign bit by means of a block unit. SOLUTION: The tap coefficient memory 20 is block-divided by the n-bit unit at every tap. Then, the high-order bit memory which is occupied only by the writing impulse response sign bits is removed in accordance with the length of the sign bit by the block unit. Then, the sign spreading part is added and connected to the output of the highest-order block of the memory in respective taps. In writing data in the tap coefficient memory 20, the signal bit corresponding to the removed memory is neglected. At the time of reading data from the tap coefficient memory, sign spreading is executed by the sign spreading part 30 in data which is written in the highest-order memory in the tap, so that the required tap number is obtained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal processing, and more particularly to a memory for accumulating impulse response signal data used in an echo canceller or a decision feedback equalizer.

A subscriber line to which a telephone is connected by a long-distance telephone line transmits and receives a signal by a two-wire line, but the long-distance telephone line is a four-wire line in which transmission and reception are separated. A hybrid circuit for 2-wire to 4-wire conversion is used at the connection point. Impedance matching at the connection point is difficult due to differences in subscriber line type and line length. Therefore, on the subscriber side, the received signal entering the 4-wire input side leaks to the 4-wire output side and becomes an echo and returns to the sender to interfere with the call.

Therefore, as shown in the example of FIG. 2, an echo called a pseudo echo is digitally processed on the subscriber line side based on a reception side input signal converted from a 4-wire line to a 2-wire line. An echo canceller is used that cancels the echo signal contained in the transmission signal on the transmission side by creating an estimated signal of the above and subtracting the pseudo echo from the input signal on the transmission side transmitted from the 2-wire line to the 4-wire line. There is.

The tap coefficient memory 14 of the echo canceller circuit 10 stores and holds an impulse response which is an echo signal taken out from the 4-wire type input side Sin via the double talk detecting section 16 as shown in FIG.

The digitized reception input signal X transmitted from the 4-wire section 4 is stored in the reception signal memory 11 in the echo canceller 10. In addition, the 2-wire / 4-wire conversion circuit 3
Echo signal Y generated from the received input signal X transmitted to the
Is included in the transmission input signal Sin from the 2-wire section 2 and is input to the subtractor 12.

When the 2-wire section 2 enters the receiving state, the transmission side input signal Sin of the 4-wire section 4 is only the echo signal Y.
The pseudo echo generation unit 13 performs the calculation shown in the equation (1) on the reception side input signal X accumulated in the reception signal memory 11 and the tap coefficient H accumulated in the tap coefficient memory 14 to obtain the pseudo echo signal Y. 'Is generated.

Y ′ _n = Σ (H _n · X _n−1 ) (1) The subtractor 12 subtracts the pseudo echo signal Y ′ generated by the pseudo echo generation unit 13 from the input echo signal Y, and the remaining This signal is sent to the four-line section 2 as the output signal Sout on the transmission side. As a result, the transmission side output signal Sout is
Only the residual echo signal E shown in the equation (2) is obtained.

E _n = Y _n −Y ′ _n (2) The tap coefficient correction unit 15 uses the residual echo signal E output from the subtractor 12 to perform the calculation of the equation (2) based on the learning identification method. , The tap coefficient H accumulated in the tap coefficient memory 14 is corrected, and the residual echo signal E is reduced as much as possible.

The processing of the echo canceller requires real-time operation, high speed, and high accuracy, but the memory for calculation is determined by the accuracy of the tap coefficient and the number of taps. Memory requirements,
Moreover, as the number of memory accesses increases, the number of memory accesses also increases, resulting in higher power consumption.

On the other hand, on the receiving side of the transmission line in which the spare line or the like branched to the transmission line remains connected,
Due to the reflection on the backup line, etc., the reflected wave is received with a slight delay, and noise called intersymbol interference occurs.However, like the echo canceller, the reflected wave noise is generated using a decision feedback equalizer. Have been removed.

Since this tap coefficient memory is also used in this decision feedback equalizer, the same thing as the echo canceller can be said.

[0012]

2. Description of the Related Art A conventional technique will be described with reference to FIGS. FIG. 8 is a conventional example, FIG. 9 is a configuration example of a tap coefficient memory in the conventional example, and FIG. 13 is a diagram illustrating an example of writing the impulse response value shown in FIG.

As shown in FIG. 5, the tap coefficient memory usually has a constant bit width, for example, a 16-bit width, and all tap coefficients have the same size.

The normal echo impulse response waveform has a long trailing waveform. If, for example, an impulse response Y as shown in FIG. 3 (1) occurs, it is sampled at a predetermined cycle, Sampling is performed at the positions indicated by 0 to 13 in (1). Then, the signal level value of the impulse response is represented by a two's complement in order to represent the level and also the + direction and the-direction with a sign, for example, as shown in FIG. 3 (2). With the conversion values as shown in Table 1 and Table 2, the read 2's complement value is counted as a value expressed in hexadecimal.

[0015]

[Table 1]

[0016]

[Table 2]

When the value expressed in hexadecimal is written in the tap coefficient memory, it is expressed in binary as shown in FIG. As can be seen from Tables 1 and 2, the values expressed in binary numbers, the + value is always the highest level "0", and the-value is always the highest level "1".

For example, the impulse response value sampled at the sampling timing "0" in FIG.
For example, if the hexadecimal number is "21BCh" (h indicates a numerical value expressed in hexadecimal number), if this numerical value is expressed in binary number, "0010000110111100" is displayed as shown in the uppermost row of FIG. Is expressed as

Next, with reference to FIG. 8, data writing and data reading of impulse response values to the tap coefficient memory 14 in the conventional example will be described. When the echo component Y input to the echo canceller 10 in FIG. 2 is input,
The double-talk detection unit 16 detects the impulse response, the tap coefficient correction unit 15, and the tap coefficient memory 1
4 and is stored as data represented by a binary number as described above.

For example, the impulse response value sampled at the sampling timing "0" in FIG. 3 (2) will be described. Although the impulse response value at this sampling timing is "21BC" in hexadecimal,
When input to the tap coefficient memory 14, it is converted into a binary number and becomes “0010000110111100”.

When "0000" designating the address "0" is input to the write decoder (not shown), the output terminal "0" of the write decoder becomes "H", for example, and the write enable terminal ( W
E) is turned on, the coefficient memory M0 is in the operating state, and the 16 memories are sequentially operated from the higher order "00100001".
Predetermined data (0 or 1) of 10111100 "is stored.

The same applies to the other memories. Also,
The same coefficient memory M0 will be described as an example for data reading. When "0000" designating the address "0" is input to the read decoder 22, the output terminal "0" becomes "H", for example, and each memory of the coefficient memory M0. The memory enable terminal (ME) of is turned on, the coefficient memory M0 is in the operating state, and “001000” is selected from 16 memories.
The predetermined data of "0110111100" is output.

The same applies to the other memories.

[0024]

As described above, when the impulse response value is written in the tap coefficient memory used in the echo canceller in the conventional technique, the input impulse response has a trailing waveform. Figure 10
When a coefficient memory of 14 taps from M0 to MD is used as shown in FIG. 6, at least the higher-order bit side of the coefficient memory from M3 to MA as a coefficient memory is seen in macro. The bit value of half of the same becomes the same value, and the same value as the sign bit indicating the sign of + direction or − direction is written.

Further, with respect to the coefficient memory MB and the subsequent positions near the tail of the impulse response, the same value as the code expressing the direction is written for the upper bit side 3/4 of each coefficient memory.

In the case of FIG. 10, it can be said that, for example, in the coefficient memory M3 and thereafter, the memory on the high-order bit side stores redundant data. Generally speaking, as shown in FIG. 9, each coefficient memory can be divided into a numerical bit represented by “X” and a bit having the same value as a sign bit represented by “S”. The bit represented by "S" is "0" or "1"
Or, one of the consecutive values will be written. Therefore, even if the block holding the same value as the higher-order code bit is deleted, no problem will occur if even one code bit is stored in the memory that is not deleted.

On the other hand, in order to obtain a pseudo echo component having a small residual echo component, it is necessary to perform calculation with high accuracy. Therefore, the number of taps in the tap coefficient memory can be increased and the number of calculation bits can be further increased. However, in reality, the number of circuits is increased, so that component space, power consumption, cost, etc. are often limited, and it is not always possible to obtain the desired pseudo echo component. It was

An object of the present invention is to solve such a problem, and an object thereof is to provide a tap coefficient memory in which the usage amount of a tap coefficient memory used in a large amount for echo component removal in an echo canceller or the like is reduced.

[0029]

In order to solve the above-mentioned problems, the tap coefficient memory of the present invention uses a plurality of taps as a tap coefficient for convolution calculation of an impulse response expressed by a complement of 2 as a negative number. In the held tap coefficient memory, the storage area of each tap coefficient has a remaining bit obtained by deleting a part of upper bits of the same value consecutively from the most significant bit of the tap coefficient expressed in binary code, It is determined corresponding to the size of each tap coefficient so as to have a bit width for storing the lower bits other than the upper bits. Then, so that each tap coefficient is output from the tap coefficient memory as data having the same bit width, the deleted higher-order bits are duplicated based on the remaining bits, and the data read from the storage area is used. It has means for adding and outputting. Further, the storage area deleted from the storage area for a certain tap coefficient due to the partial deletion of the higher-order plural bits is used as a part of the storage area for another tap coefficient.

As shown in FIG. 3, the impulse response has a large value at the beginning, but a very small value in the latter half, and has a trailing waveform. Therefore, FIG.
When the numerical value is represented by 2's complement as shown in, the value that could not be represented unless 16 bits at the beginning converges to a value close to 0 in the latter half, and thus represents the actual waveform value. Numerical bits, which are values, can be represented by a small number of bits, and the upper bits have the same value as the sign bit.

As described above, the waveform value of the input impulse response is large and the waveform value of the impulse response is expressed by a two's complement value in response to the waveform value gradually decreasing while converging. After securing the numerical bits and at least one or more sign bit required for the above, the memory on the upper bit side occupied by the bit having the same value as the sign bit is deleted.

Further, in reading the data written in the tap coefficient memory, a means for copying and adding a bit having the same value as the sign bit is provided, so that the waveform value close to the head of the impulse response is stored. The data of the tap coefficient memory, which is arranged in the upper blank portion of the coefficient memory of the tap and stores the waveform close to the tail of the impulse response, can also be correctly read.

[0033]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments will be described with reference to FIGS. 1 is a first embodiment, FIG. 2 is an echo canceller example, FIG. 3 is an impulse response example, FIG. 4 is a tap coefficient memory configuration example and impulse response value writing example of the first embodiment, and FIG. 5 is a first example. Comparison of configuration examples of tap coefficient memories of the embodiment / second embodiment / conventional example, FIG. 6 shows the second embodiment (1
2), and FIG. 7 shows the second embodiment (2/2).

In the figure, the same reference numerals as those in FIG.
20 and 40 are tap coefficient memories, 21 is a write decoder, 30 and 70 are sign extension units, 31 to 33, 51 to 5.
7, 81-86 are selectors, 34-37, 41-48,
Reference numerals 61 to 64, 71 to 78 denote OR gates, and 50 denotes a write control unit.

First, a configuration example of the tap coefficient memory of the first embodiment will be described with reference to FIG. The impulse response is stored in the tap coefficient memory 20 by using a coefficient memory composed of a 16-bit memory.
The memory composed of 6 bits is divided into blocks of 4 bits each.

Here, the block containing the least significant bit (LSB) is the first block, the next block is the second block,
Next block is 3rd block, most significant bit (MSB)
A block including is referred to as a fourth block.

Then, in the case of the tap coefficient memory for processing the impulse response waveform as shown in FIG.
As shown by the bold line in FIG. 4, the memory area for the numerical bit is a memory with some margin, and the memory for the code bit area is configured by deleting the memory indicated by the broken line in block units.

Regarding the coefficient memories M0 to M9 and the coefficient memories MA to MD constituting the tap coefficient memory 20, the coefficient memories M0 and M1 are the same as those in the conventional example. However, the coefficient memories M2 and M3 have the fourth block, the coefficient memories M4 to MB have the fourth block and the third block, and the coefficient memories MC to MD have the fourth block, the third block, and the second block, respectively. Use the deleted configuration.

The "0" to "2" memories of the first block of the coefficient memories M0 to MD are simply the code extension unit 30.
"0" to "2" in the first block
The memory other than the memory is the selector 31 of the sign extension unit 30.
~ 33.

The operation of reading the data written in the tap coefficient memory 20 in FIG. 1 will be described. The data is read from the coefficient memory M0 to the memories M1, M2, ... Sequentially at the same predetermined cycle as the sampling timing.
・ It will be done in order.

As an example, data writing to the three coefficient memories M0, M2, and MC will be described.
First, data reading from the coefficient memory M0 is performed by inputting an address to the read decoder 22 at a predetermined read timing.
An address that specifies the coefficient memory M0, for example, "000
Enter 0 ".

Then, only the "0" terminal of the output of the decoder 22 becomes "H", for example, and the memory enable terminals (ME) of the 16 memories constituting the coefficient memory M0 are turned on.
It becomes N, and 16 pieces of data, that is, 16-bit data is output.

4 of the memory "0" to "3" of the first block
The data is output simply by passing through the sign extension unit 30. However, the output of the memory “3” is the selector SEL ₁
It is also sent to the 31 "1" input terminal.

The 4th data of the second block is SEL ₁ 31
Sent to the "0" input terminal of. Read timing "0"
At this time, since the select signal "H" from the output of the OR gate 34 is not input, the SEL ₁ 31 is held in the "L" state, the 4 data of the first block is blocked, and the 4 data of the second block is blocked. Is selected and is output from SEL ₁ 31.

[0045] 4 data in the third block, and, also in the same manner 4 data of the fourth block, respectively SEL ₂ 32,
It is output from SEL ₃ 33. Next, in the data reading of the memory M2, an address designating the coefficient memory M2, for example, “0010” is input to the address input of the read decoder 22 at the read timing “1”.

Then, only the "2" terminal of the output of the decoder 22 becomes, for example, "H" (all other terminals are "L"), and the memory enable (ME) of each memory of the coefficient memory M2 composed of 12 memories is set. ) Is turned on, the coefficient memory M2 operates, and 12 pieces of data, that is, 12-bit data is output.

At the same time, the "H" at the "2" terminal of the output of the decoder 22 is also sent to the OR gate 38, so that the output of the OR gate 38 also becomes "H". Similarly, the OR gate 37
Output is also "H", so SEL ₁ 31 and SEL ₂ 3
2 continued inactive, ie, selects a "0" side input, SEL ₃ 33 operates to select "1" side input. As a result, each 4 data of the second and third blocks of the coefficient memory M2 is output via SEL ₁ 31 and SEL ₂ 32, respectively.

Then, the memory "B" of the third block is branched by the output of the selector SEL ₂ 32 and inputted to the "1" input terminal of SEL ₃ 31. However, since 33 of SEL ₃ is in the operating state. , SEL ₃ 33, the "1" input terminal side is selected, and the 4th data of the 4th block to be sent as the memory output is the 3rd of the coefficient memory M2.
"B" of the block, ie the stored coefficient memory M
The data of the uppermost memory of the data of 2 will be allocated.

Next, the data read from the coefficient memory MC is
An address designating the coefficient memory M2, for example, “1100” is input to the address input of the read decoder 22.
Then, only the "C" terminal of the output of the decoder 22 becomes "H", for example, and the coefficient memory MC including four memories is used.
Operates, and 4 data, that is, 4-bit data is output.

At the same time, the "C" terminal of the output of the decoder 22
"H" of is also sent to the OR gate 34, so
The output of the gate 34 also becomes "H". Similarly, the OR gate 36
Also becomes "H", and then the output of OR gate 37
Since it becomes “H”, SEL₁31, SEL_Two32, SE
L_ThreeAll 33 are operational. As a result, SEL ₁
4 data of 31 output outputs “3” of coefficient memory MC
And also SEL_Two4 data of 32 outputs are also SEL_Three
4 data of 33 outputs are also input to the input "1" side.
"3" of the coefficient memory MC to be output is output.

In this way, the data allocated as the memory output of the coefficient memory MC is the first data of the coefficient memory MC.
“3” of block, that is, stored coefficient memory M
The data in the uppermost memory of the C data will be used.

The writing of data to the coefficient memories M0 to MD of the tap coefficient memory 20 is the same as the conventional one, so the description thereof will be omitted, but the upper area region of each memory which is deleted is omitted. The data to be written is
Since the code bit data has the same value, the data will be discarded. Even if the data is discarded, the same data as the discarded data is saved, so there is no problem in reading the data as described above.

In this way, the memory of the tap coefficient memory can be used in about half the amount used in the conventional example. Next, a second embodiment will be described with reference to FIGS.

FIG. 5 is a diagram showing a comparison of the configuration examples of the tap coefficient memories of the first embodiment / second embodiment / conventional example, and FIG. 6 is the tap coefficient in the second embodiment (1/2). FIG. 7 is a diagram showing a portion for writing data to the memory, and FIG. 7 is a diagram showing a portion for reading data from the tap coefficient memory in the second embodiment (2/2).

In the second embodiment, as shown in (2) of FIG. 5, in the first embodiment, the coefficient memories M2 to M are used.
The memory of the coefficient memory M8 to the memory MD in which the unnecessary memory is deleted is mounted and arranged at the deleted memory position 7 to reduce the space occupied as the tap coefficient memory.

In FIG. 6, the data lines input to and output from the memories forming the coefficient memories are grouped in block units, and four data lines are represented by one. The mounting positions of the coefficient memories M8 to MD are the coefficient memory M2.
Since the write control unit 5 is arranged on the upper side of the mounting position of M7 to M7, it is composed of four OR gates and seven selectors so as to enable connection with the conventional memory input data line.
In addition to adding 0, an OR gate is also provided at the write enable (WE) terminal of each memory of the tap coefficient memory.

When writing data to the coefficient memories M2 to M7, the stored contents of the coefficient memories MD to M8 located at the same tap are not changed, and when writing data to the coefficient memories M8 to MD, the same stage is used. Located coefficient memory M7
A feedback line for re-inputting the output data is provided so that the stored contents of M2 are not changed.

Now, the writing of data to the tap coefficient memory will be described by taking the coefficient memories M0, M3 and MC as an example. Data writing is performed in the same cycle as the sampling cycle indicated by "0" to "13" in FIGS. 3A and 3B, for example, from the coefficient memory M0 to the memories M1 and M sequentially.
It is performed in order of 2, ...

First, in writing data to the coefficient memory M0, an address designating the coefficient memory M0, for example, "0000" is input to the address input section of the write decoder 21 at the sampling timing "0".

Then, only the "0" terminal of the output of the decoder 21 becomes "H", for example. Then, the write enable terminals (W
E) is turned on, and 16-bit data is input.
At this time, since the select terminals of all the selectors of the write controller 50 are in the "L" state, the data on the "0" side input of the selectors is selected and output.

As a result, the 16-bit data input to the memory passes through the selector as it is, and the coefficient memory M0
Is stored in the corresponding memory. Next, the coefficient memory M
For writing data to 3, an address for designating the coefficient memory M3, for example, “0011” is input to the address input of the write decoder 21 at the sampling timing “3”.

Then, only the "3" terminal of the output of the decoder 21 becomes "H", for example. Then, the write enable terminals (WE) of the 12 memories forming the coefficient memory M3 and the 4 memories forming the coefficient memory MC located at the same tap are turned on. Then, the 12-bit data excluding the uppermost 4 data of the input data is input to and stored in the twelve memories forming the coefficient memory M3.

Further, the "H" at the "3" terminal of the output of the decoder 21 turns on the write enable terminals (WE) of the coefficient memory M3 and the coefficient memory MC, and at the same time, the decoder 2
The “H” at the “3” terminal of the output of 1 is O of the write control unit 50.
Since it is also sent to the R gate 62, the output of the OR gate 62 also becomes "H", and the SEL ₄ 54 is in the operating state.

As a result, the coefficient memory M is sent to the selector 54.
The data output by C is fed back to the selector 5
Since it is input to the input "1" of 4, the own data is re-input to the coefficient memory MC.

Next, for writing data in the coefficient memory MC,
An address designating the coefficient memory MC, for example, “1100” is input to the address input of the read decoder 22 at the sampling timing “12”.

Then, only the "C" terminal of the output of the decoder 21 becomes "H", for example. Then, the write enable terminals (WE) of the four memories forming the coefficient memory MC and the 12 memories forming the coefficient memory M3 located at the same tap are turned on to form the coefficient memory MC4.
Bit data is input and stored.

The "H" at the "C" terminal of the output of the decoder 21 turns on the write enable terminals (WE) of the coefficient memory MC and the coefficient memory M3, and at the same time, the decoder 2
The “H” of the “C” terminal of the output of 1 is O of the write control unit 50.
Since it is also sent to the R gate 63 and the OR gate 64, the OR
The output of the gate 63 and the output of the OR gate 64 also become “H”, and SEL ₁ 51, SEL ₂ 52, SEL ₅ 55, and SE.
The five selectors L ₆ 56 and SEL ₇ 57 are activated. As a result, the four least significant data of the input memory signal are input to the coefficient memory MC via the selectors 51, 53 and 54.

At this time, the first to
As for each input data to the third block, the data output by itself is re-input via the selectors 56, 55, 54.

In this way, for example, the coefficient memory M5
When data is written in, the lower half of the input memory is written in the coefficient memory M5. At the same time, in the coefficient memory MA of the same tap, the data written in the coefficient memory MA is read and written again via the selector 55.

Next, data reading in the second embodiment will be described with reference to FIG. In the data reading method of the second embodiment, like the data reading method of the first embodiment, the highest memory data of each coefficient memory is branched and used to reproduce the data of the deleted code bit area. There is.

For data reading, the coefficient memory M0,
The three coefficient memories M2 and M8 will be described as an example.
First, when reading data from the coefficient memory M0, an address for designating the coefficient memory M0, for example, "0000" is input to the address input of a read decoder (not shown) at the read timing "0".

Then, only the output "0" terminal (memory access number "0" in FIG. 7) of the decoder becomes, for example, "H", and the memory enable terminals (16 memory elements of the coefficient memory M0 ( ME) is turned on and 16-bit data is output.

Regarding the coefficient memories M0 and M1,
Since the "0" terminal of the output of the decoder is not connected to the OR gate of the sign extension unit 70, all the selectors hold the inoperative state, and the "0" side of the input is selected. 4 the data of the memory device "0" to "3", via the selector SEL ₂ 32, is sent to the memory output section.

Similarly, the 4th data of the second block is SEL.
₃ 83 and SEL ₄ 84 are sent to the memory output section, the 4th data of the third block is sent to the memory output section via SEL ₅ 85, and the 4th data of the 4th block is
Through the SEL ₆ 86 sent to the memory output section.

Next, the data read from the coefficient memory M2 is
An address designating the coefficient memory M2, for example, "0010" is input to the address input of a read decoder (not shown).

Then, only the "2" terminal of the output of the decoder becomes "H", for example, and the memory M2 composed of 12 memory elements and the coefficient memory M located at the same tap.
D works. As a result, 12-bit data of the coefficient memory M2 and 4-bit data of the coefficient memory MD are output.

At the same time, the "H" at the "2" terminal of the decoder output is also sent to the OR gate 78 of the sign extension unit 70, so that the output of the OR gate 78 also becomes "H". Since Similarly, the output of the OR gate 77 also becomes "H", SEL ₆ 8
Since 6 operates and the "1" side of the input is selected, the "B" of the third block of the memory M2 is output via the SEL ₆ 86, and the transmission of four data of the memory MD is blocked.

Next, the data read from the coefficient memory M8 is
An address designating the coefficient memory M8, for example, "0100" is input to the address input of the read decoder. Then, only the “8” terminal of the output of the decoder becomes “H”, for example, and the coefficient memory M8 composed of eight memories and the coefficient memory M7 located at the same tap operate. As a result, the 8-bit data of the coefficient memory M8 and the 8-bit data of the coefficient memory M7 are output.

At the same time, the “H” at the “8” terminal of the output of the decoder is also sent to the OR gate 73 and the OR gate 76 of the sign extension unit 70. As a result, firstly, the OR gate 7
After 3, the output of the OR gate 72 becomes "H", and SE
L ₁ operates and the first block (“0”) of the coefficient memory M8
Data ~ "3") is sent via the SEL ₁ 81, SEL ₂ 82 to the lowest memory output.

Second, the OR gate 73 is followed by SEL ₂
Operates and the second block (“4”-
The data "7") is sent as the data "4" to "7" of the memory output through the SEL ₃ 83 and SEL ₄ 84.

Thirdly, the OR gate 75 is turned ON following the OR gate 76, the SEL ₅ 85 operates, the data of the uppermost memory "7" of M8 is sign-extended, and the data "8" of the memory output. ~ Sent as "B".

Fourthly, when the OR gate 75 is turned ON, the OR gate 77 is turned ON, the SEL ₆ 86 is operated, the data of the uppermost memory "7" of M8 is sign-extended, and the data of the memory output is outputted. It is sent as "C" to "F".

When a memory having a fixed bit width is used, it is possible to have a tap coefficient that is about twice the normal tap coefficient by assigning another tap coefficient to only the upper code bits.

[0084]

By using the present invention, the amount of memory required even when handling a large number of tap coefficients can be greatly reduced, so that the power consumption required for the memory and the cost required for the memory itself can be reduced. You can

Further, by arranging the memory at another tap position at the reduced memory position, it is possible to expect a reduction in layout size and cost.

[Brief description of the drawings]

FIG. 1 is a first embodiment.

[Fig. 2] Example of echo canceller

[Fig. 3] Example of impulse response

FIG. 4 is a tap coefficient memory configuration example of the first embodiment and an impulse response value writing example.

FIG. 5 is a comparison of configuration examples of tap coefficient memories of the first embodiment / second embodiment / conventional example.

FIG. 6 Second embodiment (1/2)

FIG. 7: Second embodiment (2/2)

FIG. 8: Conventional example

FIG. 9 is a configuration example of a tap coefficient memory of a conventional example.

FIG. 10 is an example of writing impulse response values to a tap coefficient memory of a conventional example.

[Explanation of symbols]

2 2 wire section line 3 2 wire 4 wire conversion circuit 4 4 wire section line 10 Echo canceller 11 Received signal memory 12 Subtractor 13 Pseudo echo generator 14, 20, 40 Tap coefficient memory 15 Tap coefficient corrector 16 Double talk Detector 21,22 Decoder 30,70 Code extension 31-33,51-57,81-86 Selector (S
EL) 34-37, 41-48, 61-64, 71-78
OR gate 50 Write control unit M0 to M9, MA to MD Coefficient memory

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location H04B 3/23 H04B 3/23

Claims (3)

[Claims] 1. A tap coefficient memory for holding a plurality of taps, wherein a negative number is represented as a two's complement impulse response as a tap coefficient for a convolution operation, and a storage area of each tap coefficient is represented by a binary code. Each tap has a bit width for storing the remaining bits obtained by deleting a part of the upper-order bits having the same value consecutively from the most significant bit of the tap coefficient and the lower-order bits other than the higher-order bits. A tap coefficient memory characterized in that it is defined corresponding to the size of the coefficient. 2. The tap coefficient memory according to claim 1, wherein the deleted higher-order bits are stored in the remaining bits so that each tap coefficient is output from the tap coefficient memory as data having the same bit width. A tap coefficient memory comprising means for copying based on bits, adding the data read from the storage area, and outputting the data. 3. A storage area deleted from a storage area for a certain tap coefficient due to partial deletion of a plurality of bits on the upper side is used as a part of a storage area for another tap coefficient. 3. The tap coefficient memory according to claim 1, wherein the tap coefficient memory is a tap coefficient memory.