JPH09120391A - Data transfer method for parallel computer and parallel computer processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the message transfer efficiency by sending a packet consisting of a packet body and a packet header including both transfer command and transmission control data to a reception processor to eliminate the need for copying the transfer data main body and also to transfer a single message with transfer of a single packet. SOLUTION: A packet header 11 provided on a main storage 4 of a transmitter PE 1 includes a command area 13 of a command 15 which instructs the transfer of data and a non-command area 14 which transfers the data designated by a program. The transmission control data 16 are set in the area 14. Then a transmission communication device 3 reads a packet body 17 pointed by the command 15 out of the storage 4 as a packet body 12. Then the device 3 adds the header 11 to the body 12 to form a packet 10 and sends this packet to an inter-PE connection network 2 to transfer it to the PE 1 of the reception side.

Description

Detailed Description of the Invention

(Technical Field of the Invention) Technical Field of the Invention Conventional Technology (FIGS. 8 to 11) Problems to be Solved by the Invention (FIGS. 10 and 11) Means for Solving the Problems Embodiments of the Invention (a) Description of First Embodiment (FIGS. 1 to 5) (b) Description of Second Embodiment (FIGS. 6 and 7)

[0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention applies a data transfer method in a parallel computer configured by connecting a plurality of processing devices (hereinafter referred to as PEs (Processor Elements)) to each other so that they can communicate with each other, and to apply this method. And a parallel processor for a parallel computer, particularly, a distributed main memory MIMD (Multiple
The present invention relates to a technique suitable for use in an instruction stream multiple data stream type parallel computer system.

[0003]

2. Description of the Related Art In recent years, there has been a demand for speeding up and increasing the capacity of computer systems due to the need to process enormous amounts of data at high speeds such as numerical calculation and image processing. Along with this, a parallel processing technology has been researched and developed in which a plurality of PEs are provided to perform parallel processing while communicating with each other.

Generally, in a parallel computer system, as shown in FIG. 8, for example, n PEs (PE numbers # 1 to # 1) are used.
(#N is given) 101 are connected to each other so that they can communicate with each other via the PE PE network 100 as a communication means. As shown in FIG. 9, each PE 101 has a transfer processing unit 102, an instruction processing unit (CPU) 103, and a main memory 104.

Here, the transfer processing unit 102 uses the main memory 10
4 performs data transmission / reception processing, and the instruction processing unit 103 performs program processing during communication between PEs 101. By providing the transfer processing unit 102 and the instruction processing unit 103 independently as described above, the load and overhead of the instruction processing unit 103 can be reduced. In addition, the transfer processing unit 102
Is configured so that the transmission process and the reception process can be simultaneously performed in parallel, thereby improving the data transfer rate and the data transfer efficiency.

By the way, in recent years, in the distributed main memory MIMD type parallel computer system as described above, parallel programming using a programming model called a message passing model is becoming popular. This message passing model allows the PEs 10 to communicate with each other by explicitly transmitting and receiving messages.
This is a model for executing data transfer processing between one PE 101 and synchronization processing between the PEs 101. Therefore, it is necessary to efficiently realize the message passing model in the parallel computer system.

When data is transferred in the message passing model, generally, the sending PE 101 adds the sending control data specified by the program to the transfer data body, while the receiving PE 101 receives the received transfer data body. It is necessary to add the control data on the receiving side to the control data on the transmitting side and the control data on the transmitting side for holding and management. Below, FIG.
A conventional message transfer process will be described with reference to FIGS. 10 and 11, the data holding state in the main memory 104 of each PE 101 on the transmitting side and the receiving side is shown, and a schematic display is made as the time progresses from left to right. .

In the message transfer process shown in FIG. 10, the program on the sending side PE 101 first causes the main memory 104 to execute.
In the above, while copying the transfer data body 201 such as a part of the array,
The packet body 200 is assembled by adding the transmission side control data 202 such as the identifier (hereinafter referred to as ID) of the transmission message. At the same time, the program on the transmitting side PE 101 also assembles the transfer command 210 to the communication device (transfer processing unit 102 in FIG. 9) for transferring the packet body 200 in the main memory 104. Then, for the communication device (transfer processing unit 102 in FIG. 9),
The execution of the assembled transfer command 210 is instructed [above, refer to period (1) in FIG. 10].

In response to this, the communication device reads the packet body 200 on the main memory 104 pointed by the transfer command 210, and transfers it.
Is used as a packet header, and a packet composed of this packet header and the packet body 200 is used as the inter-PE coupling network 1
Send to 00. The PE-to-PE coupling network 100 includes the receiving PE 101 included in the transfer command 210 in the packet header.
The packet is transferred to the PE 101 on the receiving side in accordance with the designation information of the above [see the period (2) in FIG. 10 above].

In the PE 101 on the receiving side, the transfer command 210 in the packet header is transmitted to the communication device (transfer processing unit 1 in FIG. 9).
02), the processing such as command analysis is executed, and the packet body 200 including the transmission side control data 202 and the transfer data body 201 is stored in the message reception queue 110 on the main memory 104 [above ,
Refer to the period (3) in FIG. 10].

Then, the program on the receiving side PE 101 stores the receiving side control data 220 on the main memory 104.
Is added to the received message (packet body 200) [see period (4) in FIG. 10]. The receiving side control data 220 includes the ID of the received message, information for pointing the message in the message receiving queue 110, and the like.

On the other hand, in the message transfer process shown in FIG. 11, the program on the transmitting side PE 101 first causes the identifier of the transmitted message (hereinafter, I
(Referred to as “D”) and the like, and a transfer command 210A to the communication device for transferring the control data 202 on the transmitting side and a transfer command 21 to the communication device for transferring the main body 201 of the transfer data.
Assemble with 0B. Then, the communication device (the transfer processing unit 102 in FIG. 9) is instructed to execute the two assembled transfer commands 210A and 210B [above, refer to the period (1) in FIG. 11].

In response to this, the communication device reads the transmission side control data 202 on the main memory 104 pointed by the transfer command 210A, and transfers the transfer command 2
With 10A as the packet header and the transmission side control data 202 as the packet body, the first packet is sent to the PE-PE coupling network 100. Subsequently, the communication device uses the transfer command 210B to point to the main memory 104.
Read the above transfer data body 201 and transfer command 2
The second packet is sent to the PE-to-PE coupling network 100 with 10B as the packet header and the transfer data body 201 as the packet body.

The PE-to-PE coupling network 100 transfers these two packets to the transfer commands 210A,
According to the designation information of the receiving PE 101 included in 210B, the data is transferred to the receiving PE 101 [above, refer to period (2) in FIG. 11]. In the PE 101 on the receiving side, the transfer commands 210A and 210B in the packet header of each packet are sent to the communication device (the transfer processing unit 102 in FIG. 9), where command analysis and other processing are executed and transferred as a packet body. The transmission side control data 202 and the transfer data body 201 are integrated and stored in the message reception queue 110 on the main memory 104 [above,
Refer to the period (3) in FIG. 11].

Then, the program on the receiving side PE 101 stores the receiving side control data 220 on the main memory 104.
Is added to the received message (integrated transmission side control data 202 and transfer data body 201) [see period (4) in FIG. 11]. This receiving side control data 22
As described above, 0 includes the ID of the received message, information for pointing the message in the message reception queue 110, and the like.

[0016]

However, as shown in FIG.
In the message transfer process shown in (1), since the transfer data body 201 needs to be copied when assembling the message (packet body 200) in the main memory 104 of the sending PE 101, a large amount of processing is required. Therefore, when transferring a large-capacity message, there is a problem that the copy process requires a lot of time and the message passing cannot be performed efficiently.

In the message transfer process shown in FIG. 11, it is not necessary for the sending PE 101 to copy the transfer data body 201, but it is necessary to assemble and transfer two packets to transfer one message. Since one transfer command 210A and 210B must be assembled, there is a problem that the processing amount is large and the efficiency is low.

Further, in the message transfer process shown in FIG. 11, if the packet from another PE interrupts between the two packets in the PE 101 on the receiving side, the subsequent process becomes troublesome. There is also a problem that special control such as not receiving packets from other PEs is required until the end of receiving the packet.

The present invention was devised in view of such problems, and it is not necessary to copy the transfer data body, and
Provided is a data transfer method in a parallel computer and a processor for a parallel computer, in which one message can be transferred by each packet transfer, the processing amount for message transfer is reduced, and the efficiency of message transfer is improved. The purpose is to do.

[0020]

Therefore, a data transfer method in a parallel computer according to the present invention is a data transfer method in a parallel computer constituted by connecting a plurality of processing devices so that they can communicate with each other via a communication means. Then, the transmission side processing device transmits a packet including a packet header containing various control information and a packet body containing the transfer data body to the communication means, and the communication means receives the packet in a predetermined manner. In the one for transferring the data in the main memory of the transmitting side processing device to the main memory of the receiving side processing device by transferring to the side processing device, the data created in the main memory of the transmitting side processing device The packet header is used to transfer the command area (command area for hardware) for commands that direct data transfer and the data specified by the program. Non command area of the constructed from (program area) and is characterized by setting the transmission side control data to the non-command area of the packet header (claim 1).

In the receiving side processing device of claim 1, when the packet is received, both the packet header and the packet body may be stored in the message reception queue on the main memory (claim). 2) When the packet is received, the non-command area of the packet header and the packet body may be stored in the message reception queue on the main memory (claim 3).

Further, in claim 3, the command area of the packet header may be stored in a command receiving area on the main memory (claim 4). At this time, the command receiving area is configured to be able to store a plurality of command areas, and if no abnormality occurs during reception, the command area of the packet header is overwritten and stored in the command receiving area. At the time of occurrence, the command area of the packet relating to the cause of the abnormality is held in the command receiving area, and in the command receiving area,
When there is no valid area for storing a new command area, the reception of a new packet is stopped (claim 5).

Further, in claim 2, a process identifier is set in the command area of the packet header in the transmitting side processing device, and a message receiving queue is provided in the main memory of the receiving side processing device for each process identifier. The receiving-side processing device may be configured to store both the packet header and the packet body in a message reception queue corresponding to a process identifier in a command area of the packet header (claim 6). .

Similarly, in the third to fifth aspects, a process identifier is set in the command area of the packet header in the transmitting side processing device, and a message receiving queue for each process identifier is stored in the main memory of the receiving side processing device. In addition, the receiving side processing device may be configured to store the non-command area of the packet header and the packet body in a message reception queue corresponding to the process identifier of the command area of the packet header ( Claim 7).

On the other hand, the processor for parallel computers of the present invention is
A processing device that is communicably connected to another processing device via a communication means and constitutes a parallel computer, and a packet including a packet header including various control information and a transfer data body when transmitting data to the other processing device. In a device for transmitting a packet including a body to the communication means, the packet header transfers a command area for a command instructing data transfer (a command area for hardware) and data designated by a program. And a non-command area (program area) for performing transmission, and transmission side control data is set in the non-command area of the packet header (claim 8).

In the above-described data transfer method in the parallel computer and the processing device for the parallel computer of the present invention, at the time of data transmission, the command for instructing the data transfer is set in the command area of the packet header, and the transmission side control data is set by the program. Is set in the non-command area of the packet header, and a packet composed of a packet header containing both a transfer command and transmission side control data and a packet body containing the transfer data body is transferred to the receiving side processing device.

At this time, since the transfer data body is read from the main memory as a packet body designated by the transfer command set in the command area of the packet header, the transfer data body is stored in the main memory when the packet is assembled in the transmitting side processing device. Since there is no need to copy above, and because the packet header contains the control data on the transmission side, it is not necessary to transfer two packets, and one message can be transferred by one packet transfer. it can.

[0028]

Embodiments of the present invention will be described below with reference to the drawings. (A) Description of First Embodiment FIG. 1 is a block diagram showing the overall configuration of a parallel computer system as a first embodiment of the present invention. As shown in FIG. 1, the parallel computer system of the present embodiment also , N PEs (PE number as #
1 to #n) are connected to each other so that they can communicate with each other via an inter-PE coupling network 2 as a communication means.

Each PE1 is the PE1 with PE number # 1 in FIG.
As shown in the block, it is configured to include at least the communication device 3 and the main memory 4. In FIG. 1, only the PE1 with PE number # 1 is shown, but the PEs with other PE numbers # 2 to #n are shown.
It goes without saying that 1 also has the same configuration and has various functions described later.

Here, the communication device 3 performs transmission / reception processing of data in the main memory 4 similarly to the transfer processing unit 102 described above with reference to FIG. 9, and its detailed configuration and operation are shown in FIGS. 5, which will be described later. Then, each P of the present embodiment
When performing data transmission (message transfer) to another PE1, the E1 is basically a packet 1 including a packet header 11 and a packet body 12 as in the conventional case.
0 is transmitted to the PE-to-PE connection network 2,
In this embodiment, the packet header 11 uses various commands for instructing data transfer (see FIG. 3 for details;
A packet header is composed of a command area (hardware command area) 13 in which a communication device transfer command 15 is set, and a non-command area (program area) 14 for transferring data designated by a program. In the non-command area 11 of 11, transmission side control data 16 is set by the program.

The transfer data body 17 such as a part of the array on the main memory 4 is stored in the command area 1 of the packet header 11.
It is designated by the communication device transfer command 15 set to 3, and is read from the main memory 4 as the packet body 17. The contents of the packet head 11 are, for example, as shown in FIG. In the example shown here, the words "0" to "15" are the portions corresponding to the above-mentioned command area 13, and the words "16" to "31".
Is a portion corresponding to the non-command area 14 in which the transmission side control data 16 is set.

As the communication device transfer command 15 set in the command area 13, as shown in FIG. 3, the reception PE number is transmitted in the word “0”, the transmission PE number is transmitted in the word “1”, and the transmission PE number is transmitted in the word “2”. A command code, a transmission packet layout designation, a transmission body layout designation, and a reservation are set, and similarly, a reception command code, a reception packet layout designation, a reception body layout designation, and a reservation are set in the word “3”. Further, the word “4” has the element length, the word “5” has the body length, the word “6” has the transmission body start address, the word “7” has the reception body start address, and the word “8” has the transmission stride distance. 1 is the transmission stride distance 1 in the word "9" and the number of elements is transmission stride 2 in the word "10"
, The word "11" is reserved, the word "12" is the received stride distance 1, the word "13" is the received stride distance 1 number of elements, and the word "14" is the received stride distance 2.
The reservation is set in the word "15".

Here, of the above-mentioned setting data, the “transmission packet arrangement designation” has only one arrangement method for the transmission packet 10 (packet header 11 and packet body 12) in the present embodiment, so this “transmission packet arrangement designation” is possible. The contents of the "Transmit packet placement designation" area are ignored. Further, for example, when "0x00" is set as the "receive packet arrangement designation", the packet body 12 (transfer data body 17) is stored at the receive body start address, and when "OxO1" is set, The packet header 11 and the packet body 12 are stored in the message reception queue 18.

The "transmission body layout designation" and "reception body layout designation" are, for example, "0x00" for continuous layout, "0x01" for stride layout, "0x02" for double stride layout, "0x03". Specifies the indirect placement. At this time, when the body start address is S, the stride distance 1 is D1, the stride distance 2 is D2, and the stride distance 1 element number is N1, when the stride arrangement is designated as “transmit body arrangement designation”, the transmitting side PE1 , Address S, S + D1, S + 2 * D1, S + 3 * D1,
,, S + N1 * D1 data is read from the main memory 4 as transfer data, while stride arrangement is specified as "receive body arrangement specification", the receiving side PE1 receives addresses S, S + of main memory 4 Transfer data will be stored in D1, S + 2 * D1, S + 3 * D1, ..., S + N1 * D1.

When the double stride arrangement is designated as the "transmit body arrangement designation", the addresses S, S + D1, S + 2 * D1 ,. ...., S + N1 * D1, S + N1 * D1 + D2, S + N1 * D1 + D2 + D1, S + N1 * D1 + D2 + 2 * D1, ....., S + 2 * N1 * D1 + D2, S + 2 * N1 * D1 + 2 * D2, S + 2 * N1 * D1 + 2 * D2 + D1, S + 2 * N1 * D1 + 2 * D2 + 2 * D1 ,. , S + 3 * N1 * D1 + 2 * D2, S + 3 * N1 * D1 + 3 * D2, ............ While data is read from main memory 4 as transfer data , When the double stride arrangement is designated as the “reception body arrangement designation”, the main memory 4 is set in the receiving side PE1.
The transfer data is stored at the above address in.

By setting the transfer command as described above in the command area 13 of the packet header 11, in the packet body 12 of this embodiment, stride transfer or partial array transfer of the array on the main memory 4 of the sending side PE 1 is performed. Can be done. However, the packet body 12 on the main memory 4 of the receiving side PE 1 is always stored as continuous data, as shown in FIGS.

Next, the data transfer procedure in the parallel computer system of the first embodiment will be described with reference to FIG. Note that FIG. 2 shows a data holding state in the main memory 4 of each PE 1 on the transmitting side and the receiving side, and is schematically displayed as time progresses from left to right. As shown in FIG. 2, the program on the transmitting side PE1 first designates the communication device transfer command 15 for transferring the transfer data body 17 in the command area 13 on the main memory 4, and As shown, the sending side control data 16 such as the ID of the sending message is designated in the non-command area 14 following the command area 13.
The command area 13 and the non-command area 14 are combined to form a packet header 11. And the communication device 3
(See FIG. 1) is instructed to execute the communication device transfer command 15 in the command area 13 of the packet header 11 [see the period (1) in FIG. 2 above].

In response to this, the transmission side communication device 3 reads the packet body 17 on the main memory 4 pointed by the communication device transfer command 15 as the packet body 12, and the communication device transfer command 15 and the transmission side control data 16 are read. Is added to the packet header 11 to form a packet 10 and the packet 10 is sent to the PE-to-PE coupling network 2. PE
The inter-connection network 2 follows the designation information of the receiving side PE1 included in the communication device transfer command 15 in the packet header 11,
The packet 10 is transferred to the receiving side PE1 [above, refer to period (2) in FIG. 2].

In the receiving side PE1, the communication device transfer command 15 of the packet header 11 is sent to the receiving side communication device 3 and processing such as command analysis is executed, and at the same time, the entire packet 10, that is, the communication device transfer command. Packet header 11 including 15 and sender control data 16
And the packet body 12 including the transfer data body 17 are stored in the message receiving queue 18 which is a cyclic queue on the main memory 4 (see the period (3) in FIG. 2).

Then, the program on the receiving side PE1
In the main memory 4, the receiving side control data 19 is added to the received message (packet 10) [see period (4) in FIG. 2]. The receiving side control data 19 includes the ID of the received message, information for pointing the message in the message receiving queue 18, and the like.

It is to be noted that at the transmitting side PE1, the packet header 1
While setting the process ID as one of the information of the communication device transfer command 15 in the command area 13 of No. 1, a plurality of message reception queues 18 may be provided in the main memory 4 of the receiving side PE 1 for each process ID. Good. in this case,
In the receiving side PE1, both the packet header 11 and the packet body 12 have a message receiving queue 18 corresponding to the process ID of the command area 13 of the packet header 11.
Is stored in

Now, the detailed configuration of the communication device 3 in each PE 1 of this embodiment will be described with reference to FIG. The communication device 3 shown in FIG. 4 is also used in the second embodiment described later. The communication device 3 is roughly divided into three parts, namely, a transmission system 3A,
It is composed of a receiving system 3B and a main memory access control section 3C. The main memory access control unit 3C accesses the main memory 4 in response to commands from the transmitting system 3A and the receiving system 3B, transfers data from the main memory 4 to the transmitting system 3A, and receives data from the receiving system 3B to the main memory 4. Control data transfer to and from.

The transmission system 3A includes a command register 21, a decoder 22, a control circuit 23, an address register 24, a selector 25, an adder 26, and a body address register 2.
7, an address generation circuit 28, a packet header queue base address register 29, a transmission pointer 30, a 1 adder 31, a transmission end pointer 32, a comparator 33 and an output buffer 34.

Here, the command register 21 sends data to the main memory 4 via the main memory access control unit 3C.
The communication device transfer command 15 of the packet header 11 read out from is temporarily held. Decoder 2
2 analyzes the transfer command 15 held in the command register 21, and the control circuit 23 controls each part of the transmission system 3A based on the analysis result of the decoder 22.

The address register 24 temporarily holds the address on the main memory of the transfer data to be read from the main memory 4, and the address register 24 holds the address data selected by the selector 25. It has become. The selector 25 selects address data from any one of the adder 26, the body address register 27 and the address generation circuit 28 and outputs it to the address register 24.

The adder 26 sequentially generates addresses corresponding to the packet header 11 in order to read the packet header 11 from the main memory 4, and the register 29
The packet header queue base address (head address on the main memory 4 of the packet header 11) held in the above is added to the value of the transmission pointer 30 and output to the selector 25. The transmission pointer 30 is set to 0 as an initial value, but when data transmission is started, the transmission pointer 3
The value of 0 is incremented by 1 by the 1 adder 31.

Therefore, the output from the adder 26 sequentially increases by 1 with the packet header queue base address as the initial value. The address value from the adder 26 as described above is selected from the packet header queue base address until the final address of the packet header 11 is reached.
5 are sequentially set in the address register 24. As a result, the packet header 11 is read from the main memory 4 via the main memory access control unit 3C.

The body address register 27 holds the body address (the start address of the transfer data body 17 in the main memory 4, the above-mentioned body start address S), and after reading the packet header 11, the selector. 25, the body address of the register 27 is set in the address register 24, whereby the reading of the transfer data body 17 forming the packet body 12 is started.

When the body address is set in the address register 24, the selector 25 thereafter operates to select the address value from the address generation circuit 28 and sequentially set it in the address register 24. At this time, the address generation circuit 28 generates an address by using the body address as an initial value in accordance with the transmission body arrangement specified in the transfer command 15. In addition to outputting a value that increments by one, if the transmission body arrangement is stride arrangement designation or double stride arrangement designation, an address value is generated based on the above-described calculation formula.

The address value from the address generating circuit 28 is sent to the address register 2 via the selector 25.
4 is sequentially set, and as a result, the transfer data body 17
However, the packet body 12 is sequentially read from the main memory 4 via the main memory access control unit 3C. The packet header 11 and the packet body 12 read as described above are held in the output buffer 34 as the packet 10 and transferred to the receiving side PE 1 via the PE-to-PE coupling network 2 as will be described later with reference to FIG. It has become so.

The transmission end pointer 32 has a transmission end pointer value set in advance, and the comparator 33
Compares the value of the transmission pointer 30 with the value of the transmission end pointer 32, and outputs a transmission stop signal when they match. On the other hand, the receiving system 3B has the command register 3
5, decoder 36, control circuit 37, input buffer 38,
Address register 39, selector 40, adder 41, command reception area address registers 42 and 43, address generation circuit 44, message reception queue base address register 45, reception pointer 46, 1 adder 47, reception start pointer 48 and comparator 49. It consists of

Here, the command register 35 temporarily holds the communication device transfer command 15 of the packet header 11 when receiving data from the PE-to-PE coupling network 2, and the decoder 36 holds it in the command register 35. The control circuit 3 analyzes the transferred transfer command 15.
Reference numeral 7 controls each part of the reception system 3B based on the analysis result of the decoder 36.

The input buffer 38 temporarily holds the packet 10 received from the PE 1 on the transmitting side through the PE-PE coupling network 2, and the data of the packet 10 held in the input buffer 38 is as shown in FIG. As will be described later according to the flowchart shown in FIG. 7, the message reception queue 1 on the main memory 4 is sequentially paired with the address shown in the address register 39 via the main memory access control unit 3C.
8 is stored.

The address register 39 is the input buffer 3
It temporarily holds the address in the main memory 4 to which the packet 10 held in 8 is to be written. The address data selected by the selector 40 is held in this address register 39. . The selector 40 selects the address data from any one of the adder 41, the command receiving area address registers 42 and 43, or the address generation circuit 44, and then selects the address register 39.
Is output to The command reception area address registers 42 and 43 are not used in the first embodiment, but are used when realizing the second embodiment described later. Regarding the configuration and operation of these constituent elements, the second embodiment will be described. This will be described in the description of the embodiment.

The adder 41 is for sequentially generating a write address when the packet 10 held in the input buffer 38 is stored in the message reception queue 18 in the main memory 4, and is held in the register 45. The message reception queue base address (empty start address of the message reception queue 18) and the value of the reception pointer 46 are added and output to the selector 40.

Although the reception pointer 46 is set to 0 as an initial value, when the data writing to the main memory 4 is started, the value of the reception pointer 46 is set to the reception queue 18 for the message reception queue 18. Each time one block of data is written, it is incremented by 1 by the 1 adder 47 and set in the address register 39 via the selector 40.

Therefore, the output from the adder 41 is sequentially incremented by 1 every time one block of data is written with the message reception queue base address as an initial value. The address value from the adder 41 is sent to the address register 3 via the selector 40 until the entire packet 10 is written.
It is sequentially set to 9. Then, the data of the packet 10 is written in the message reception queue 18 of the main memory 4 via the main memory access control unit 3C in combination with the addresses sequentially set in the address register 39.

At this time, when the address value from adder 41 is set in address register 39, address generation circuit 44 stores in address register 39 each time data is written from input buffer 38 to main memory 4. The data storage byte length is added once to the set address value, and the addition result is set in the address register 39 via the selector 40. This address generation circuit 4
The addition process by 4 is performed until the data writing for one block is completed or the writing of all the packets 10 is completed.

The reception head pointer 48 is set in advance to the head pointer value of the message reception queue 18 which is a cyclic queue, and the comparator 49 sets the value of the reception pointer 46 and the value of the reception head pointer 48. Are compared with each other, and if they match, a reception overflow signal is output. Next, the operation of the first embodiment [particularly the operation at the time of data reception (inter-PE coupling network 2 and reception system 3B)] will be described according to the flowchart (steps S1 to S12) of FIG.

The inter-PE coupling network 2 always captures the number of empty words in the input buffer 38 of each PE 1 connected to the inter-PE coupling network 2 (step S1), and the predetermined PE1
If there is a packet 10 destined for (reception side PE) and the input buffer 38 of this reception side PE1 is empty (step S2), the packet 10 is accompanied by a packet transmission start signal in the first word. Is started (step S3), and the entire packet 10 is transferred to the receiving side PE1 according to the empty state of the input buffer 38 of the receiving side PE1 (step S4). The process in step S4 is repeated until the transfer of one packet 10 is completed (until a YES determination is made in step S5). When the transfer of packet 10 is completed, the process returns to step S1.

PE interconnection network 2 through steps S3 and S4
When packet transfer to the PE1 on the receiving side is started, the packet 10 is read in the receiving system 3B in the communication device 3 on the PE1 on the receiving side as long as the input buffer 38 is empty (step S6). At this time, when the command code (communication device transfer command 15) in the packet header 11 flows, the transfer command 15 is read into the command register 35 (step S7).

In step S7, the command register 35
The command code read in is decoded by the decoder 36, and a signal for controlling the receiving and storing method of the packet 10 is generated by the control circuit 37 (step S).
8). In the present embodiment, as described above with reference to FIG. 2, the entire packet 10, that is, the communication device transfer command 15
And a packet header 11 including transmission side control data 16
And the packet body 12 including the transfer data body 17 are enqueued to the message reception queue 18 on the main memory 4 by the selector 40 first.
The address value from is selected and set in the address register 39.

In other words, the address register 39 first has the message reception queue base address register 45.
Is added to the value of the reception pointer 46.
The value of the reception pointer 46 is incremented by one by the adder 47 each time the storage of one block of packet data in the message reception queue 18 is completed (step S9).

The address set in the address register 39 and the packet data from the input buffer 38 are paired and sent to the main memory access control unit 3C, and the packet data is sent to the main memory 4 via the main memory access control unit 3C. Stored in the above message reception queue 18 (step S1)
0). When the packet data is stored once in step S10, the data storage byte length of one time is added to the address value of the address register 39 by the address generation circuit 44, and the addition result is stored in the address register 39 via the selector 40. It is set (step S11).

In the processing in steps S10 and S11, the packet data transfer for one block to the message reception queue 18 is completed or all the packets 10 are transferred to the message reception queue 18 (YES determination in step S12). Until the reception of the packet 10 is completed, that is, the packet 10 is repeatedly executed.
Are repeatedly executed until all of the above are transferred to the message reception queue 18 (until YES determination is made in step S13).

As described above, according to the first embodiment of the present invention, the packet 10 including the packet header 11 including both the transfer command 15 and the transmission side control data 16 and the packet body 12 including the transfer data body 17 is described. Are transferred to the PE1 on the receiving side, it is not necessary to copy the transfer data body 17 on the main memory 4 when assembling the packet on the PE1 on the sending side, and one message can be transferred by one packet transfer. Therefore, the processing amount for message transfer /
There is an advantage that the overhead can be reduced and the performance and efficiency of such message transfer (message passing) are significantly improved.

(B) Description of Second Embodiment Next, a second embodiment of the present invention will be described. Also in this second embodiment, the process of assembling the packet 10 performed by the sending side PE1 and the sending side are performed. The packet transmission process from the PE1 to the PE-PE coupling network 2 is exactly the same as that in the first embodiment. However, in the second embodiment, the packet 10 in the receiving side PE1 is described as described with reference to FIGS. 6 and 7. The storage method is different from that of the first embodiment.

A data transfer procedure in the parallel computer system of the second embodiment will be described with reference to FIG. FIG.
However, the data holding state in the main memory 4 of each PE 1 on the transmitting side and the receiving side is shown, and a schematic display is made as the time progresses from left to right. As shown in FIG. 6, the program on the transmitting side PE1 first specifies the communication device transfer command 15 for transferring the transfer data body 17 in the command area 13 on the main memory 4, and Command area 13 as shown
In the non-command area 14 consecutive to
The transmission side control data 16 such as D is designated. The command area 13 and the non-command area 14 are combined to form a packet header 11. Then, the communication device 3 is instructed to execute the communication device transfer command 15 in the command area 13 of the packet header 11 [see the period (1) in FIG. 6 above].

In response to this, the transmission side communication device 3 reads the packet body 17 in the main memory 4 pointed by the communication device transfer command 15 as the packet body 12, and the communication device transfer command 15 and the transmission side control data 16 are read. Is added to the packet header 11 to form a packet 10 and the packet 10 is sent to the PE-to-PE coupling network 2. PE
The inter-connection network 2 follows the designation information of the receiving side PE1 included in the communication device transfer command 15 in the packet header 11,
The packet 10 is transferred to the receiving side PE1 [above, refer to period (2) in FIG. 6]. The processing up to this point is exactly the same as in the first embodiment.

In the receiving side PE1 of the second embodiment, the command area 13 (transfer command 15) of the packet header 11 is stored in the main memory 4 in addition to the message receiving queue 18.
Command receiving areas 20A and 20B for storing the individual pieces are provided. And, as will be described later in FIG. 7,
The communication device transfer command 15 of the packet header 11 is sent to the communication device 3 on the receiving side, and after processing such as command analysis is performed, the communication device transfer command 15 is sent to the command receiving area 20A or 20B according to the free state of the command receiving area 20A or 20B. Retained.

At this time, in the second embodiment, when no abnormality occurs during reception, the command area 13 of the packet header 11 is stored by overwriting in the command receiving area 20A or 20B, while when an abnormality occurs,
When the command area 13 of the packet 10 relating to the cause of the abnormality is kept held in the command receiving area 20A or 20B and the effective area for storing the new command area 13 disappears, the command receiving area 20A or 20B If the transfer command 15 is held and it becomes impossible to overwrite, the reception of the new packet 10 is stopped, and the process waits until the cause of the abnormality is eliminated.

Command area 13 of packet header 11
After the (transfer command 15) is stored in the command receiving area 20A or 20B on the main memory 4, the remaining part of the packet 10, that is, the transmission side control data 16 in the non-command area 14 and the transfer data body 17 are included. The packet body 12 and the packet body 12 are stored in a message reception queue 18 which is a cyclic queue on the main memory 4 [above,
See period (3) in FIG. 6].

Then, the program on the receiving side PE1
In the main memory 4, the receiving side control data 19 is added to the received message (the transmitting side control data 16 and the transfer data body 17) [see period (4) in FIG. 2]. This receiving side control data 19 contains the ID of the received message.
And information for pointing a message in the message reception queue 18 and the like.

Also in the second embodiment, the transmitting side P
At E1, in the command area 13 of the packet header 11, the process I as one of the information of the communication device transfer command 15 is transmitted.
While setting D, a plurality of message reception queues 18 may be provided in the main memory 4 of the receiving side PE1 for each process ID. In this case, the PE 1 on the receiving side transmits the control data 16 on the transmitting side of the packet header 11 and the packet body 1
2 (transfer data body 17) is stored in the message reception queue 18 corresponding to the process ID of the command area 13 of the packet header 11.

Here, of the configuration of the communication device 3 (reception system 3B) shown in FIG. 4, the configuration of the portion according to the second embodiment will be described in detail. The command reception area address registers 42 and 43 and the address generation circuit 44 shown in FIG. 4 store only the communication device transfer command 13 in the packet header 11 in the command reception area 20A or 20B on the main memory 4 instead of the message reception queue 18. Used when writing. At this time, the transmission side control data 15 and the transfer data body 17 are written in the message reception queue 18 based on the address value from the adder 41 described above.

Command receiving area address register 42,
Reference numerals 43 hold the start addresses of the command receiving areas 20A and 20B shown in FIG. 6, respectively. In the second embodiment, the selector 40 first sets the command The address of the receiving area address register 42 or 43 is selected and set in the address register 39.

When the command receiving area address is set in the address register 39, the selector 40 thereafter selects the address value from the address generating circuit 44 and sequentially selects it.
It operates as if set in the address register 39. At this time, the address generation circuit 44 adds the data storage byte length once to the address value set in the address register 39 each time data is written from the input buffer 38 to the main memory 4. The addition result is set in the address register 39 via the selector 40. The addition processing by the address generation circuit 44 is performed until the command area 13 (transfer command 15) of the packet header 11 is stored in the command receiving area 20A or 20B.

As a result, the transfer command 15 of the packet header 11 held in the input buffer 38 becomes a pair with the address value, and the command reception area 20A on the main memory 4 is passed through the main memory access control section 3C. Or 20
Written to B. When the writing of the transfer command 15 is completed, the selector 40 operates to select the address value from the adder 41 and the address value from the address generation circuit 44 and set them in the address register 39. The transmission side control data 16 of the packet header 11 and the packet body 1 held in the buffer 38
The transfer data body 17, which is No. 2, is stored in the main memory 4 via the main memory access control unit 3C in exactly the same manner as in the first embodiment.
It is adapted to be written in the upper message transfer queue 18.

Next, regarding the operation of the second embodiment [in particular, the operation at the time of receiving data (inter-PE coupling network 2 and receiving system 3B)], the flowchart of FIG. 7 (steps S21 to S3)
It will be described according to 8). The PE-to-PE connecting network 2 is the same as in the first embodiment, and each PE 1 is connected to the PE-to-PE connecting network 2.
The number of empty words in the input buffer 38 is always captured (step S21). Then, when there is a packet 10 destined to the predetermined PE1 (PE on the receiving side) and the input buffer 38 of the PE1 on the receiving side is empty (step S22), a packet transmission start signal is sent to the first word. Accordingly, the transfer of the packet 10 is started (step S2
3) According to the empty state of the input buffer 38 of the receiving side PE1, the entire packet 10 is transferred to the receiving side PE1 (step S24). The processing in step S24 is repeated until the transfer of one packet 10 is completed (until a YES determination is made in step S25),
When the transfer of the packet 10 is completed, the process returns to step S21.

When the packet transfer from the inter-PE coupling network 2 to the receiving side PE1 is started in steps S23 and S24, as long as the input buffer 38 is empty in the receiving system 3B in the communication device 3 of the receiving side PE1, The packet 10 is read (step S26). At this time, packet header 1
When the command code in 1 (communication device transfer command 15) flows, the transfer command 15 is read into the command register 35 (step S27).

In step S27, the command register 3
The command code read in 5 is decoded by the decoder 36, and a signal for controlling the receiving and storing method of the packet 10 is generated by the control circuit 37 (step S28). In the present embodiment, as described above with reference to FIG. 6, the communication device transfer command 15 in the command area 13 is stored in the command receiving area 20A or 20B in the main memory 4, and the transmission side control data 16 in the non-command area 14 is stored. In order to enqueue the packet body 12 including the transfer data body 17 into the message reception queue 18 in the main memory 4, the selector 40 causes the address values of the command reception area address registers 42 and 43, the address value from the adder 41, or Any of the address values from the address generation circuit 44 is appropriately selected and the address register 3
9 (steps S30 to S38 described later).

At this time, if both of the command receiving areas 20A and 20B are not empty, wait until at least one becomes empty (step S29), and if either one of the command receiving areas 20A or 20B is empty. First, the selector 40 sets the address value of the command receiving area address register 42 or 43 in the address register 39 (step S30).

The address set in the address register 39 and the transfer command 15 of the input buffer 38 are paired and sent to the main memory access control unit 3C, and the transfer command 15 is sent via the main memory access control unit 3C. 4 in the command receiving area 20A or 20B (step S31). Transfer command 1 by step S31
When the data of 5 is stored once, the address generation circuit 44 adds the data storage byte length of once to the address value of the address register 39, and the addition result is set in the address register 39 via the selector 40. (Step S32).

In the processing of steps S31 and S32, the command area 13 (transfer command 15) of the packet header 11 is entirely transferred to the command receiving area 20A on the main memory 4.
Or until stored in 20B (YES in step S33)
It is repeatedly executed until it becomes a judgment. Transfer command 1
5 is the command receiving area 20A or 2 on the main memory 4
When stored in 0B, the selector 40 sets the added value of the value of the message reception queue base address register 45 and the value of the reception pointer 46 in the address register 39, as in the first embodiment. Receive pointer 4
The value of 6 is incremented by 1 when the storage of one block of packet data in the message reception queue 18 is completed.
Is incremented by 1 (step S3
4).

The address set in the address register 39 and the packet data (transmitting side control data 16 and transfer data body 17) from the input buffer 38 are sent as a set to the main memory access control section 3C, and this main memory access control is carried out. The packet data is stored in the message reception queue 18 on the main memory 4 via the unit 3C (step S3).
5).

When the packet data is stored once in step S35, the data storage byte length is added once to the address value of the address register 39 by the address generation circuit 44, and the addition result is addressed via the selector 40. It is set in the register 39 (step S3)
6). The processing in steps S35 and S36 is performed until the packet data transfer for one block to the message reception queue 18 is completed or all the packets 10 other than the transfer command 15 are transferred to the message reception queue 18 (in step S37). It is repeatedly executed until a YES determination is made, and the above-described steps S34 to S3 are performed.
The process by 7 is until the reception of the packet 10 is completed.
That is, the packet 10 is repeatedly executed until all of the packets other than the transfer command 15 are transferred to the message reception queue 18 (until YES is determined in step S38).

According to the second embodiment of the present invention as described above, the same operation and effect as those of the first embodiment can be obtained, and in the second embodiment, the transfer command 15 is separate from the message reception queue 18. The transfer command 15 is held in the command receiving area 20A or 20B, and when the error is received, the transfer command 15 is held until the abnormality is resolved. Therefore, the transfer command 15 is read from the command receiving area 20A or 20B and the error is received. Can be dealt with immediately.

[0088]

As described above in detail, according to the data transfer method and the parallel computer processing device in the parallel computer of the present invention, the packet header and the packet body each include both the transfer command and the transmission side control data. Since the packet is transferred to the receiving side processing device, it is not necessary to copy the transfer data body on the main memory when assembling the packet in the transmitting side processing device, and one message can be transferred by one packet transfer.

Therefore, the processing amount for message transfer /
Overhead can be reduced, and it greatly contributes to improvement of performance and efficiency of such message transfer (message passing).

[Brief description of the drawings]

FIG. 1 is a block diagram showing an overall configuration of a parallel computer system as a first embodiment of the present invention.

FIG. 2 is a diagram for explaining a data transfer procedure in the parallel computer system of the first embodiment.

FIG. 3 is a diagram for explaining the contents of a packet header in this embodiment.

FIG. 4 is a block diagram showing a detailed configuration of a communication device in the PE of this embodiment.

FIG. 5 is a flowchart for explaining the operation of the first embodiment.

FIG. 6 is a diagram for explaining a data transfer procedure in the parallel computer system as the second embodiment of the present invention.

FIG. 7 is a flowchart for explaining the operation of the second embodiment.

FIG. 8 is a block diagram showing a configuration of a general parallel computer system.

FIG. 9 is a block diagram illustrating a configuration of a general parallel computer processing device.

FIG. 10 is a diagram for explaining a conventional data transfer process in a parallel computer system.

FIG. 11 is a diagram for explaining another example of conventional data transfer processing in a parallel computer system.

[Explanation of symbols]

 1 PE (processor for parallel computer) 2 PE interconnection network (communication means) 3 communication device 3A transmission system 3B reception system 3C main memory access control unit 4 main memory 10 packet 11 packet header 12 packet body 13 command area (hardware) Command area) 14 non-command area (program area) 15 communication device transfer command 16 transmission side control data 17 transfer data body 18 message reception queue (cyclic queue) 19 reception side control data 20A, 20B command reception area 21 command register 22 Decoder 23 Control Circuit 24 Address Register 25 Selector 26 Adder 27 Body Address Register 28 Address Generation Circuit 29 Packet Header Queue Base Address Register 30 Transmission Pointer 31 1 Adder 32 Transmission End Inter 33 Comparator 34 Output Buffer 35 Command Register 36 Decoder 37 Control Circuit 38 Input Buffer 39 Address Register 40 Selector 41 Adder 42, 43 Command Reception Area Address Register 44 Address Generation Circuit 45 Message Reception Queue Base Address Register 46 Reception Pointer 47 1 Adder 48 Reception start pointer 49 Comparator

Claims (8)

[Claims] 1. A data transfer method in a parallel computer constituted by connecting a plurality of processing devices so that they can communicate with each other via a communication means, wherein a transmission side processing device transfers a packet header including various control information and transfers. A packet composed of a packet body including a data body is transmitted to the communication means, and the communication means transfers the packet to a predetermined reception side processing device, thereby storing the main memory of the transmission side processing device. A data transfer method for transferring the data in the main memory of the receiving side processing device, the packet header created in the main memory of the transmitting side processing device, and a command area for a command for instructing data transfer, It is composed of a non-command area for transferring data specified by the program, and sender-side control data is set in the non-command area of the packet header. Data transfer method in characterized, parallel computer to. 2. The reception side processing device, when receiving the packet, stores both the packet header and the packet body in a message reception queue on the main memory. Data Transfer Method for Parallel Computers in Japan. 3. The receiving side processing device, when receiving the packet, stores the non-command area of the packet header and the packet body in a message reception queue on the main memory. 1. A data transfer method in the parallel computer according to 1. 4. A command area of the packet header,
4. The data transfer method in a parallel computer according to claim 3, wherein the data is stored in a command receiving area on the main memory. 5. The command receiving area is configured to be able to store a plurality of command areas, and when no abnormality occurs during reception, the command area of the packet header is stored by overwriting the command receiving area. When an abnormality occurs, the command area of the packet related to the cause of the abnormality is held in the command receiving area, and when the command receiving area has no effective area for storing a new command area, a new area is created. The data transfer method in a parallel computer according to claim 4, wherein reception of packets is stopped. 6. The transmission side processing device sets a process identifier in a command area of the packet header, and a message reception queue is provided for each process identifier in the main memory of the reception side processing device. 3. The data in the parallel computer according to claim 2, wherein the side processing device stores both the packet header and the packet body in a message reception queue corresponding to a process identifier of a command area of the packet header. Transfer method. 7. The transmission side processing device sets a process identifier in the command area of the packet header, and a message reception queue is provided for each process identifier in the main memory of the reception side processing device. 6. The side processing device stores the non-command area of the packet header and the packet body in a message reception queue corresponding to a process identifier of the command area of the packet header. A data transfer method in a parallel computer according to any one of 1. 8. A processing device constituting a parallel computer, which is communicably connected to another processing device via a communication means, wherein a packet header including various control information and a transfer are transmitted when the data is transmitted to the other processing device. In a parallel computer processing device that transmits a packet composed of a packet body including a data body to the communication means, the packet header has a command area for a command for instructing data transfer, and data specified by a program. And a non-command area for transferring a packet, and transmission side control data is set in the non-command area of the packet header.