JPH09107313A - Amplitude equalization circuit, clock extract circuit and optical reception circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an amplitude equalization circuit capable of receiving data even without a preamble and without the need for a high speed response by inputting only data whose amplitude is constant to each amplitude equalization circuit. SOLUTION: Input data consisting of burst signals with different amplitude in time sharing multiplex are given to a bottom level detection circuit 1d and SW circuits 1a, 1b, 1c of a data demultiplex circuit section 1. The circuit section 1a is controlled by a control signal (a) corresponding to a time slot of a terminal equipment #1 to select input data only for a time slot of the terminal equipment #1, to give the selected data to an amplitude equalization circuit 2a, and to select an output of the circuit 1d in other cases and to input the selected data to the circuit 2a. The circuits 1b, 1c are controlled by signals b, c corresponding to the time slot of terminal equipments #2, #3, the input data to select the input data only at the time slot of the terminal equipments #2, #3, to provide the selected data to amplitude equalization circuit sections 2b, 2c and to select an output of the circuit 1d in other cases and to provide the selected data to the circuits 2b, 2c. An output of the circuit 1a (1b, 1c) is given respectively to the circuit 2a (2b, 2c), in which the amplitude is equalized.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention performs time division multiplexing communication by an optical communication network in which one station device and a plurality of terminal devices are connected by an optical fiber and an optical distributor, and a predetermined time. The present invention relates to an amplitude equalization circuit, a clock extraction circuit, and an optical reception circuit of an optical reception device provided in the station device in an optical communication system in which an optical burst signal from each terminal device is accommodated in a slot.

[0002]

2. Description of the Related Art FIG. 10 is a diagram showing one system example of an optical communication network to which the present invention is applied. This is one station device
24 and a plurality (three in the example in the figure) of each terminal device 25a, 25b, 25c are connected by optical fiber 26a, 26b, 26c, 26d and an optical distributor 27 by an optical communication network for time division multiplexing communication. Each terminal device 25
It is an optical communication system that accommodates optical burst signals from a, 25b, and 25c. In this optical communication system, since the distance between the optical distributor 27 and each of the terminal devices 25a, 25b, 25c is different, each of the terminal devices 25a, 25b, received by the station device 24,
The burst data sequence from 25c has different amplitude and phase.

FIG. 11 is a block diagram showing a configuration of a conventional optical receiving circuit in the station device shown in FIG. This is because the incident light (burst data string) from the optical fiber 26d performs photoelectric conversion in the light receiving element 19, and the photocurrent obtained by the light receiving element 19 in the preamplifier 20, as shown in FIG. 12, for example. It is converted to the voltage of # 1, # 2, and # 3 and amplified. Then, the amplitude equalizing circuit 21 makes the amplitude of the output signal of the preamplifier 20 constant and outputs it to the clock extracting circuit 22 and the data reproducing circuit 23. The clock extraction circuit 22 reproduces the output clock 22C based on the output signal having a constant amplitude, and the data reproduction circuit 23 uses the reproduced output clock 22C as the output signal of the amplitude equalization circuit 21 as the output data 23D. Output.

As described above, in the above conventional optical receiving circuit, the amplitude of the output signal of the preamplifier 20 is always made constant by the amplitude equalizing circuit 21, so that even if the optical receiving level changes, the output data 23D and the output clock are changed. 22C playback is possible.

[0005]

However, the above-mentioned diagram
When the conventional optical receiver circuit shown in 11 is used, the amplitude equalization circuit
21 and the clock extraction circuit 22 must perform amplitude equalization and clock extraction for each burst data, and a bit called a preamble is required at the beginning of each burst signal. Since this preamble lowers the transmission efficiency, a high-speed response of the amplitude equalization circuit 21 causes a decrease in homo-code continuity proof strength, and a high-speed response of the clock extraction circuit 22 causes an increase in jitter and a decrease in homo-code continuity proof strength. There was a problem.

The present invention solves such a conventional problem, and it is a first object of the present invention to provide an amplitude equalization circuit capable of eliminating a preamble without requiring high-speed response.

A second object is to provide a clock extraction circuit which can eliminate the preamble without requiring high speed response.

A third object is to provide an optical receiving circuit having a high transmission efficiency without requiring a preamble by combining an amplitude equalizing circuit and a clock extracting circuit.

[0009]

In order to achieve the first object of the present invention, the first means of the amplitude equalization circuit in the station device is that the burst data from each of the plurality of terminal devices is time-divided. A data separation circuit unit that separates the received data sequence of the multiplexed signal for each data from each of the plurality of terminal devices,
Amplitude equalization circuit section composed of a plurality of amplitude equalization circuits for equalizing amplitude of each data separated by the data separation circuit section, and amplitude equalization circuit individually by the amplitude equalization circuit of the amplitude equalization circuit section. And a data multiplexing circuit section for inputting a plurality of signals and again time-division-multiplexing the separated data.

The second means of the amplitude equalization circuit separates a received data string of a signal in which burst data from a plurality of terminal devices are time-division multiplexed, for each data from a plurality of terminal devices. A peak level detecting circuit section comprising a data separating circuit section, a plurality of peak level detecting circuits detecting a peak level for each data separated by the data separating circuit section, and a peak level detecting circuit of the peak level detecting circuit section. A peak level selection circuit unit that outputs the peak level detected for each data of a plurality of terminal devices in the order of time slots, and outputs the peak level of the immediately preceding time slot when there is no data, and the peak level selection circuit unit. Intermediate level generation for generating an intermediate level between the output of the output signal and the output of the bottom level detection circuit in the data separation circuit section. And a circuit, the output of the intermediate level generating circuit and a threshold, and having a limiter amplifier for amplifying the received data sequence.

Further, the clock extraction circuit separates a received data string of a signal in which burst data from each of the plurality of terminal devices are time-division-multiplexed for each data from each of the plurality of terminal devices, A clock extraction circuit unit including a plurality of clock extraction circuits for extracting a clock for each data separated by the data separation circuit unit, and a plurality of clocks extracted by the clock extraction circuit of the clock extraction circuit unit are input, And a clock multiplexing circuit unit that time-division-multiplexes the extracted clock for each terminal device.

Further, the optical receiving circuit includes a light receiving element for performing optical / electrical conversion of a received data string of a signal in which burst data from a plurality of terminal devices are time-division multiplexed, and a photocurrent obtained by the light receiving element. To a voltage, a data amplifier circuit that separates the received data string for each data from a plurality of terminal devices, and a plurality of amplitudes that are used for each data separated by the data separator circuit unit. An amplitude equalization circuit unit including an equalization circuit, a plurality of signals that have been amplitude equalized by the amplitude equalization circuit of the amplitude equalization circuit unit are input, and the data separated for each terminal device is time-division multiplexed again. An amplitude equalization circuit including a data multiplexing circuit unit, a clock extraction circuit unit including a plurality of clock extraction circuits connected to the plurality of amplitude equalization circuits, and the clock extraction circuit unit A clock multiplexing circuit unit that inputs a plurality of clocks extracted by the clock extraction circuit and time-division-multiplexes the clocks extracted for each of the plurality of terminal devices; and the amplitude and the like based on the clock from the clock multiplexing circuit unit. And a data reproducing circuit for reproducing the output data from the digitizing circuit section.

[0013]

Therefore, according to the amplitude equalization circuit of the present invention,
Utilizing the fact that the time slots of the time-division-multiplexed data are known in advance, the input data from each of the plurality of terminal devices are input to the individual amplitude equalization circuits, and the amplitudes are input to the respective amplitude equalization circuits. Since only constant data is input, there is no need to perform amplitude equalization for each burst data,
Time division multiple access (TDMA) data having different amplitudes can be amplitude-equalized with good transmission efficiency without requiring a high-speed response and without a preamble.

According to the clock extraction circuit of the present invention, the input data from each of the plurality of terminal devices are sent to different clock extraction circuits for each data, and only the data whose phase is constant is supplied to each clock extraction circuit. Since it is input, it is not necessary to extract the clock for each burst data, and the TDMA data having different phases can be extracted with good transmission efficiency without requiring a high-speed response and without a preamble.

According to the optical receiving circuit of the present invention, by combining the above-described amplitude equalizing circuit and the clock extracting circuit, TDMA data having different amplitudes and phases is transmitted without requiring a high-speed response and without a preamble. You can receive efficiently.

[0016]

1 is a block diagram showing the configuration of an amplitude equalizing circuit according to a first embodiment of the present invention. This is illustrated for the case where the number of terminal devices 25 is three, as in FIG. 10 of the conventional example. In FIG. 1, reference numeral 1 denotes a data separation circuit unit that separates a received data string for each data from each terminal device. The data separation circuit unit 1 includes a bottom level detection circuit 1d that detects a bottom level of the received data string. , A plurality of switch (SW) circuits which are controlled by a plurality of control signals a, b, c which output an H level only during the time slot of each terminal device and which switch the output of the bottom level detection circuit 1d and the received data string as an input It is composed of 1a, 1b and 1c.

Reference numeral 2 denotes a plurality of amplitude equalization circuits 2 used for each data separated by the data separation circuit unit 1.
It is an amplitude equalization circuit unit having a, 2b, and 2c. Reference numeral 3 denotes a data multiplex circuit unit for inputting a plurality of signals whose amplitudes have been equalized, and again time-division multiplexes the separated data. The data multiplex circuit unit 3 includes the plurality of control signals a, b, c and a plurality of switch (SW) circuits 3a, 3b, 3 which are opened / closed by another control signal d corresponding to NOR
It is composed of c and 3d. These data separation circuit units 1,
The amplitude equalization circuit section 2 and the data multiplexing circuit section 3 constitute an amplitude equalization circuit 4.

Next, the operation of the amplitude equalization circuit 4 in the first embodiment will be described with reference to the time charts of FIGS. The input data (received data string) in which burst signals with different amplitudes shown in FIG. 2 (1) are time-division multiplexed is input to the bottom level detection circuit 1d and the SW circuits 1a, 1b, 1c of the data separation circuit unit 1. It The bottom level detection circuit 1d detects the bottom level of the input data and inputs the detection output shown in FIG. 2 (2) to the SW circuits 1a, 1b, 1c. SW
The circuit 1a is controlled by the control signal a shown in FIG. 2 (3) corresponding to the time slot of the terminal device # 1,
Input data is selected and input to the amplitude equalization circuit 2a of the amplitude equalization circuit unit 2 only during the time slot of, and at other times, the output of the bottom level detection circuit 1d is selected and input to the amplitude equalization circuit 2a. To do. The SW circuits 1b and 1c are terminal devices #
The terminal devices # 2 and # 3 are controlled by the control signals b and c shown in FIGS. 2 (4) and (5) corresponding to the time slots # 2 and # 3.
Input data is selected and input to the amplitude equalization circuits 2b and 2c of the amplitude equalization circuit unit 2 only during the time slot of the other time slot. In other cases, the output of the bottom level detection circuit 1d is selected and the amplitude equalization circuit 2b is selected. , 2c. By this, each SW
The outputs of the circuits 1a, 1b, 1c are obtained by separating the received data string for each data of each terminal device # 1, # 2, # 3, as shown in FIGS. 2 (6), (7), (8). become. SW circuits 1a, 1b,
The output of 1c is input to the amplitude equalization circuits 2a, 2b, 2c, respectively, and the amplitude is equalized. FIG. 3 shows an output time chart of the output data of the amplitude equalization circuits 2a, 2b and 2c.

Each amplitude equalizing circuit 2 shown in FIGS. 3 (1), (2) and (3)
The outputs of a, 2b and 2c are input to the data multiplexing circuit unit 3. The SW circuit 3a of the data multiplexing circuit unit 3 is the terminal device # 1.
Control signal a shown in FIG. 3 (4) corresponding to the time slot of
The output of the amplitude equalization circuit 2a is short-circuited only during the time slot of the terminal device # 1 and is used as the output data of the amplitude equalization circuit 4. Similarly, the SW circuits 3b and 3c are controlled by the control signals b and c shown in FIGS. 3 (5) and 3 (6) corresponding to the time slots of the terminal devices # 2 and # 3, respectively.
Amplitude equalization circuit 2 short-circuited only during time slot # 3
The outputs of b and 2c are output data of the amplitude equalization circuit 4.

Further, the SW circuit 3d controls the control signals a, b, c.
Is controlled by the control signal d shown in FIG. 3 (7) corresponding to the NOR of, and the output of the amplitude equalization circuit 2c is used as the output data of the amplitude equalization circuit 2 which is short-circuited when there is no input data. That is, as shown in the time chart of the output data of FIG. 3, the circuit of FIG. 1 operates as an amplitude equalization circuit, and the output data has a constant amplitude of the input data as shown in FIG. 3 (8). It becomes a thing.

As described above, according to the first embodiment,
Input data from each of the terminal devices # 1, # 2, # 3 is sent to the individual amplitude equalization circuits 2a, 2b, 2c, and the amplitudes of the amplitude equalization circuits 2a, 2b, 2c are constant. Since only data is input, amplitude equalization does not have to be performed for each burst data, high-speed response is not required, and a preamble that reduces transmission efficiency is not required.

FIG. 4 is a block diagram showing the configuration of the amplitude equalization circuit according to the second embodiment of the present invention. This also exemplifies the case where there are three terminal devices. In FIG.
The blocks having the same functions as those in the first embodiment (FIG. 1) are designated by the same reference numerals, and the description thereof will be omitted. Here, the point different from the configuration of FIG. 1 is that instead of the data multiplexing circuit section 3, there is an OR circuit 5 for inputting a plurality of signals whose amplitudes have been equalized by the amplitude equalization circuit section 2.

Next, the operation of the amplitude equalization circuit in the second embodiment will be described with reference to the time chart of FIG. The operations of the data separation circuit unit 1 and the amplitude equalization circuit unit 2 are the same as in the case of the above-mentioned first embodiment, and therefore their explanations are omitted. Here, the amplitude equalization circuits 2a, 2b, and 2c of FIG.
The outputs shown in (2) and (3) are input to the OR circuit 5, and the output becomes the output data of the amplitude equalization circuit 6 (FIG. 5 (4)). That is, as shown in the output time chart of the amplitude equalization circuits 2a, 2b, 2c and the output data time chart in FIG.
The circuit of FIG. 4 operates as an amplitude equalization circuit, and the output data has a constant amplitude of the input data as shown in FIG. 5 (4).

As described above, according to the second embodiment,
Similar to the first embodiment, each terminal device # 1, # 2, # 3
The input data from the individual amplitude equalization circuits 2a, 2a,
2b, 2c, and only the data having a constant amplitude is input to the amplitude equalization circuits 2a, 2b, 2c, so that it is not necessary to perform amplitude equalization for each burst data, and high speed response is required. And does not require a preamble that reduces transmission efficiency. Further, in the second embodiment, the first
The control system used in this embodiment is not required and the control system is simplified.

FIG. 6 is a block diagram showing the structure of an amplitude equalizing circuit according to the third embodiment of the present invention. This also exemplifies the case where there are three terminal devices. In FIG.
The blocks having the same functions as those in the first embodiment (FIG. 1) are designated by the same reference numerals, and the description thereof will be omitted. Here, 7 is a plurality of peak level detection circuits 7a for detecting the peak level of each data separated by the data separation circuit unit 1,
A peak level detection circuit unit having 7b and 7c, 8 is a peak level selection for inputting a plurality of peak levels detected by the peak level detection circuits 7a, 7b and 7c and selecting a peak level of data according to a time slot. It is a circuit part. The peak level selection circuit unit 8 includes a plurality of switch (SW) circuits 8 which are opened / closed by a plurality of control signals a, b, c and another control signal d corresponding to their NOR.
It is composed of a, 8b, 8c and 8d. Reference numeral 9 is an intermediate level generation circuit that generates an intermediate level between the output of the peak level selection circuit unit 8 and the output of the bottom level detection circuit 1d in the data separation circuit unit 1, and 10 is the output of the intermediate level generation circuit 9 as a threshold value. It is a limiter amplifier that amplifies input data.

The operation of the amplitude equalization circuit according to the third embodiment will be described with reference to the time chart of FIG.
The operation of the data separation circuit unit 1 is the same as that of the first embodiment, so its explanation is omitted. SW circuits 1a, 1b, 1
The outputs of c are input to the peak level detection circuits 7a, 7b and 7c of the peak level detection circuit unit 7, respectively, and are output as shown in FIG.
Their peak levels are detected as shown in (2) and (3). The outputs of the peak level detection circuits 7a, 7b, 7c are input to the peak level selection circuit unit 8. The SW circuit 8a of the peak level selection circuit unit 8 is controlled by the control signal a corresponding to the time slot of the terminal device # 1,
The output of the peak level detection circuit 7a, that is, the output of the peak level selection circuit unit 8 (SW circuit 8a) shown in FIG.
To enter.

Similarly, the SW circuits 8b and 8c are connected to the terminal device # 2.
It is controlled by the control signals b and c corresponding to the # 3 time slot, short-circuited only during the time slots of the terminal devices # 2 and # 3, and the outputs of the peak level detection circuits 7b and 7c, that is, shown in FIG. 7 (4). The output of the peak level selection circuit unit 8 (SW circuits 8b, 8c) is input to the intermediate level generation circuit 9. S
The W circuit 8d is controlled by the control signal d corresponding to the NOR of the control signals a, b, and c, and is short-circuited when there is no input data to input the output of the peak level detection circuit 7c to the intermediate level generation circuit 9.

The output signal shown in FIG. 7 (4) of the peak level selection circuit section 8 and the output signal of the bottom level detection circuit 1d shown in FIG. 7 (5) are input to the intermediate level generation circuit 9, and their intermediate levels are output. Is generated and output (FIG. 7 (6)). The output shown in FIG. 7 (6) of the intermediate level generation circuit 9 is input to the limiter amplifier 10 as a threshold value, the limiter amplifier 10 amplifies the input data, and the output thereof is output from the amplitude equalization circuit 11 (see FIG. Output as 7 (7)). That is, as shown in FIG. 7, the circuit of FIG. 6 operates as an amplitude equalization circuit,
The output data has the same amplitude as the input data as shown in FIG. 7 (7).

As described above, according to the third embodiment,
The input data from each of the terminal devices # 1, # 2, # 3 is sent to the individual peak level detection circuits 7a, 7b, 7c, and the amplitude is constant in each of the peak level detection circuits 7a, 7b, 7c. Since only the data is input, it is not necessary to detect the peak level for each burst data, and the input threshold value of the limiter amplifier 10 can be given before the burst data is input. In addition, the preamble that reduces the transmission efficiency is not required.

FIG. 8 is a block diagram showing the configuration of a clock extraction circuit according to the fourth embodiment of the present invention. This also exemplifies the case where there are three terminal devices. In FIG. 8, reference numeral 12 denotes a data separation circuit unit that separates the received data string for each data from each terminal device. The data separation circuit unit 12 includes a bottom level detection circuit 12d that detects the bottom level of the received data string. , A plurality of switch (SW) circuits 12a, 12 controlled by a plurality of control signals a, b, c corresponding to the time slots of the respective terminal devices and switching the output of the bottom level detection circuit 12d and the received data string as an input.
It consists of b and 12c.

Reference numeral 13 denotes a plurality of clock extraction circuits used for each data separated by the data separation circuit unit 12.
It is a clock extraction circuit unit having 13a, 13b, 13c. 14
Is a clock multiplexing circuit unit for inputting a plurality of extracted clocks and time-division-multiplexing the extracted clocks for each terminal device. The clock multiplexing circuit unit 14 includes a plurality of control signals a, b, c and a plurality of switches opened and closed by another control signal d corresponding to their NOR
(SW) circuit 14a, 14b, 14c, 14d.

Next, the operation of the clock extraction circuit in the fourth embodiment will be described. The received data sequence in which the burst signals having different phases are time-division multiplexed is the bottom level detection circuit 12d and the SW circuits 12a, 12 of the data separation circuit unit 12.
Input to b and 12c. The bottom level detection circuit 12d detects the bottom level of the input data and outputs its output to the SW circuit 12
Input in a, 12b, and 12c. The SW circuit 12a is controlled by the control signal a corresponding to the time slot of the terminal device # 1,
Input data is selected and input to the clock extraction circuit 13a of the clock extraction circuit unit 13 only during the time slot of the terminal # 1, otherwise, the output of the bottom level detection circuit 12d is selected and input to the clock extraction circuit 13a. To do.

Similarly, the SW circuits 12b and 12c are connected to the terminal device # 2.
Controlled by the control signals b and c corresponding to the time slot # 3, the input data is selected and input to the clock extraction circuits 13b and 13c only during the time slots of the terminal devices # 2 and # 3, and otherwise, The output of the bottom level detection circuit 12d is selected and input to the clock extraction circuits 13b and 13c. As a result, the outputs of the SW circuits 12a, 12b, 12c are obtained by separating the input data string for each data of the individual terminal devices # 1, # 2, # 3.

The outputs of the SW circuits 12a, 12b, 12c are input to the clock extraction circuits 13a, 13b, 13c, respectively, and the clocks are extracted. The clocks extracted by the clock extraction circuits 13a, 13b, 13c are input to the clock multiplexing circuit unit 14. The SW circuit 14a of the clock multiplexing circuit unit 14 is the terminal device #
A clock controlled by a control signal a corresponding to one time slot, short-circuited only in the time slot of terminal # 1 and extracted by the clock extraction circuit 13a is used as an output clock of the clock extraction circuit 15.

Similarly, the SW circuits 14b and 14c are the terminal devices # 2 and # 2, respectively.
The clocks controlled by the control signals b and c corresponding to the time slot # 3, short-circuited only in the time slots of the terminal devices # 2 and # 3 and extracted by the clock extraction circuits 13b and 13c, are output clocks of the clock extraction circuit 15. And The SW circuit 14d is controlled by the control signal d corresponding to the NOR of the control signals a, b, c, and is short-circuited when there is no input data, and the clock extracted by the clock extraction circuit 13c is used as the output clock of the clock extraction circuit 15. .

As described above, according to the fourth embodiment,
The input data from each terminal device # 1, # 2, # 3 is sent to the respective clock extraction circuits 13a, 13b, 13c, and only the data having a constant phase is supplied to each clock extraction circuit 13a, 13b, 13c. Since it is input, it is not necessary to perform clock extraction for each burst data, and high speed response is not required. In addition, the preamble that reduces the transmission efficiency is not required.

FIG. 9 is a block diagram showing the arrangement of an optical receiving circuit according to the fifth embodiment of the present invention. This also exemplifies the case where there are three terminal devices. In FIG. 9, 16
Is a light receiving element that performs optical-electrical conversion, 17 is a preamplifier that converts the photocurrent obtained by the light receiving element 16 into a voltage and amplifies it.
4 is the amplitude equalization circuit in the first embodiment (FIG. 1) of the present invention, and 13 is the amplitude equalization circuits 2a, 2b, 2 in the amplitude equalization circuit 4.
A clock extraction circuit unit 14 having a plurality of clock extraction circuits 13a, 13b, 13c used for each output data of c,
It is a clock multiplexing circuit unit that inputs a plurality of extracted clocks and time-division-multiplexes the extracted clocks for each terminal device. Reference numeral 18 denotes a data reproduction circuit which receives the output data of the amplitude equalization circuit 4 and the output clock of the clock multiplexing circuit unit 14 to reproduce the data. The clock extraction circuit unit 13 and the clock multiplexing circuit unit 14 are provided in the fourth embodiment (FIG. 8).
The configuration is the same as the case.

Next, the operation of the optical receiver circuit in the fifth embodiment will be described. Incident light in which burst signals of different levels are time-division-multiplexed is input to the light receiving element 16 and is optically / electrically converted. The photocurrent obtained by the light receiving element 16 is converted into a voltage by the preamplifier 17 and amplified. The output of the preamplifier 17 is input to the amplitude equalization circuit 4 and amplitude equalized. The operation of the amplitude equalization circuit 4 is similar to that of the first embodiment (FIG. 1). The output data of the amplitude equalization circuits 2a, 2b, 2c in the amplitude equalization circuit 4 is the data multiplexing circuit unit 3
Is input to the clock extraction circuit 13a, 13b, 13c of the clock extraction circuit unit 13, and the respective clocks are extracted. The operations of the clock extraction circuit unit 13 and the clock multiplexing circuit unit 14 are the same as in the case of the fourth embodiment (FIG. 8), and the output of the clock multiplexing circuit unit 14 becomes the output clock of the optical receiving circuit. The output clock from the clock multiplexing circuit unit 14 and the output data of the amplitude equalization circuit 4 are input to the data reproduction circuit 18, and the data is reproduced and output.

As described above, according to the fifth embodiment,
Input data from each of the terminal devices # 1, # 2, # 3 is sent to the individual amplitude equalization circuits 2a, 2b, 2c and the clock extraction circuits 13a, 13b, 13c, and the respective amplitude equalization circuits 2a, 2b, 2c
Since only the data with the same amplitude and phase are input to each clock extraction circuit 13a, 13b, 13c, it is not necessary to perform amplitude equalization and clock extraction for each burst data, and high speed response is not required. Also, it does not require a preamble that reduces transmission efficiency.

[0040]

As described above, according to the present invention, the input data from each terminal device is sent to each individual amplitude equalization circuit, and only the data whose amplitude is constant is input to each amplitude equalization circuit. Therefore, it is not necessary to perform amplitude equalization for each burst data, and it is possible to configure an amplitude equalization circuit that can receive TDMA data having different amplitudes without a high-speed response and without a preamble.

The input data from each terminal device is
Since each data is sent to an individual clock extraction circuit, and only the data having a constant phase is input to each clock extraction circuit, it is not necessary to extract the clock for each burst data, and the TDMA data having the different phases can be transmitted at high speed. A clock extraction circuit that can be received without a preamble without requiring responsiveness can be configured.

Furthermore, by combining the amplitude equalizing circuit and the clock extracting circuit, it is possible to construct an optical receiving circuit having a high transmission efficiency without requiring a preamble at all.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an amplitude equalization circuit according to a first exemplary embodiment of the present invention.

FIG. 2 is an output time chart of the bottom level detection circuit 1d and SW circuits 1a, 1b, 1c for the input data string of FIG.

FIG. 3 is a time chart of outputs and output data strings of the amplitude equalization circuits 2a, 2b, 2c of FIG.

FIG. 4 is a block diagram showing a configuration of an amplitude equalization circuit according to a second exemplary embodiment of the present invention.

5A and 5B are output time charts and output data string time charts of the amplitude equalization circuits 2a, 2b, and 2c in FIG.

FIG. 6 is a block diagram showing a configuration of an amplitude equalization circuit according to a third exemplary embodiment of the present invention.

7 is a diagram illustrating peak level detection circuits 7a, 7b and 7c, a peak level selection circuit unit 8 and a bottom level detection circuit 1d in FIG.
3 is an output time chart of the intermediate level generation circuit 9 and a time chart of an output data string.

FIG. 8 is a block diagram showing a configuration of a clock extraction circuit according to a fourth embodiment of the present invention.

FIG. 9 is a block diagram showing a configuration of an optical receiver circuit according to a fifth embodiment of the present invention.

FIG. 10 is one of optical communication networks to which the present invention is applied.
FIG.

11 is a block diagram showing a configuration of a conventional optical receiving circuit in the station device shown in FIG.

FIG. 12 is a diagram showing an example of a data string input to the optical receiving circuit of FIG.

[Explanation of symbols]

1, 12 ... Data separation circuit unit, 1a, 1b, 1c, 3a, 3
b, 3c, 3d, 8a, 8b, 8c, 8d, 12a, 12b, 12c, 14
a, 14b, 14c, 14d ... SW circuit, 1d ... Bottom level detection circuit, 2 ... Amplitude equalization circuit section, 2a, 2b, 2c ... Amplitude equalization circuit, 3 ... Data multiplexing circuit section, 4, 6, 11 ...
Amplitude equalization circuit, 5 ... OR circuit, 7 ... Peak level detection circuit section, 7a, 7b, 7c ... Peak level detection circuit,
8 ... Peak level selection circuit section, 9 ... Intermediate level generation circuit, 10 ... Limiter amplifier, 13 ... Clock extraction circuit section, 13a, 13b, 13c ... Clock extraction circuit, 14 ... Clock multiplex circuit section, 15 ... Clock extraction circuit, 16 ... Light receiving element, 17 ... Preamplifier, 18 ... Data reproducing circuit.

Claims (10)

[Claims] 1. A data separation circuit unit for separating a received data sequence of a signal in which burst data from a plurality of terminal devices are time-division multiplexed, for each data from a plurality of terminal devices, and the data separation circuit unit. Inputs a plurality of signals that have been individually amplitude-equalized by the amplitude equalization circuit section, which includes a plurality of amplitude equalization circuits that perform amplitude equalization for each data separated by And a data multiplexing circuit section for time-division multiplexing the separated data again. 2. The data separation circuit unit is controlled by a bottom level detection circuit for detecting a bottom level of a received data string and a plurality of control signals for outputting an H level only during time slots of a plurality of terminal devices. An output of the bottom level detection circuit and a plurality of switch circuits for switching a received data string as an input, and the data multiplexing circuit unit is connected between each amplitude equalization circuit and an output terminal in the amplitude equalization circuit unit. A plurality of switch circuits that are opened and closed by any of the plurality of control signals, and are connected between any one of the amplitude equalization circuits in the amplitude equalization circuit unit and the output terminal, and 2. A switch circuit which is opened / closed by another control signal corresponding to NOR of a plurality of control signals. Amplitude equalization circuit. 3. The data multiplexing circuit section is configured by an OR circuit so that another control signal corresponding to NOR of a plurality of control signals outputting H level only during the time slot of each terminal device is not required. The amplitude equalization circuit according to claim 2, wherein 4. A data separation circuit section for separating a received data sequence of a signal in which burst data from a plurality of terminal apparatuses are time-division multiplexed, for each data from a plurality of terminal apparatuses, and the data separation circuit section. The peak level detection circuit unit composed of a plurality of peak level detection circuits for detecting the peak level for each data separated by, and the peak level detection circuit of the peak level detection circuit unit detects the data for each of the plurality of terminal devices. Output peak level in the order of time slots, and when there is no data, the peak level selection circuit section that outputs the peak level of the immediately preceding time slot, the output of the peak level selection circuit section and the bottom level in the data separation circuit section. An intermediate level generation circuit for generating an intermediate level with the output of the detection circuit; An amplitude equalizing circuit, comprising: a limiter amplifier that amplifies the received data string using an output as a threshold value. 5. The data separation circuit unit is controlled by a bottom level detection circuit that detects a bottom level of a received data string and a plurality of control signals that output an H level only during time slots of a plurality of terminal devices. The output of the bottom level detection circuit and a plurality of switch circuits that switch the received data string as an input, and the peak level selection circuit section is provided between each peak level detection circuit and an output terminal in the peak level detection circuit section. A plurality of switch circuits connected and opened / closed by any of the plurality of control signals; and a plurality of control signals connected between any one of the individual peak level detection circuits and the output terminal. And a switch circuit opened / closed by another control signal corresponding to NOR. The amplitude equalization circuit according to claim 4, 6. A bottom level detection circuit for detecting a bottom level of a received data string used in the intermediate level generation circuit, and a bottom level detection circuit for detecting a bottom level of a received data string used in the data separation circuit section. The amplitude equalization circuit according to claim 5, wherein 7. A data separation circuit unit for separating a received data sequence of a signal in which burst data from a plurality of terminal devices are time-division multiplexed, for each data from a plurality of terminal devices, and the data separation circuit unit. A clock extraction circuit unit composed of a plurality of clock extraction circuits for extracting clocks for each data separated by, and a plurality of clocks extracted by the clock extraction circuit of the clock extraction circuit unit are input, and each of a plurality of terminal devices And a clock multiplexing circuit unit for time-division multiplexing the extracted clock. 8. The data separation circuit unit is controlled by a bottom level detection circuit for detecting a bottom level of a received data string and a plurality of control signals for outputting an H level only during a time slot of each of a plurality of terminal devices. An output of the bottom level detection circuit and a plurality of switch circuits for switching a received data string as an input are configured, and the clock multiplexing circuit unit is connected between each clock extraction circuit and an output terminal in the clock extraction circuit unit. A plurality of switch circuits that are opened and closed by any of a plurality of control signals, and are connected between any one of the individual clock extraction circuits and an output terminal, and correspond to NOR of the plurality of control signals. 8. The black circuit according to claim 7, wherein the switch circuit is opened and closed by one control signal. Circuit extraction circuit. 9. A light receiving element for performing optical-electrical conversion on a received data sequence of a signal in which burst data from a plurality of terminal devices are time-division multiplexed, and a photocurrent obtained by the light receiving element is converted into a voltage. It includes a preamplifier for amplifying, a data separation circuit unit that separates the received data string for each data from a plurality of terminal devices, and a plurality of amplitude equalization circuits used for each data separated by the data separation circuit unit. Amplitude equalization circuit section, a data multiplexing circuit section for inputting a plurality of signals amplitude-equalized by the amplitude equalization circuit of the amplitude equalization circuit section, and again time-division-multiplexing the data separated for each terminal device And a clock extraction circuit section including a plurality of clock extraction circuits connected to the plurality of amplitude equalization circuits, and a clock extraction circuit of the clock extraction circuit section. Therefore, a plurality of clocks extracted are input, and a clock multiplex circuit unit that time-division multiplexes the clocks extracted for each of the plurality of terminal devices, and the amplitude equalization circuit unit based on the clocks from the clock multiplex circuit unit And a data reproducing circuit for reproducing output data from the optical receiving circuit. 10. The bottom level detection circuit for detecting the bottom level of the received data sequence, wherein the data separation circuit section includes:
The data multiplexing is composed of a plurality of switch circuits which are controlled by a plurality of control signals which output an H level only between time slots of a plurality of terminal devices and which switch the output of the bottom level detection circuit and the received data string as an input. The circuit section includes a plurality of switch circuits which are connected between the individual amplitude equalization circuits in the amplitude equalization circuit section and output terminals and which are opened and closed by any of the plurality of control signals, and the individual amplitude equalization circuits. And a switch circuit connected between any one of the amplitude equalization circuits and an output terminal and opened and closed by another control signal corresponding to the NOR of the plurality of control signals. A plurality of switch circuits connected between the individual clock extraction circuits and the output terminals and opened and closed by any of the plurality of control signals; And a switch circuit connected between any one of the clock extraction circuits and the output terminal and opened and closed by another control signal corresponding to NOR of the plurality of control signals. Item 9. The optical receiving circuit according to Item 9.