JPH09103077A - Power-factor control circuit - Google Patents

Power-factor control circuit

Info

Publication number
JPH09103077A
JPH09103077A JP7282615A JP28261595A JPH09103077A JP H09103077 A JPH09103077 A JP H09103077A JP 7282615 A JP7282615 A JP 7282615A JP 28261595 A JP28261595 A JP 28261595A JP H09103077 A JPH09103077 A JP H09103077A
Authority
JP
Japan
Prior art keywords
signal
circuit
input
output
pulse
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP7282615A
Other languages
Japanese (ja)
Other versions
JP3215613B2 (en
Inventor
Tomohiko Sakamoto
智彦 坂本
Hiroaki Inoue
裕章 井上
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Furukawa Battery Co Ltd
Original Assignee
Furukawa Battery Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Furukawa Battery Co Ltd filed Critical Furukawa Battery Co Ltd
Priority to JP28261595A priority Critical patent/JP3215613B2/en
Publication of JPH09103077A publication Critical patent/JPH09103077A/en
Application granted granted Critical
Publication of JP3215613B2 publication Critical patent/JP3215613B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02PCLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P80/00Climate change mitigation technologies for sector-wide applications
    • Y02P80/10Efficient use of energy, e.g. using compressed air or pressurized fluid as energy carrier

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  • Rectifiers (AREA)
  • Dc-Dc Converters (AREA)
  • Power Conversion In General (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a power-factor control circuit, in which a signal synchronized with input ACs is applied to the voltage and current of the input ACs and a power factor can be improved sufficiently, regarding the power-factor control circuit reducing the waveform distortion of the single-phase input ACs. SOLUTION: An input-signal detecting section 16 is composed of a synchronizing pulse signal generating circuit 17 generating a pulse signal synchronized with AC input voltage and a signal adder 18 adding the output pulse of the circuit 17 and an input-voltage waveform. This control circuit has a circuit 19 collating and comparing the output signal of the detecting section 16 and a load-side DC output-voltage detecting value and a comparison circuit 20 comparing an output from the circuit 19 and a single-phase AC input-current waveform, and a pulse-width control-signal generating section 21 is controlled by the output signal of the comparison circuit 20. The on-off of a main switch 7 are controlled by the pulse-width control signal.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は単相の入力交流の波
形歪みを減少させるように制御する力率制御回路に関す
る。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power factor control circuit for controlling so as to reduce the waveform distortion of a single-phase input AC.

【0002】[0002]

【従来の技術】交流回路にリアクタンス分を含む負荷が
接続されているとき、印加電圧と流れる電流との間に位
相差を生じ、そのときの位相差の余弦値を「力率」と言
う。即ち、力率が100%に近い程位相差が無いことで
ある。交流を直流に変換して直流電源を得るとき、整流
回路の近辺にリアクタンスとコンデンサで構成する平滑
回路を使用するため、入力する交流電流波形に高次高調
波を含むこととなり、その交流源を他の回路と接続した
とき、他の回路に流れた歪み電流、即ち力率が悪い電流
のため、他の回路における変圧器、コンデンサなどは発
熱・焼損の起こることがある。そこで交流電流変換回路
内に力率制御回路を設け、前記障害発生を防止してい
る。特開平4−140064号公報にはその回路例で記
載されている。添付図面の図6は従来の力率制御回路の
構成を示す図である。図6において、1は交流入力源、
2は直流負荷、3は整流回路、4はダイオード、5はコ
ンデンサ、6はリアクタンスで、ダイオード4からリア
クタンス6までが平滑回路を示す。7は主スイッチで整
流回路3の出力側端子を示す。8は変流器で、交流入力
源1の電流値を検出する。9はコンデンサ5の出力端
子、10は第1誤差増幅回路、11は乗算器、12は第
2誤差増幅回路、13は波形比較回路、14は三角波発
生回路、15は出力PWM信号を示す。交流入力源1か
らの交流入力は、整流回路3及び逆流防止ダイオード4
を経て直流となされ、負荷2へ供給される。負荷2の両
端端子9は、コンデンサ5が接続され、電圧はEoであ
る。交流入力源1の電圧波形は乗算器11の一方の端子
に印加される。乗算器11の他方端子には第1誤差増幅
回路10の出力、即ち直流出力電圧の誤差値が印加され
る。第1誤差増幅回路10には直流回路の出力電圧検出
値Eoと、所定負荷電流の場合の出力電圧設定値とが入
力され、演算して得られた差が誤差として出力される。
乗算器11において、その誤差信号と入力電圧値とが印
加演算され、所定の出力電圧を得るため、即ち出力電圧
誤差が無い状態とするための入力電流目標値を求める。
次に第2誤差増幅回路12において入力電流目標値と入
力電流値とを入力して演算する。演算後の出力は電流波
形誤差と言える。即ち入力電流波形に歪みがあれば、そ
の歪みを含んでいる。波形比較回路13において、三角
波発生回路14からの三角波形信号と前記誤差信号とを
比較する。図7は波形比較回路13に対する入出力信号
波形を示す図の一例である。図7(a)に示す波形にお
いて、Vcは三角波発生回路14からの出力信号、波形
Viは電流波形誤差信号を示す。図7(b)に示す波形
は波形比較回路13の出力信号である。同出力信号は所
謂PWM信号であって、主スイッチ7をオンオフし、そ
の結果、電流包絡線を正弦波となるように制御する。図
7(c)は力率100%の正弦波の半波正弦波を示す。
例えば電流波形誤差信号が正常正弦波より大きい状態で
あれば主スイッチ7のオフ時間が長くなるように、逆に
誤差信号が小であればオン時間を長くする。そのため交
流波形の正負両半波について制御がされるから、交流入
力源1からの交流電流は純粋な正弦波状になり力率10
0%が達成される。
2. Description of the Related Art When a load including a reactance component is connected to an AC circuit, a phase difference occurs between an applied voltage and a flowing current, and the cosine value of the phase difference at that time is called "power factor". That is, the closer the power factor is to 100%, the less the phase difference is. When converting AC to DC to obtain a DC power supply, a smoothing circuit composed of a reactance and a capacitor is used near the rectifier circuit, so the input AC current waveform contains high-order harmonics. When connected to another circuit, the distortion current flowing in the other circuit, that is, a current with a poor power factor, may cause heat generation and burnout in the transformer, the capacitor, and the like in the other circuit. Therefore, a power factor control circuit is provided in the alternating current conversion circuit to prevent the occurrence of the trouble. Japanese Patent Laid-Open No. 4-140064 discloses an example of the circuit. FIG. 6 of the accompanying drawings is a diagram showing a configuration of a conventional power factor control circuit. In FIG. 6, 1 is an AC input source,
Reference numeral 2 is a DC load, 3 is a rectifier circuit, 4 is a diode, 5 is a capacitor, 6 is a reactance, and the diodes 4 to 6 represent a smoothing circuit. A main switch 7 is an output side terminal of the rectifier circuit 3. A current transformer 8 detects the current value of the AC input source 1. Reference numeral 9 is an output terminal of the capacitor 5, 10 is a first error amplification circuit, 11 is a multiplier, 12 is a second error amplification circuit, 13 is a waveform comparison circuit, 14 is a triangular wave generation circuit, and 15 is an output PWM signal. The AC input from the AC input source 1 is the rectifier circuit 3 and the backflow prevention diode 4
Then, it is converted to a direct current and is supplied to the load 2. The capacitor 5 is connected to both terminals 9 of the load 2, and the voltage is Eo. The voltage waveform of the AC input source 1 is applied to one terminal of the multiplier 11. The output of the first error amplification circuit 10, that is, the error value of the DC output voltage is applied to the other terminal of the multiplier 11. The output voltage detection value Eo of the DC circuit and the output voltage set value in the case of a predetermined load current are input to the first error amplification circuit 10, and the difference obtained by the calculation is output as an error.
In the multiplier 11, the error signal and the input voltage value are applied and calculated to obtain an input current target value for obtaining a predetermined output voltage, that is, a state in which there is no output voltage error.
Next, in the second error amplification circuit 12, the input current target value and the input current value are input and calculated. It can be said that the output after the calculation is a current waveform error. That is, if the input current waveform has a distortion, the distortion is included. The waveform comparison circuit 13 compares the triangular waveform signal from the triangular wave generation circuit 14 with the error signal. FIG. 7 is an example of a diagram showing input / output signal waveforms with respect to the waveform comparison circuit 13. In the waveform shown in FIG. 7A, Vc represents an output signal from the triangular wave generation circuit 14, and waveform Vi represents a current waveform error signal. The waveform shown in FIG. 7B is the output signal of the waveform comparison circuit 13. The output signal is a so-called PWM signal, which turns the main switch 7 on and off, and as a result controls the current envelope to be a sine wave. FIG. 7C shows a half-wave sine wave of a sine wave with a power factor of 100%.
For example, if the current waveform error signal is larger than the normal sine wave, the off time of the main switch 7 is extended, and conversely, if the error signal is small, the on time is extended. Therefore, since the positive and negative half waves of the AC waveform are controlled, the AC current from the AC input source 1 becomes a pure sine wave and the power factor is 10
0% is achieved.

【0003】[0003]

【発明が解決しようとする課題】上述の説明は力率制御
が理論通りに実行された場合であるが、実際の動作はそ
のようにならない。即ち力率改善のため制御されるべき
交流波形は実験的に見ると、入力電圧・入力電流が零の
線を横切る付近の波形を対象とすることが必要であるこ
とが判ったが、所謂ゼロクロスの検出信号は、当然小レ
ベルであるため、制御用信号に処理するまでレベル増幅
することが必要である。しかし原信号が小レベルであっ
て、雑音と区別がつきにくく、増幅して所望の信号が得
られるとは限らない。また図7(a)において信号Vi
とVcの大小関係を見ると、点MはVc=Vi=零の筈
であるが、ViはVcと同様に零になるとは限らない。
点Mにおいて雑音等のためViに正の値が生じている
と、図7(b)に示すパルスが発生してしまうから、主
スイッチの不正常な開閉がなされ、正確な正弦波を得る
ことが難しい。従って入力電流の歪みは中々取り除くこ
とができなかった。従って、従来の欠点を改善するた
め、入力交流の電圧電流に対し、入力交流に同期した負
荷信号を印加して力率を充分に改善できる力率制御回路
を提供することができるならば望ましい。
Although the above explanation is for the case where the power factor control is executed according to the theory, the actual operation is not so. In other words, it has been found experimentally that the AC waveform that should be controlled to improve the power factor should be targeted at the waveform near the point where the input voltage / input current crosses zero. Since the detection signal of 1 is of a small level, it is necessary to amplify the level until it is processed into a control signal. However, since the original signal is at a low level, it is difficult to distinguish it from noise, and the desired signal is not always obtained by amplification. Further, in FIG. 7A, the signal Vi
Looking at the magnitude relationship between Vc and Vc, the point M should be Vc = Vi = 0, but Vi does not always become zero like Vc.
When Vi has a positive value due to noise or the like at the point M, the pulse shown in FIG. 7B is generated, so that the main switch is abnormally opened / closed and an accurate sine wave is obtained. Is difficult. Therefore, the distortion of the input current could not be removed. Therefore, it is desirable to provide a power factor control circuit capable of sufficiently improving the power factor by applying a load signal synchronized with the input alternating current to the voltage of the input alternating current in order to improve the conventional drawbacks.

【0004】[0004]

【課題を解消するための手段】本発明は、上記の課題を
解決した力率制御回路を提供するもので、単相交流入力
電圧検出値と、負荷側直流出力電圧検出値とを照合比較
する照合比較回路と、該照合比較回路出力を単相交流入
力電流波形と比較する比較回路と、該比較回路で得られ
た信号によりパルス幅を制御する信号を得るパルス幅制
御信号発生部とを具備し、該信号発生部出力により交流
入力整流回路の出力電圧端子間をオンオフする主スイッ
チを制御動作させるようにした単相交流入力電流の力率
制御回路において、該力率制御回路に更に入力信号検出
部を設け、該入力信号検出部は、交流入力電圧と同期し
たパルス信号を発生する同期パルス信号発生回路と、該
同期パルス信号発生回路の出力パルスと入力電圧波形と
を加算する信号加算回路とで構成し、該信号加算回路出
力信号を前記単相入力電圧検出値とすることを特徴とす
る。この場合、前記の同期パルス発生回路は、信号比較
回路で構成し、該信号比較回路の一方の信号は交流入力
電圧で、他方は零V信号とすることが好ましい。
DISCLOSURE OF THE INVENTION The present invention provides a power factor control circuit which solves the above-mentioned problems, and collates and compares a single-phase AC input voltage detection value and a load-side DC output voltage detection value. The comparison and comparison circuit, a comparison circuit for comparing the output of the comparison and comparison circuit with a single-phase AC input current waveform, and a pulse width control signal generator for obtaining a signal for controlling the pulse width by the signal obtained by the comparison circuit. In the power factor control circuit for a single-phase alternating current input current, which controls the main switch that turns on and off between the output voltage terminals of the alternating current input rectifier circuit by the output of the signal generator, the input signal is further input to the power factor control circuit. A detection unit is provided, and the input signal detection unit includes a synchronization pulse signal generation circuit that generates a pulse signal synchronized with an AC input voltage, and a signal addition unit that adds an output pulse of the synchronization pulse signal generation circuit and an input voltage waveform. Constituted by a circuit, characterized in that the signal adding circuit output signal and the single-phase input voltage detection value. In this case, it is preferable that the synchronizing pulse generating circuit is composed of a signal comparing circuit, and one signal of the signal comparing circuit is an AC input voltage and the other is a zero V signal.

【0005】[0005]

【発明の実施の形態】本発明の実施例を添付図面につき
詳述する。図1は本発明の力率制御回路の構成を示すブ
ロック図である。図1において、1は交流電源、2は負
荷、7は主スイッチ、16は入力信号検出部、17は同
期パルス発生回路、18は信号加算回路、19は照合比
較回路、20は比較回路、21はパルス幅制御信号発生
部、22は整流回路を示す。而して、本発明の力率制御
回路の構成を参照番号と共に説明すれば、単相交流入力
電圧検出値と、負荷側直流出力電圧検出値とを照合比較
する照合比較回路19と、該照合比較回路出力を単相交
流入力電流波形と比較する比較回路20と、該比較回路
20で得られた信号によりパルス幅を制御する信号を得
るパルス幅制御信号発生部21とを具備し、該信号発生
部21の出力により交流入力電流回路の出力電圧端子間
をオンオフする主スイッチ7を制御動作させるようにし
た単相交流入力電流の力率制御回路において、該力率制
御回路に更に入力信号検出部16を設け、該入力信号検
出部16は、交流入力電圧と同期したパルス信号を発生
する同期パルス信号発生回路17と、該同期パルス信号
発生回路17の出力パルスと入力電圧波形とを加算する
信号加算回路18とで構成し、該信号加算回路18出力
信号を前記単相入力電圧検出値とすることで構成する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of the present invention will be described in detail with reference to the accompanying drawings. FIG. 1 is a block diagram showing the configuration of the power factor control circuit of the present invention. In FIG. 1, 1 is an AC power supply, 2 is a load, 7 is a main switch, 16 is an input signal detection unit, 17 is a synchronous pulse generation circuit, 18 is a signal addition circuit, 19 is a collation comparison circuit, 20 is a comparison circuit, 21 Is a pulse width control signal generator, and 22 is a rectifier circuit. Thus, the configuration of the power factor control circuit of the present invention will be described with reference numerals, a collation comparison circuit 19 that collates and compares a single-phase AC input voltage detection value and a load-side DC output voltage detection value, and the collation comparison circuit 19. The comparison circuit 20 is provided with a comparison circuit 20 for comparing the output of the comparison circuit with a single-phase AC input current waveform, and a pulse width control signal generator 21 for obtaining a signal for controlling the pulse width by the signal obtained by the comparison circuit 20. In a power factor control circuit for a single-phase alternating current input current, in which a main switch 7 for turning on / off between output voltage terminals of an alternating current input current circuit is controlled by an output of a generator 21, a further input signal is detected by the power factor control circuit. A section 16 is provided, and the input signal detection section 16 generates a sync pulse signal generation circuit 17 for generating a pulse signal synchronized with an AC input voltage, an output pulse of the sync pulse signal generation circuit 17 and an input voltage waveform. Constituted by the signal adding circuit 18 to calculate, constitutes the signal adder circuit 18 output signal by said single-phase input voltage detection value.

【0006】本発明において力率制御のため同期パルス
信号発生回路17により入力交流に対し同期したパル
ス、即ち交流電源の周波数に同期したパルスを発生させ
る。その信号は入力電圧が零Vのときパルス振幅だけの
大きさを有しているから、前記パルス信号と入力電圧と
を信号加算回路18により加算すると、正弦波の交流入
力が正負両方向に膨らみを付けた形となる。次でその信
号に対し照合比較回路19において出力電圧の誤差と乗
算する。照合比較回路19の出力はそのとき接続してい
る負荷に対して必要な入力電流に目標値である。そのた
めこの目標値と入力電流波形とを比較回路20において
比較することで、前記目標値と実際の値との誤差を求め
る。本発明によれば、次でパルス幅制御信号発生部21
においてPWM信号を得る。PWM信号によりスイッチ
7をオンオフすれば、整流回路22へ流れ込む電流の力
率は100%と見て良い。
In the present invention, for power factor control, the synchronous pulse signal generating circuit 17 generates a pulse synchronized with the input AC, that is, a pulse synchronized with the frequency of the AC power supply. Since the signal has a magnitude corresponding to the pulse amplitude when the input voltage is 0 V, when the pulse signal and the input voltage are added by the signal adding circuit 18, the AC input of the sine wave expands in both positive and negative directions. It becomes the attached shape. Then, the signal is multiplied by the error of the output voltage in the comparison and comparison circuit 19. The output of the verification and comparison circuit 19 is the target value for the input current required for the load connected at that time. Therefore, by comparing this target value and the input current waveform in the comparison circuit 20, the error between the target value and the actual value is obtained. According to the present invention, the pulse width control signal generator 21
At get the PWM signal. If the switch 7 is turned on / off by the PWM signal, the power factor of the current flowing into the rectifier circuit 22 can be regarded as 100%.

【0007】図2は上記の発明の好ましい実施の形態と
して、図1に示す入力信号検出部16の具体的な構成図
である。図2において31は交流入力電圧の印加端子S
を示す。32は電圧比較器を示し、同期パルス信号発生
回路の一例である。33は電圧加算回路を示す。電圧比
較器32の一方の端子には交流入力電圧の印加端子から
の信号が印加され、他方の端子には零V(0V)の基準
電位が印加されている。零Vの基準電位を得ることは、
例えば電池端子の接地側端子と接続してその電位を得る
こと、或いは電源変圧器の二次側出力の一線を図示の制
御線の零Vと接続して得ることである。電圧比較器31
は二つの端子の電位が同じになった瞬間、出力端子にパ
ルス出力を発生させるから、交流入力電圧が零Vを横切
る瞬間に、出力にパルスが発生し、入力電圧が半波の高
い値から再び低下し零Vを横切るまでの正性パルスとな
る。そして零Vを横切る瞬間に負性パルスを発生する。
この負性パルスの幅も次に零Vを横切るまでである。こ
のパルス波形は図2において「方形波P」と示してい
る。電圧加算回路33の一方の端子の信号は、前記パル
ス信号Pで、他方の端子の信号は端子31に示す入力電
圧波形である。電圧加算回路33の出力端子Tには、そ
の右方に実線で示すような正弦波状の中間部が上下に嵩
張った波形が出力する。尚、その波形に接して示す点線
の信号は入力電圧波形である。電圧加算回路33におい
ては、入力交流に同期した負荷信号としてのパルス信号
Pを入力電圧波形に加算しているから、電圧加算回路3
3の出力信号は特殊な波形になる。
FIG. 2 is a concrete configuration diagram of the input signal detecting section 16 shown in FIG. 1 as a preferred embodiment of the invention described above. In FIG. 2, reference numeral 31 denotes an AC input voltage application terminal S.
Is shown. Reference numeral 32 denotes a voltage comparator, which is an example of a synchronizing pulse signal generating circuit. Reference numeral 33 indicates a voltage adding circuit. The signal from the application terminal of the AC input voltage is applied to one terminal of the voltage comparator 32, and the reference potential of zero V (0V) is applied to the other terminal. Obtaining a zero V reference potential is
For example, it can be obtained by connecting to the ground side terminal of the battery terminal to obtain its potential, or by connecting one line of the secondary side output of the power supply transformer to zero V of the illustrated control line. Voltage comparator 31
Generates a pulse output at the output terminal at the moment when the potentials of the two terminals become the same, a pulse is generated at the output at the moment when the AC input voltage crosses zero V, and the input voltage changes from a high half-wave value. It becomes a positive pulse until it drops again and crosses zero V. Then, a negative pulse is generated at the moment when the voltage crosses zero V.
The width of this negative pulse is until the next crossing of 0V. This pulse waveform is shown as "square wave P" in FIG. The signal at one terminal of the voltage adding circuit 33 is the pulse signal P, and the signal at the other terminal is the input voltage waveform shown at the terminal 31. To the output terminal T of the voltage adding circuit 33, a waveform in which a sine wave-shaped intermediate portion as shown by a solid line on the right side thereof is bulky up and down is output. The dotted line signal shown in contact with the waveform is the input voltage waveform. In the voltage adding circuit 33, since the pulse signal P as a load signal synchronized with the input AC is added to the input voltage waveform, the voltage adding circuit 3
The output signal of 3 has a special waveform.

【0008】電圧加算回路33の出力端子Tは図3に示
す従来の力率制御回路に相当する回路の交流入力源の入
力端子と接続される。即ち、図3において乗算器11に
対する一方の入力信号となる。乗算器11に対する他方
の入力信号は出力電圧誤差値である。そのため乗算器1
1の出力Uには出力電圧誤差が無い状態とするための入
力電流目標値が得られる。
The output terminal T of the voltage adding circuit 33 is connected to the input terminal of the AC input source of the circuit corresponding to the conventional power factor control circuit shown in FIG. That is, it becomes one input signal to the multiplier 11 in FIG. The other input signal to the multiplier 11 is the output voltage error value. Therefore multiplier 1
The input current target value for making the output U of 1 have no output voltage error is obtained.

【0009】図4は図2及び図3に示す構成の回路にお
ける各部の波形を示す図である。図4(a)は図2の端
子Sにおける入力電圧波形を示す。図4(b)は電圧比
較器32の出力端子の波形を示す。図4(c)は電圧加
算回路33の出力端子Tにおける波形を示す。図4
(c)に示す波形はその形状から判断して入力信号検出
部16において入力電圧検出波形の立ち上がりを急峻に
するため、パルス信号Pを加算している。図4(d)は
前記入力電圧目標値を示す波形を示す。次に図3示の第
2誤差信号増幅器12において、端子Wから入力波形の
信号を入力させ演算する。第2誤差信号増幅器12の出
力Vyは、入力電流波形に含まれる誤差信号を含んだも
のである。(図4(f)参照)。そのため波形比較回路
13において出力信号Vyと三角波14の出力Vcとを
比較して、PWM信号15Vzが得られる。
FIG. 4 is a diagram showing the waveform of each part in the circuit having the configuration shown in FIGS. 2 and 3. FIG. 4A shows an input voltage waveform at the terminal S in FIG. FIG. 4B shows the waveform at the output terminal of the voltage comparator 32. FIG. 4C shows the waveform at the output terminal T of the voltage adding circuit 33. FIG.
The waveform shown in (c) is added with the pulse signal P in order to make the rising edge of the input voltage detection waveform steep in the input signal detection unit 16 judging from its shape. FIG.4 (d) shows the waveform which shows the said input voltage target value. Next, in the second error signal amplifier 12 shown in FIG. 3, the signal of the input waveform is input from the terminal W and the calculation is performed. The output Vy of the second error signal amplifier 12 includes the error signal included in the input current waveform. (See FIG. 4 (f)). Therefore, the waveform comparison circuit 13 compares the output signal Vy with the output Vc of the triangular wave 14 to obtain the PWM signal 15Vz.

【0010】図5に示すPWM信号15Vzは図7と比
較し、パルス波形の幅について広狭の差が少ない。それ
は図3に示すように、波形比較回路13において三角波
発生回路14の出力信号Vcと前記の第2誤差信号増幅
器12の出力信号Vyとを比較したとき、信号Vyに含
まれる誤差信号を確実に取り出しているからである。従
ってこのPWM信号15により図1に示すスイッチ7を
制御すれば、従来よりも力率改善の効果が大きく得られ
る。
Compared to FIG. 7, the PWM signal 15Vz shown in FIG. 5 has a small difference in width between pulse waveforms. As shown in FIG. 3, when the output signal Vc of the triangular wave generating circuit 14 and the output signal Vy of the second error signal amplifier 12 are compared in the waveform comparison circuit 13, the error signal included in the signal Vy is surely detected. This is because it is taken out. Therefore, if the switch 7 shown in FIG. 1 is controlled by the PWM signal 15, the effect of improving the power factor is greater than that in the conventional case.

【0011】[0011]

【発明の効果】このように本発明の上記構成によれば、
単相交流入力電流の力率改善のため入力電圧無誤差目標
値を得る負荷側の出力線圧と乗算する回路への印加信号
として、入力電圧検出波形の立ち上がりを急峻にした信
号、即ち入力電源交流の周波数に同期したパルスを使用
しているので、その信号に基づき演算して得られたスイ
ッチのオンオフ信号は、力率改ざん用に充分に大きな効
果を奏する。
As described above, according to the above configuration of the present invention,
To improve the power factor of the single-phase AC input current, obtain the input voltage error-free target value.The signal applied to the circuit that multiplies with the output line pressure on the load side, that is, the signal with a sharp rise in the input voltage detection waveform Since the pulse synchronized with the frequency of the alternating current is used, the on / off signal of the switch obtained by calculation based on the signal has a sufficiently large effect for tampering with the power factor.

【図面の詳細な説明】[Detailed Description of Drawings]

【図1】 本発明の実施例の構成を示すブロック図であ
る。
FIG. 1 is a block diagram showing a configuration of an exemplary embodiment of the present invention.

【図2】 図1に示す入力信号検出部の具体的な構成図
である。
FIG. 2 is a specific configuration diagram of the input signal detection unit shown in FIG.

【図3】 従来の力率制御回路に本発明を適用した場合
の回路図である。
FIG. 3 is a circuit diagram when the present invention is applied to a conventional power factor control circuit.

【図4】 図2及び図3に示す構成の回路における各部
の波形を示す図である。
FIG. 4 is a diagram showing the waveform of each part in the circuit having the configuration shown in FIGS. 2 and 3.

【図5】 本発明の実施例における波形比較用信号とP
WM信号とを示す図である。
FIG. 5 is a waveform comparison signal and P in the embodiment of the present invention.
It is a figure which shows a WM signal.

【図6】 従来の力率制御回路の構成を示す図である。FIG. 6 is a diagram showing a configuration of a conventional power factor control circuit.

【図7】 図6に示す波形比較回路に対する入出力信号
波形を示す図である。
7 is a diagram showing input / output signal waveforms for the waveform comparison circuit shown in FIG.

【符号の説明】[Explanation of symbols]

1 交流入力源 2 負荷 7 主スイッチ 16 入力信号
検出部 17 同期パルス信号発生回路 18 信号加算
回路 19 照合比較回路 20 比較回路 21 パルス幅制御信号発生部 22 整流回路
DESCRIPTION OF SYMBOLS 1 AC input source 2 Load 7 Main switch 16 Input signal detection unit 17 Synchronous pulse signal generation circuit 18 Signal addition circuit 19 Collation comparison circuit 20 Comparison circuit 21 Pulse width control signal generation unit 22 Rectification circuit

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 単相交流入力電圧検出値と、負荷側直流
出力電圧検出値とを照合比較する照合比較回路と、該照
合比較回路出力を単相交流入力電流波形と比較する比較
回路と、該比較回路で得られた信号によりパルス幅を制
御する信号を得るパルス幅制御信号発生部とを具備し、
該信号発生部出力により交流入力整流回路の出力電圧端
子間をオンオフする主スイッチを制御動作させるように
した単相交流入力電流の力率制御回路において、該力率
制御回路に更に入力信号検出部を設け、該入力信号検出
部は、交流入力電圧と同期したパルス信号を発生する同
期パルス信号発生回路と、該同期パルス信号発生回路の
出力パルスと入力電圧波形とを加算する信号加算回路と
で構成し、該信号加算回路出力信号を前記単相入力電圧
検出値とすることを特徴とする力率制御回路。
1. A collation comparison circuit that collates and compares a single-phase AC input voltage detection value and a load-side DC output voltage detection value; and a comparison circuit that compares the collation comparison circuit output with a single-phase AC input current waveform. A pulse width control signal generator for obtaining a signal for controlling the pulse width by the signal obtained by the comparison circuit,
In a power factor control circuit for a single-phase AC input current, wherein a main switch that turns on and off between output voltage terminals of an AC input rectifier circuit is controlled by the output of the signal generation unit, the power factor control circuit further includes an input signal detection unit. The input signal detection unit is provided with a synchronous pulse signal generating circuit for generating a pulse signal synchronized with an AC input voltage, and a signal adding circuit for adding an output pulse of the synchronous pulse signal generating circuit and an input voltage waveform. A power factor control circuit, wherein the output signal of the signal addition circuit is the detected value of the single-phase input voltage.
【請求項2】 請求項1記載の同期パルス発生回路は、
信号比較回路で構成し、該信号比較回路の一方の信号は
交流入力電圧で、他方は零V信号とすることを特徴とす
る力率制御回路。
2. The synchronizing pulse generating circuit according to claim 1,
A power factor control circuit comprising a signal comparison circuit, wherein one signal of the signal comparison circuit is an AC input voltage and the other is a zero V signal.
JP28261595A 1995-10-04 1995-10-04 Power factor control circuit Expired - Fee Related JP3215613B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP28261595A JP3215613B2 (en) 1995-10-04 1995-10-04 Power factor control circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP28261595A JP3215613B2 (en) 1995-10-04 1995-10-04 Power factor control circuit

Publications (2)

Publication Number Publication Date
JPH09103077A true JPH09103077A (en) 1997-04-15
JP3215613B2 JP3215613B2 (en) 2001-10-09

Family

ID=17654834

Family Applications (1)

Application Number Title Priority Date Filing Date
JP28261595A Expired - Fee Related JP3215613B2 (en) 1995-10-04 1995-10-04 Power factor control circuit

Country Status (1)

Country Link
JP (1) JP3215613B2 (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013520801A (en) * 2010-02-19 2013-06-06 アプライド マテリアルズ インコーポレイテッド High efficiency / high accuracy heater driver
JP5818395B1 (en) * 2015-04-25 2015-11-18 日理工業株式会社 Power correction apparatus and power correction method
JP2019122073A (en) * 2017-12-28 2019-07-22 三菱重工サーマルシステムズ株式会社 Converter device, control method, and program
JP2021040420A (en) * 2019-09-03 2021-03-11 三菱重工サーマルシステムズ株式会社 Converter device, control method, and program

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013520801A (en) * 2010-02-19 2013-06-06 アプライド マテリアルズ インコーポレイテッド High efficiency / high accuracy heater driver
US9612020B2 (en) 2010-02-19 2017-04-04 Applied Materials, Inc. High efficiency high accuracy heater driver
JP5818395B1 (en) * 2015-04-25 2015-11-18 日理工業株式会社 Power correction apparatus and power correction method
JP2019122073A (en) * 2017-12-28 2019-07-22 三菱重工サーマルシステムズ株式会社 Converter device, control method, and program
JP2021040420A (en) * 2019-09-03 2021-03-11 三菱重工サーマルシステムズ株式会社 Converter device, control method, and program

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