JPH09102804A - Automatic speed detecting device in fsk modem and fsk modem providing automatic speed detecting device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To automatically setting reception speed in accordance with the transmission speed of a reception signal. SOLUTION: A first decoder 7 and a second decoder 8 are respectively provided to the quaternary FSK signal of 2400bps with a probability to be inputted from an outside and the binary FSK signal of 1200bps. A flag code which is inputted at the time of starting communication in accordance with HDLC procedure is detected in a speed detecting circuit 9 and the change-over contact 10a of a change-over switch 10 is changed-over by the speed detecting circuit 9 so as to permit one of the decoders 7 or 8 where the flag code is detected as a prescribed value in accordance with the transmission speed of the input signal to be connected to a signal converter 11 where an NRZI type is converted into an NRZ type. Then, reception speed is automatically changed in accordance with the bit rate of the inputted signal so that a monitor signal suitable to the reception signal is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a so-called FSK modem for modulating / demodulating an FSK signal, and more particularly to an automatic speed detecting device and an FSK modem in an FSK modem for automating setting of a receiving speed.

[0002]

2. Description of the Related Art FSK (Frequency Shift Keying) signals are widely used for recording data from telephone modems and personal computers on magnetic tapes such as so-called cassette tapes. In the field of amateur radio, it is used as a signal system for packet communication. By the way, in the packet radio communication of the amateur radio, various transmission speeds of the FSK signal are selected and used according to the use situation.

[0003]

Therefore, a so-called wireless FSK modem that handles such wireless FSK is required to support various transmission speeds of FSK signals. However, in this type of wireless FSK modem that has been conventionally provided, the FSK to receive is
Although there is a function that supports various signal transmission rates, it is premised that the user recognizes the transmission rate of the FSK signal received in advance. It was a so-called manual setting. Therefore, without bothering the user
There has been a demand for a device in which the reception speed of a modem is automatically set according to the speed of an input signal.

The present invention has been made in view of the above situation, and an automatic speed detecting device in an FSK modem capable of automatically setting a receiving speed according to a transmission speed of an input signal and such automatic speed detection. An FSK modem with a device is provided. Another object of the present invention is to provide an automatic speed detecting device in an FSK modem capable of automatic speed setting without adding new changes to an existing transmission control procedure, and an FSK modem equipped with such an automatic speed detecting device. To do.

[0005]

An automatic speed detecting device in an FSK modem according to the present invention as set forth in claim 1 is constructed on the basis of a predetermined transmission control procedure and is adapted to receive a packet signal which is FSK-modulated and inputted. Demodulate, decode the demodulated signal based on the predetermined transmission control procedure,
In the output FSK modem, the decoding means for decoding the demodulated signal is provided corresponding to the bit transmission rate that can be input from the outside, and the output signals of the plurality of decoding means are input to the predetermined FSK modem. A flag detecting means for detecting a flag code based on a transmission control procedure; and an output selecting means for selecting an output signal of the decoder means in which the flag code is detected by the flag detecting means and outputting the signal to the outside. It will be.

In such a configuration, the signal input from the outside is demodulated and then simultaneously input to each decoding means, but only the flag code output from the decoding means that matches the transmission speed of the input signal is used. , It is obtained in a state of being decoded into a predetermined code pattern, and therefore, in the flag detecting means, it is input from the outside by determining whether the decode signal from each decoding means corresponds to a predetermined flag code. The transmission rate of the generated signal can be determined. Then, the output selection means is adapted to select the output of the decoding means which is determined to have detected the flag by the flag detection means and output it to the outside, so that the user can recognize the transmission speed of the input signal. Regardless of the presence or absence, the speed of the received signal is automatically selected, and the monitor signal adapted to the transmission speed can be obtained.

The FSK modem according to a second aspect of the present invention comprises the automatic speed detecting device according to the first aspect of the present invention. As described above, the FSK modem automatically operates according to the transmission speed of the input signal. The reception speed is switched, and an appropriate monitor signal can be obtained.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to FIGS. First, the configuration of an FSK (Freqency Shift Keying) modem to which the present invention is applied will be described with reference to FIG. This figure 1
The configuration shown in (1) is particularly related to the part related to demodulation in the FSK modem, and is roughly divided into a demodulation section 1 and a decoding section 2. The demodulation unit 1 is an FSK demodulator (“FSK DEM” in FIG. 1) that demodulates an FSK signal.
The output signal from the FSK demodulator 3 is sampled using a clock signal reproduced by a so-called PLL (Phase-Locked Loop) as a sampling clock, and NRZI (Non Return to Zero-Inverte
It is designed to be output as a d) format signal.

That is, in the demodulation section 1, in addition to the FSK demodulator 3, an edge detection circuit 4 for detecting the falling and rising edges of the output signal of the FSK demodulator 3 and a PLL circuit (in FIG. 1, "PLL" is used). 5) and a sampling circuit 6 are provided. The PLL circuit 5 is an oscillating circuit having a known and well-known general configuration, and is an FSK.
The clock signal is generated in synchronization with the pulse signal output from the edge detection circuit 4 based on the edge detection of the output signal of the demodulator 3.

Then, in synchronization with the clock signal output from the PLL circuit 5, the sampling circuit 6
The output signal of the FSK demodulator 3 is sampled and output to the decoding unit 2 in the NRZI format.

The decoding unit 2 includes first and second decoders 7 and 8, a speed detection circuit 9, a changeover switch 10 and a signal converter 11, and a signal input from the demodulation unit 1 is included. First and second automatically according to the bit transmission rate of
Of the decoders 7 and 8 is selected and output as a monitor signal. First
Decoder (shown as "2400bps DEC" in Fig. 1)
7 is 2400 bps (bit) in the embodiment of the present invention.
per second) four-valued FSK signal is decoded. On the other hand, the second decoder (in FIG. 1, "1200bp
s DEC ") 8 is for decoding a binary FSK signal of 1200 bps.

In the embodiment of the present invention, binary FSK
It is assumed that either the signal or the four-valued FSK signal is input from the outside, and the binary FSK signal has a frequency corresponding to the logical value "0" of 1200 Hz and a frequency corresponding to the logical value "1". 2200 Hz is assumed to be used respectively (see FIG. 2). Also, 4
As the value FSK signal, the frequency corresponding to the logical value "10" is 2200 Hz, the frequency corresponding to the logical value "01" is 1200 Hz, the frequency corresponding to the logical value "00" is 1533 Hz, and the logical value "11". It is assumed that 1867 Hz is used as the frequency corresponding to (see FIG. 2).

Further, the bit transmission rate of the binary FSK signal (hereinafter referred to as "bit rate") is 1200 bps.
The bit rate of the 4-level FSK signal is 2400 bps
Are assumed, and the so-called 1-symbol change speeds of these two types of signals are the same.

Speed detection circuit ("DET" in FIG. 1)
9) inputs the output signal from the first decoder 7 and the output signal from the second decoder 8 and detects a flag code based on the HDLC procedure, as will be described later. The changeover switch 10 is switched so that the decoder on the side where is detected and the signal converter 11 are connected. The speed detecting circuit 9 may be entirely configured by so-called hardware, but in consideration of its function, it is more preferable that the speed detecting circuit 9 is configured by a so-called CPU so as to perform a required function by software.

In the changeover switch 10, the output stage of the first decoder 7 is connected to the first contact 10b, and the output stage of the second decoder 8 is connected to the second contact 10c. As described above, the switching contact 10a is switched in accordance with the control signal from the speed detection circuit 9, so that the first contact
Either the output signal of the decoder 7 or the output signal of the second decoder 8 is input to the signal converter 11.

The change-over switch 10 is preferably an electronic switch made of a semiconductor, but is not limited to this. The signal converter (denoted as “CON” in FIG. 1) 11 converts a signal input in the NRZI format into a signal in the NRZ (Non Return to Zero) format.

Next, the operation of the above configuration will be described with reference to FIG.
This will be described with reference to FIG. First, this FSK modem is for transmitting and receiving packet signals, and its transmission control procedure (transmission control protocol) is HDLC (High Lev
el Date Link Procedure). Since HDLC is set as a standard of CCITT and is a known and well-known transmission control procedure, detailed description thereof will be omitted here.

When the communication is started, an external transmission side (not shown), which is a communication partner, first transmits a bit code, which is set by the transmission side, based on the HDLC control, with a flag consisting of a predetermined code. The signals are continuously input in the state of being FSK-modulated at the speed. This flag code is expressed as "7EH" in hexadecimal notation, and this "7EH"
However, the signal is continuously input until the operation on the receiving side rises and a normal receiving state is achieved.

The flags input to the first and second decoders 7 and 8 via the FSK demodulator 3 and the sampling circuit 6 are respectively decoded, but in the decoders on the side where the transmission rates do not match, , The flag code "7EH" is not decoded, and "7EH" is output only from the decoder side having the same transmission rate.

For example, if a signal is inputted from the transmitting side by binary FSK modulation of 1200 bps, a binary NRZ for "7EH" which can be outputted from the second decoder 8.
The decoded output signal of the I format is "N
As indicated in the column labeled "RZI", "000
Two patterns of "00001" and "11111110" can be considered. In addition, in the column described as “input” in FIG. 3, the code displayed below “7EH” is “7
It is a binary display of "EH".

Therefore, in the speed detection circuit 9,
After eight "0" s are continuously detected, one "1" is continuously detected for a predetermined number of times, or "1" is detected.
FS received when the occurrence of one "0" after a predetermined number of times is detected for a predetermined number of times.
The bit rate of the K signal is determined to be 1200 bps. Here, the predetermined number of times may be at least one, but in reality, it is preferably a plurality of times from the viewpoint of improving the certainty of detection.

In the HDLC procedure, when five "1" s are consecutive in the main body of information transmitted together with a flag, a CRC code, etc., based on a predetermined frame structure, transmission is performed. Since there is a zero insertion function in which a "0" is forcibly inserted on the side, seven "1" s are not detected consecutively as described above except for the flag, and the main body of information is It is not mistaken for a flag.

On the other hand, the binary FS corresponding to the above-mentioned flag
K signal, that is, "00000001" or "1111"
When "1110" is input to the first decoder 7, which is a decoder for 4-valued FSK signals, this input code is converted into a 4-valued code in which each bit is represented by 2 bits. That is, "0" becomes "00" and "1"
Are converted into “10” and output from the first decoder 7, so that the first
The signal output from the decoder 7 of 1 does not satisfy the condition for being judged as the flag by the binary FSK signal as described above. The decode output of the first decoder 7 for "00000001" is "0101".
"010101010110" becomes "1111111.
"0" means "101010101010101001"
Becomes

Next, a quaternary F of 2400 bps from the transmitting side
A case where a signal is input by SK modulation will be described. In this case, “7EH” that can be output from the first decoder 7
As for the 4-valued NRZI-type decoded output signal for the sequence of, there are four possible patterns as shown in FIG. That is, whether “00000001” is repeated or “10000000” is repeated,
Repeat "11111110", or even more,
It is one of the repetitions of "01111111".

As described above, it is possible to generate four patterns by converting two bits as one set when being decoded into four values, and the combination of the two bits depends on the input timing and the flag code ". When the first bit of "7EH" is just converted into four values by two, the last bit of the immediately preceding flag code "7EH" and the first bit of the flag code "7EH" immediately after are converted to one. This is because, as a set, there may be a case where every 2 bits are converted into 4 values.

Then, the speed detection circuit 9 is adapted to detect these four patterns as follows. First, when the pattern shown in FIG. 4A, that is, “00000001” is input to the speed detection circuit 9, “00” is 3 in the speed detection circuit 9.
When the detection of “01” once occurs consecutively a predetermined number of times after being detected continuously, it is assumed that the first decoder 7 outputs the flag code “7EH”. A control signal is output to the switching contact 10a of the changeover switch 10 to the first contact 10b side.

Next, when the pattern shown in FIG. 4B, that is, "10000000" is input to the speed detection circuit 9, after the speed detection circuit 9 detects "10" once, When "00" is detected three times consecutively at least once, it is determined that the first decoder 7 outputs the flag code "7EH", and the control signal is output to the changeover switch 10. , Changeover switch 1
The 0 switching contact 10a is switched to the first contact 10b side.

When the pattern shown in FIG. 4C, that is, "11111110" is input to the speed detection circuit 9, "11" is detected three times in succession in the speed detection circuit 9. After that, when the detection of "10" once occurs continuously for a predetermined number of times, it is determined that the flag code "7EH" is output from the first decoder 7, and the control signal is output to the changeover switch 10. Thus, the switching contact 10a of the changeover switch 10 is switched to the first contact 10b side.

Further, when the pattern shown in FIG. 4D, that is, "01111111" is input to the speed detecting circuit 9, "01" is 1 in the speed detecting circuit 9.
After the first detection, the first decoder 7 detects that “11” has been detected three times in succession for a predetermined number of times.
Assuming that the flag code "7EH" is output from the control switch 10, a control signal is output to the changeover switch 10, and the changeover contact 10a of the changeover switch 10 is switched to the first contact 10b side. In any of the above cases, the predetermined number of times may theoretically be one,
In reality, a plurality of times is desirable from the viewpoint of prevention of erroneous determination.

On the other hand, when the code shown in FIG. 4 is input to the second decoder 8, the decoding result is as follows. First, this second decoder 8
Then, the 4-level code is converted into the binary code, and in this case, the 2-bit code is converted into the corresponding 1-bit binary code. Therefore, for "00000001", "00" and " As a result of converting both "01" into "0", "0000" is obtained.

Regarding "10000000",
As a result of converting “10” into “1” and “00” into “0”, the result becomes “10000”, and further, “11”
For “111110”, the result of converting “11” and “10” into “1” is “1111”. Furthermore, as for “01111111”, “01” is converted to “0” and “11” is converted to “1”, resulting in “0111”.

Therefore, even if these codes are input from the second decoder 8 to the speed detection circuit 9, the above-mentioned condition for judging as the four-valued FSK signal is not satisfied, and it is possible to use the code from the outside. When the value FSK signal is input, regarding the decode output from the second decoder 8,
The speed detection circuit 9 is prevented from being judged as a four-valued FSK signal.

Next, of the above-mentioned operations, particularly, the operation of the speed detection circuit 9 will be generally described again with reference to the flowchart of FIG. First, the first received signal is 1200 bps
The flag is detected by the binary FSK signal in order to determine whether or not the binary FSK signal (see step 100 in FIG. 5). That is, it is judged whether or not the input signal from the second decoder 8 satisfies the predetermined condition. Specifically, "0" is detected seven times in a row and then "1" is detected once, or
After seven consecutive detections of "1", it is determined whether the detection of "0" once occurs a predetermined number of times. Here, the predetermined number of times may be one, but from the viewpoint of improving detection accuracy, it is preferable to set a plurality of times.

Then, if it is determined that the flag is detected under the above-described determination conditions (step 102 in FIG. 5).
In the case of “YES”), the changeover contact 10a of the changeover switch 10 is set to the second position by the control signal from the speed detection circuit 9.
The output signal of the second decoder 8 is output via the signal converter 11 and the output is switched (see step 108 in FIG. 5).

On the other hand, if the flag is not detected under the above-mentioned determination conditions ("NO" in step 102 of FIG. 5), the flag is detected by the four-valued FSK signal. (See step 104 in FIG. 5). That is, it is determined whether or not any of the following conditions is satisfied for the input signal from the first decoder 7.

The first condition is that "01" is detected once after "00" is repeated three times. The second condition is that after "10" occurs once, "00" is detected three times in a row. The third condition is that "10" is detected once after "11" is repeated three times. The fourth condition is that “01” occurs once and then “11” is detected three times in succession.

Then, it is determined whether or not the flag is detected by determining whether or not any of these four conditions has occurred a predetermined number of times in succession, and it is determined that the flag is detected. If (YES in step 106 of FIG. 5), the switching contact 10a of the changeover switch 10 is connected to the first contact 10b by the control signal from the speed detection circuit 9, and the first decoder 7 The output signal is output through the signal converter 11 and the output is switched (see step 110 in FIG. 5).

On the other hand, if the flag is not detected (“NO” in step 106 of FIG. 5), the flag should be detected by either the first or second decoder 7, 8 originally. However, since the flag has not been detected, the series of processes is temporarily terminated, the process returns to the main routine (not shown), and the reception speed set before this series of processes is maintained. In the flowchart shown in FIG. 5, first 1200 bps
Whether or not it is determined whether or not it is 2400 bps is determined thereafter. However, since the order of this determination has nothing to do with the essence of the present invention, it may be reversed. Of course.

In the embodiment of the invention described above, signals of two kinds of bit rates are assumed as the signals input from the outside, and the decoders 7 and 8 for the signals of the respective bit rates are provided. The signals input externally do not necessarily have to be of two types as described above.
It goes without saying that a decoder corresponding to each bit rate may be provided as the number of types or more.

In the embodiment of the invention described above, the decoding means is the first and second decoders 7 and 8, the flag detecting means is the speed detecting circuit 9, and the output selecting means is the changeover switch 10. , Have been realized respectively.

[0041]

As described above, according to the present invention,
In the existing transmission control procedure, the transmission rate of the received signal is
The transmission speed of the received signal is determined by detecting the presence or absence of the flag sent based on a predetermined transmission control procedure by adopting a configuration that can automatically detect it without adding new signals or other changes. Since the reception speed can be set automatically, the reception speed can be set automatically and the user is not bothered with F.
An SK modem can be provided.

Further, since it is not necessary to add a new signal for automatic detection of the transmission rate of the received signal, for example,
It can maintain compatibility with conventional signals such as binary FSK signals, can be applied to existing modems by adding a small number of configurations, and when transmitting data to conventional modems. The present invention has an effect that it is possible to provide a modem having high compatibility with a conventional device without any trouble.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing a configuration of an automatic speed detection device in an FSK modem according to the present invention in an embodiment of the invention.

FIG. 2 is an explanatory diagram for explaining an FSK signal in the embodiment of the present invention.

FIG. 3 is an explanatory diagram for describing hexadecimal display of flags based on the HDLC procedure and binary display in the NRZI format according to the embodiment of the present invention.

FIG. 4 is an explanatory diagram for describing four-value display of a flag based on the HDLC procedure in the NRZI format according to the embodiment of the present invention.

FIG. 5 is a flowchart illustrating a flag detection operation in the speed detection circuit according to the embodiment of the present invention.

[Explanation of symbols]

 3 ... FSK demodulator 4 ... Edge detection circuit 5 ... PLL circuit 6 ... Sampling circuit 7 ... First decoder 8 ... Second decoder 9 ... Speed detection circuit 10 ... Changeover switch 11 ... Signal converter

Claims (2)

[Claims] 1. A packet signal which is constructed on the basis of a predetermined transmission control procedure and which is FSK-modulated and input is demodulated, and the demodulated signal is decoded on the basis of the predetermined transmission control procedure and output. In the FSK modem, the decoding means for decoding the demodulated signal is provided corresponding to the bit transmission rate that can be input from the outside, and the output signals of the plurality of decoding means are input to perform the predetermined transmission. A flag detecting unit for detecting a flag code based on a control procedure; and an output selecting unit for selecting an output signal of the decoder unit in which the flag code is detected by the flag detecting unit and outputting it to the outside. An automatic speed detecting device in an FSK modem. 2. A packet signal which is constructed based on a predetermined transmission control procedure and which is FSK-modulated and input is demodulated, and the demodulated signal is decoded based on the predetermined transmission control procedure and output. In the FSK modem, a decoding means for decoding the demodulated signal is provided corresponding to a bit transmission rate that can be input from the outside, and output signals of the plurality of decoding means are input to the predetermined unit. A flag detecting means for detecting a flag code based on the transmission control procedure, and an output selecting means for selecting an output signal of the decoder means in which the flag code is detected by the flag detecting means and outputting the signal to the outside. An FSK modem comprising an automatic speed detecting device.