JPH09102630A - Ii-vi compound semiconductor light emitting device and semiconductor surface emitting laser - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve an in-plane uniformity in luminous intensity, and obtain a light emitting device in a blue green region which has a high luminous efficiency and long life, by forming a window for light emission which is so formed that a semiconductor substrate and a part of a semiconductor light emitting device are eliminated from the semiconductor substrate as far as an etching.stop layer. SOLUTION: In order to form a light leading-out window, a titanium/gold electrode 26 is circularly etched with gold etching solution and buffer hydrofluoric acid by using photolithography techique. An N-type GaAs substrate 18 and a ZnSe buffer layer 19 in the window part are etched. Since the etching rate of etching solution to a Znx Cd1-x S (1<=x<=1) layer 20 as the etching-stop layer is low, the etching automatically stops when the Znx Cd1-x S layer 20 is exposed. Thereby the light leading-out window is formed. By adopting the etching.stop layer, controllabity can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a II-VI group semiconductor light emitting device and a semiconductor surface emitting laser.

[0002]

2. Description of the Related Art In a light emitting device using a II-VI semiconductor in the blue-green region (wavelength 480 to 520 nm), GaAs having a close lattice constant has conventionally been used as a substrate. Since the forbidden band width of GaAs is 1.43 eV (wavelength 870 nm) at room temperature, light in the blue-green region having a shorter wavelength than this is Ga.
It is absorbed by the As substrate. Therefore, in the above light emitting device, the emitted light is taken out mainly by the following two methods.

The first method is a method of emitting light from the surface side (hereinafter referred to as the upper surface) of the II-VI group semiconductor laminated structure epitaxially grown on the substrate (top emitting method). FIG. 1 shows a schematic structure of a conventional semiconductor light emitting device using an n-type GaAs substrate. In the figure, 1 is an n-type GaAs substrate, 2 is an n-type low resistance ZnSe buffer layer, 3 is n-type Zn
MgSSe carrier confinement layer, 4 is non-doped ZnC
dSe single quantum well active layer, 5 p-type ZnMgSSe carrier confinement layer, 6 ZnSe / ZnTe superlattice contact layer, 7 palladium / gold electrode, 8 gold / germanium electrode, and 9 a light extraction window. . Thus, when the n-type GaAs substrate is used, p-type ZnMg
Due to the high resistance of the SSe carrier confinement layer, ZnTe
A system contact layer is required. However, since the bandgap of ZnTe is 2.26 eV (wavelength 550 nm),
Most of the light emission in the blue-green region is absorbed in the contact layer. Therefore, in the top emission method, the light extraction efficiency becomes poor. Furthermore, in this structure, since the II-VI group semiconductor laminated structure side cannot be mounted on the heat sink downward, the efficiency of heat radiation from the device is poor. In addition, p-type Ga
Even when an As substrate is used, a top-emission type light emitting diode having a structure similar to that of FIG. 1 can be manufactured. In this case, since the n-type ZnSSe layer having a low resistance is used instead of the ZnSe / ZnTe superlattice contact layer of 6, light absorption is small. However, for the same reason as for the n-type substrate,
The efficiency of heat dissipation becomes poor. Furthermore, p-type GaAs and p-type II
-Since the valence band discontinuity with the group VI material is large, the operating voltage becomes high.

The second method is a method (bottom emission method) in which a hole is formed by etching on a substrate surface (hereinafter referred to as a lower surface) opposite to the side where the II-VI group semiconductor laminated structure is epitaxially grown (hereinafter referred to as a lower surface) to extract light. is there. FIG. 2 shows a schematic structure of a conventional semiconductor light emitting device using an n-type GaAs substrate.
In the figure, 10 is an n-type GaAs substrate, 11 is an n-type low resistance Zn
Se buffer layer, 12 n-type ZnMgSSe carrier confinement layer, 13 undoped ZnCdSe single quantum well active layer, 14 p-type ZnMgSSe carrier confinement layer, 15 ZnSe / ZnTe superlattice contact layer, 1
Reference numeral 6 denotes a palladium / gold electrode, and 17 denotes a titanium / gold electrode provided with a circular light extraction window. The n-type GaAs substrate 10 is etched in a circular shape to extract light, but since there is no etching method with a large selection ratio between GaAs and ZnSe, II-VI is sufficient to remove GaAs in the window region. The group semiconductor layer is also considerably etched. Therefore, the thickness of the n-type ZnMgSSe carrier confinement layer 14 is distributed, and the current injection into the active layer 13 becomes non-uniform. Therefore, the current bottom emission type II
In the group VI semiconductor light emitting device, the in-plane uniformity of the emission intensity is poor. Further, since heat is locally generated, deterioration is likely to occur and the life of the element is short. In some cases, the active layer is etched and no light is emitted.

In the II-VI group semiconductor blue-green surface-emitting laser, a light extraction window is conventionally formed by etching a substrate, as in the above-mentioned bottom emission type element, and a DBR composed of a dielectric multilayer film is formed thereon. Had been placed. In this case also, since the etching selection ratio cannot be obtained, n-type ZnMgSS
e The carrier confinement layer is uneven. As a result, the flatness of the distributed Bragg reflector (DBR) formed on it deteriorates and the reflectance decreases. Further, since the resonator length is uneven, it does not efficiently oscillate at a single wavelength. Due to these factors, the oscillation threshold current becomes large, and at present, continuous oscillation at room temperature is not performed.

[0006]

SUMMARY OF THE INVENTION An object of the present invention is to provide a blue-green region II-VI semiconductor light emitting device having a high luminous efficiency and a long life, which has improved in-plane uniformity of light emission intensity. .

It is another object of the present invention to provide a blue-green region II-VI semiconductor surface emitting laser having a small oscillation threshold current and capable of continuous oscillation at room temperature.

[0008]

SUMMARY OF THE INVENTION The present invention is a II-VI group semiconductor light-emitting device in the visible range for extracting light from the semiconductor substrate side, and a semiconductor substrate or DBR and a II-VI group semiconductor laminate which is a light-emitting region. Between the structure and Zn _x Cd
_The basic feature is to arrange a _1-x S layer (0 ≦ x ≦ 1).

That is, the semiconductor light emitting device according to the first solution of the present invention is a planar semiconductor light emitting device whose light emitting layer is a II-VI group compound semiconductor, and a semiconductor substrate on which the semiconductor light emitting device is formed. Zn _x Cd between the light emitting layers
_An etching stop layer made of _1-x S (0 ≦ x ≦ 1) is arranged, and a part of the semiconductor substrate and the semiconductor light emitting device is removed from the semiconductor substrate to the etching stop layer. It is characterized in that the formed window for emitting light is provided.

A semiconductor light emitting device according to a second solving means of the present invention is the semiconductor light emitting device according to the above first solving means, wherein one of a pair of electrodes for current injection is formed on a surface of the semiconductor light emitting device. From the top of the insulating film that has an opening,
Alternatively, the semiconductor light emitting device is characterized in that it is formed from above a semiconductor layer having a conductivity type different from that of the outermost surface layer of the semiconductor light emitting device and formed on the surface of the semiconductor light emitting device and having an opening.

A semiconductor surface emitting laser according to a third solution of the present invention is a semiconductor surface emitting laser in which the light emitting layer is a II-VI group compound semiconductor, and the semiconductor substrate on which the semiconductor light emitting element is formed and the light emitting layer. Zn _x Cd _1-x S (0
≦ x ≦ 1) is provided with an etching stop layer,
From the semiconductor substrate to the etching stop layer, a window for light emission formed so as to remove a part of the semiconductor substrate and the semiconductor light emitting element is provided, and an optical resonance of the semiconductor surface emitting laser is provided. A light reflecting film or a distributed Bragg reflecting mirror which is one of a pair of light reflecting mirrors constituting the container is formed in contact with the etching stop layer.

[0012]

BEST MODE FOR CARRYING OUT THE INVENTION ZnCdS is difficult to dissolve in an ammonia-based etching solution. For example, the etching rate for ammonia water + hydrogen peroxide water + water (mixing ratio 1:30:30) is 3300 nm / min for GaAs, Zn
Se is 100 nm / min, whereas ZnCdS is 5 nm / min, which is very slow. Therefore, ZnCds serve as an etching stop layer when the GaAs substrate is etched. That is, if the ZnCdS layer is disposed between the GaAs substrate and the laminated structure of the II-VI group semiconductor, the substrate is partially etched to form the light extraction window, and the etching is performed when the ZnCdS layer is reached from the GaAs substrate. To stop automatically. As a result, in the window area, G
The aAs substrate can be removed completely and with good reproducibility, and the stacked structure of the ZnCdS layer and the II-VI group semiconductor can be preserved in a complete form. Moreover, the remaining ZnCd
Since the band gap of the S layer is about 3 eV, the light emission in the blue to green region can be extracted to the outside with almost no absorption. Thus, by using the ZnCdS layer,
As compared with the conventional bottom emission type light emitting device, a bottom emission type light emitting device having a smaller carrier confinement layer thickness distribution can be easily obtained with good reproducibility. This makes the injection of current into the active layer uniform and improves the in-plane uniformity of emission intensity. Further, since the current injection is uniform, the element is less likely to deteriorate, and the element has a longer life than the conventional one. Moreover,
Since the heat generation due to current concentration is small, the luminous efficiency is also good. Further, in the surface emitting laser, the flatness of the DBR is improved and the reflectance is increased by reducing the distribution of the carrier confinement layer thickness. Further, since the in-plane distribution of the resonator length becomes small, the resonator oscillates at a single wavelength. These effects reduce the oscillation threshold current.

[0013]

【Example】

(Embodiment 1) FIG. 3 is a sectional view for explaining a first embodiment of the present invention. This figure is a view in which the LED structure is cut parallel to the direction of current flow. The direction perpendicular to the paper is [ 11
0] direction. Element size is 500μm × 500μ
m, and the thickness is about 65 μm. The device structure and manufacturing method will be described below with reference to this drawing. 18 is an n-type GaAs substrate, 19
Is a chlorine-doped n-type ZnSe buffer layer (thickness: 50 nm,
Carrier concentration 1 × 10 ¹⁸ cm ^-3 ), 20 is n-type GaAs
Chlorine-doped n-type Zn _0.41 Cd lattice-matched to the substrate 18
_0.59 S etching stop layer (thickness 100 nm, carrier concentration 1 × 10 ¹⁸ cm ^-3 ), 21 is chlorine-doped n-type Zn _0.90 Mg _0.10 S lattice-matched to the n-type GaAs substrate 18.
_0.18 Se _0.82 carrier confinement layer (thickness 2 μm, carrier concentration 5 × 10 ¹⁷ cm ⁻³ ), 22 is a 10 nm-thick non-doped Zn _0.80 Cd _0.20 Se single quantum well active layer, 23
Is a nitrogen-doped p-type Zn _0.90 Mg _0.10 S _0.18 Se _0.82 carrier confinement layer (thickness 2 μm, carrier concentration 5 × 10 ¹⁷ cm ⁻³ ), which is lattice-matched to the n-type GaAs substrate 18, 24
Is a nitrogen-doped low resistance p-type ZnSe / ZnTe superlattice contact layer (thickness 0.2 μm, carrier concentration 1 × 10 ¹⁸ c
m ^-3 ), 25 is a p-side ohmic electrode formed by depositing palladium / gold in this order, and 26 is an n-side ohmic electrode formed by depositing titanium and gold in this order.

Device Fabrication (1) Chlorine-doped n-type ZnSe buffer layer 19 having a thickness of 50 nm is formed on an n-type GaAs substrate 18 having a thickness of 350 μm.
(Carrier concentration 1 × 10 ¹⁸ cm ⁻³ ), 100 nm thick chlorine-doped n-type Zn _0.41 Cd _0.59 S etching stop layer 20 (carrier concentration 1 × 10 ¹⁸ cm ⁻³ ), chlorine-doped n-type Zn _0.90 Mg _0.10 S _0.18 Se _0.82 Carrier confinement layer 21 (thickness 2 μm, carrier concentration 5 × 10 ¹⁷ c
m ^-3 ), non-doped Zn _0.80 Cd _0.20 S with a thickness of 10 nm
e Single quantum well active layer 22, 2 μm thick nitrogen-doped p
Type Zn _0.10 Mg _0.90 S _0.18 Se _0.82 carrier confinement layer 23 (carrier concentration 5 × 10 ¹⁷ cm ⁻³ ), thickness 0.2 μ
m nitrogen-doped low resistance p-type ZnSe / ZnTe superlattice contact layer 24 (carrier concentration 1 × 10 ¹⁸ cm ⁻³ ),
Metal-organic vapor phase epitaxy method (MOVPE method)
And continuous growth by the molecular beam epitaxy method (MBE method).

(2) The substrate side is rubbed with methanol / bromine to a thickness of about 60 μm.

(3) A palladium film having a thickness of 30 nm and a gold film having a thickness of 200 nm are continuously vapor-deposited on the p-type ZnSe / ZnTe superlattice contact layer 24 by an electron beam vapor deposition method to form a palladium / gold electrode 25.

(4) A titanium film having a thickness of 30 nm and a thickness of 40 are formed on the n-type GaAs substrate 18 by the electron beam evaporation method.
A titanium / gold electrode 26 is formed by continuously depositing a 0 nm gold film.

(5) In order to form the light extraction window, the titanium / gold electrode 26 is formed by using the photolithography technique.
Circularly etch with gold etchant and buffered hydrofluoric acid. Next, the n-type GaAs substrate 18 and the ZnSe buffer layer 19 in the window are etched with ammonia water 1: hydrogen peroxide solution 30: water 30. At this time, Zn _0.41 Cd _0.59 S
Since the etching rate of the layer 20 with respect to the etching solution is slow, the etching is automatically stopped when the Zn _0.41 Cd _0.59 S layer 20 is exposed. The diameter of the opening of the light extraction window is 350 μm.

(6) Finally, element chips are cut out from the wafer by cleavage.

Device Characteristics Current-optical output (IL) characteristics at room temperature when a device having the cross-sectional structure of FIG. 3 is mounted on a silicon heat sink by using a lead-tin eutectic alloy with junction down. It is represented by the curve (a) of No. 4. When the injection current was 5.0 mA and the voltage was 3.1 V, the maximum optical output of 750 μW was obtained. The external quantum efficiency is 6.2%. The central wavelength of light emission is 5
It was around 00 nm. On the other hand, ZnCdS shown in FIG.
When the characteristics of the conventional semiconductor light emitting device having no etching stop layer were examined, the IL characteristics represented by the curve (b) of FIG. 4 were obtained at room temperature. The structure of each layer except the ZnCdS layer is the same as that of the element of FIG. Injection current 5.0m
The optical output and the external quantum efficiency at A are 544 each.
μW, 4.5%, which is about 30% compared to the device of the present invention
small.

Next, the changes over time in the optical output of the semiconductor light emitting device of the present invention and the conventional semiconductor light emitting device at room temperature are shown by curves (a) and (b) in FIG. 5, respectively. All devices were measured under a constant current condition of 3 mA. The life defined by the time at which the light output is 1 / e of the initial value is about 700 hours in the conventional device, whereas the life of the device of the present invention is dramatically extended to 3500 hours.

These element characteristics are improved by etching.
This is because the thickness of the n-type carrier confinement layer is made uniform by introducing the stop layer. By making the carrier confinement layer thickness uniform, the current injection into the active layer also becomes uniform. As a result, deterioration was less likely to occur and the life of the device was longer than that of the conventional device. Further, since the heat generation due to the current concentration is small, the luminous efficiency is also improved.

Further, in the above-mentioned embodiment, the example of the light emitting diode (LED) having the double hetero structure is shown, but it is also applicable to the semiconductor light emitting device having the homojunction structure, the separate confinement hetero structure or the improved structure thereof. The effects of the present invention can be obtained by using the same etching stop layer.

Note that the titanium / gold electrode 26 on the substrate side does not necessarily have to be taken from the back surface of the substrate, and after removing a part of the light emitting element formed on the substrate up to the n-type GaAs substrate 18, the substrate that appears on the front surface. You may form in a part.

(Embodiment 2) FIG. 6 is a diagram for explaining a second embodiment of the present invention. This figure is a view in which the LED structure is cut parallel to the direction of current flow. The direction perpendicular to the paper surface is the [1 1 0] direction. Element size is 500 μm x 5
The thickness is 00 μm and the thickness is about 65 μm. The device structure and manufacturing method will be described below with reference to this drawing. 27 is an n-type GaAs substrate, 28 is a chlorine-doped n-type ZnSe buffer layer (thickness 5
0 nm, carrier concentration 1 × 10 ¹⁸ cm ⁻³ ), 29 is chlorine-doped n-type Zn lattice-matched to the n-type GaAs substrate 27
_0.41 Cd _0.59 S etching stop layer (thickness 100n
m, carrier concentration 1 × 10 ¹⁸ cm ⁻³ ), 30 is n-type Ga
Chlorine-doped n-type Zn _0.90 M lattice-matched to As substrate 27
g _0.10 S _0.18 Se _0.82 Carrier confinement layer (thickness 2μ
m, carrier concentration 5 × 10 ¹⁷ cm ⁻³ ), 31 is thickness 10
nm non-doped Zn _0.80 Cd _0.20 Se single quantum well active layer, 32 is a nitrogen-doped p-type Zn _0.90 Mg _0.10 S _0.18 Se _0.82 carrier confinement layer (thickness 2 μm, carrier concentration 5 ×) that lattice-matches the n-type GaAs substrate 27. 10 ¹⁷ c
m ^-3 ), 33 is nitrogen-doped low resistance p-type ZnSe / ZnT
e Superlattice contact layer (thickness 0.2 μm, carrier concentration 1 × 10 ¹⁸ cm ⁻³ ), 34 is a silicon oxide insulating layer for current confinement, and 35 is a p-side ohmic electrode in which palladium / gold is deposited in this order. , 36 are n-side ohmic electrodes formed by depositing titanium and gold in this order.

Device fabrication (1) Chlorine-doped n-type ZnSe buffer layer 28 having a thickness of 50 nm is formed on an n-type GaAs substrate 27 having a thickness of 350 μm.
(Carrier concentration 1 × 10 ¹⁸ cm ^-3 ), 100 nm thick chlorine-doped n-type Zn _0.41 Cd _0.59 S etching stop layer 29 (carrier concentration 1 × 10 ¹⁸ cm ^-3 ), chlorine-doped n-type Zn _0.90 Mg _0.10 S _0.18 Se _0.82 Carrier confinement layer 30 (thickness 2 μm, carrier concentration 5 × 10 ¹⁷ c
m ^-3 ), non-doped Zn _0.80 Cd _0.20 S with a thickness of 10 nm
e Single quantum well active layer 31, 2 μm thick nitrogen-doped p
Type Zn _0.10 Mg _0.90 S _0.18 Se _0.82 carrier confinement layer 32 (carrier concentration 5 × 10 ¹⁷ cm ⁻³ ), thickness 0.2 μ
m nitrogen-doped low resistance p-type ZnSe / ZnTe superlattice contact layer 33 (carrier concentration 1 × 10 ¹⁸ cm ⁻³ ),
The MOVPE method and the MBE method continuously grow in this order.

(2) In order to form a current injection region on the p-electrode side, a photolithography technique is used to obtain a diameter of 30 μm.
The ZnSe / ZnTe superlattice contact layer 33 is etched, leaving the circular contact region.

(3) p-type Zn _0.90 Mg _0.10 S _0.18 Se
_A 0.5 μm thick SiO ₂ current confinement layer 34 is formed on the _0.82 carrier confinement layer 32 and the circular contact region 33 by the RF magnetron sputtering method.

(4) Using the photolithography technique,
Silicon oxide film (SiO ₂ ) directly on the contact region 33
The current confinement layer 34 is etched into a circle (diameter 25 μm).

(5) The substrate side is rubbed with methanol / bromine to a thickness of 60 μm.

(6) A palladium film having a thickness of 30 nm and a gold film having a thickness of 200 nm are continuously vapor-deposited on the SiO ₂ current confinement layer 34 by an electron beam vapor deposition method to form a palladium / gold electrode 35.

(7) A titanium film having a thickness of 30 nm and a gold film having a thickness of 400 nm are continuously vapor-deposited on a GaAs substrate by an electron beam evaporation method to form a titanium / gold electrode 36.

(8) In order to form the light extraction window, the titanium / gold electrode 36 is formed by photolithography.
Circularly etch with gold etchant and buffered hydrofluoric acid. Next, the n-type GaAs substrate 27 and the ZnSe buffer layer 28 in the window are etched with ammonia water 1: hydrogen peroxide solution 30: water 30. At this time, Zn _0.41 Cd _0.59 S
Since the etching rate of the layer 29 with respect to the etching solution is slow, the etching is automatically stopped when the Zn _0.41 Cd _0.59 S layer 29 is exposed. The diameter of the opening of the light extraction window is 350 μm.

(9) Finally, element chips are cut out from the wafer by cleavage.

Element Characteristics Next, the element characteristics at room temperature when the element having the structure of FIG. 6 is mounted on a silicon heat sink with a lead-tin eutectic alloy by junction down are shown in. Maximum optical output 800μ when injection current is 4.5mA and voltage is 3.1V
W was obtained. The external quantum efficiency is 7.3%. The central wavelength of light emission was around 500 nm. As shown in the first embodiment, p is directly formed on the light emitting layer without passing through the through hole of the insulating film.
The external light emission efficiency is 1.1% higher than that of the element having electrodes. Further, the life under the constant current condition of 3 mA is as long as 4000 hours. The improvement of the light emission efficiency is due to the fact that the ineffective light emission that could not be extracted to the outside can be suppressed as a result of limiting the current injection region to be smaller than the area of the light extraction window by the insulating film. Further, the improvement of luminous efficiency reduces extra heat generation and prolongs the life.

Further, in the above embodiment, the through hole of the insulating film is used for constricting the current, but the present invention can also be realized by using the through hole of the semiconductor layer having the conductivity type opposite to that of the semiconductor layer forming the electrode. The effect of is obtained.

(Third Embodiment) FIG. 7 is a diagram for explaining a third embodiment of the present invention. This figure is a view obtained by cutting the semiconductor surface emitting laser structure in parallel with the direction of current flow. The direction perpendicular to the paper surface is the [1 1 0] direction. Element size is 1
The size is 00 μm × 100 μm and the thickness is about 65 μm. The device structure and manufacturing method will be described below with reference to this drawing. 37 is an n-type GaAs substrate, 38 is a chlorine-doped n-type ZnSe buffer layer (thickness 50 nm, carrier concentration 1 × 10 ¹⁸ cm ⁻³ ),
Numeral 39 is a chlorine-doped n-type Zn _0.41 Cd _0.59 S etching stop layer (thickness 100 nm, carrier concentration 1 × 10 ¹⁸ cm ^-3 ), which lattice-matches the n-type GaAs substrate 37, and 40 lattice-matches the n-type GaAs substrate 37. Chlorine-doped n-type Z
n _0.90 Mg _0.10 S _0.18 Se _0.82 carrier confinement layer (thickness 2 μm, carrier concentration 5 × 10 ¹⁷ cm ⁻³ ), 41 is 6
Periodic non-doped Zn _0.80 Cd _0.20 Se / ZnSe single quantum well active layer, 42 is nitrogen-doped p-type Zn _0.90 Mg _0.10 S _0.18 Se _0.82 lattice-matched to the n-type GaAs substrate 37.
Carrier confinement layer (thickness 2 μm, carrier concentration 5 × 1
0 ¹⁷ cm ⁻³ ), 43 is nitrogen-doped low resistance p-type ZnSe /
ZnTe superlattice contact layer (thickness 0.2 μm, carrier concentration 1 × 10 ¹⁸ cm ⁻³ ), 44 is a silicon oxide insulating layer for current confinement, 45 is a p-side ohmic electrode in which palladium / gold is deposited in this order. , 46 is an n-side ohmic electrode formed by depositing titanium and gold in this order, and 47 is a silicon oxide film / titanium oxide dielectric DBR (reflectance of 98 for 5 cycles).
%), 48 is a silicon oxide film / titanium oxide film dielectric DBR (reflectance 99.7%) of 8 cycles.

Device Production (1) Chlorine-doped n-type ZnSe buffer layer 38 having a thickness of 50 nm is formed on an n-type GaAs substrate 37 having a thickness of 350 μm.
(Carrier concentration 1 × 10 ¹⁸ cm ^-3 ), 100 nm thick chlorine-doped n-type Zn _0.41 Cd _0.59 S etching stop layer 39 (carrier concentration 1 × 10 ¹⁸ cm ^-3 ), chlorine-doped n-type Zn _0.90 Mg _0.10 S _0.18 Se _0.82 Carrier confinement layer 40 (thickness 2 μm, carrier concentration 5 × 10 ¹⁷ c
m ^-3 ), non-doped Zn _0.80 Cd _0.20 S with a thickness of 10 nm
e Single quantum well active layer 41, 2 μm thick nitrogen-doped p
Type Zn _0.10 Mg _0.90 S _0.18 Se _0.82 carrier confinement layer 42 (carrier concentration 5 × 10 ¹⁷ cm ⁻³ ), thickness 0.2 μ
m nitrogen-doped low resistance p-type ZnSe / ZnTe superlattice contact layer 43 (carrier concentration 1 × 10 ¹⁸ cm ⁻³ ),
Continuous growth is performed in this order by MOVPE or MBE.

(2) In order to form a current injection region on the p-electrode side, a photolithography technique is used to obtain a diameter of 20 μm.
The ZnSe / ZnTe superlattice contact layer 43 is etched, leaving the circular contact region.

(3) p-type Zn _0.90 Mg _0.10 S _0.18 Se
_A 0.5 μm thick SiO ₂ current confinement layer 44 is formed on the _0.82 carrier confinement layer 42 and the circular contact region 43 by the RF magnetron sputtering method.

(4) Using the photolithography technique,
The SiO ₂ current confinement layer directly above the contact region 43 is etched into a circle (diameter 15 μm).

(5) Using the photolithography technique,
The center of the contact region 43 is etched to have a circular shape of 10 μm).

(6) A silicon oxide film / titanium oxide dielectric DBR 48 of 8 cycles is formed by the RF magnetron sputtering method without removing the photoresist used in the etching of (5). After that, the dielectric DBR 48 deposited on the resist is removed by lift-off.

(7) The substrate side is rubbed with methanol / bromine to a thickness of 60 μm.

(8) A palladium film having a thickness of 30 nm and a gold film having a thickness of 200 nm are continuously vapor-deposited on the SiO ₂ current confinement layer 44 by an electron beam vapor deposition method to form a palladium / gold electrode 45.

(9) A titanium film having a thickness of 30 nm and a thickness of 40 are formed on the n-type GaAs substrate 37 by the electron beam evaporation method.
A 0 nm gold film is continuously vapor deposited to form a titanium / gold electrode 46.

(10) Titanium / gold electrode 46 is formed by using photolithography technique to form a light extraction window.
Are circularly etched with gold etchant and buffered hydrofluoric acid. Next, the n-type GaAs substrate 37 of the window and ZnS
e buffer layer 38 with ammonia water 1: hydrogen peroxide water 3
0: Etching with water 30 At this time, Zn _0.41 Cd
_{Since the} etching rate of the _0.59 S layer 39 with respect to the etching solution is slow, the etching is automatically stopped when the Zn _0.41 Cd _0.59 S layer 39 is exposed. The diameter of the opening of the light extraction window is 30 μm.

(11) A silicon oxide film / titanium oxide dielectric DBR 47 of 5 cycles is formed by the RF magnetron sputtering method without removing the photoresist used in the etching of (10). After that, the dielectric DBR deposited on the resist is removed by lift-off.

(12) Finally, element chips are cut out from the wafer by cleavage.

Device Characteristics FIG. 8 shows current-light output (IL) characteristics at 77K when the device having the structure of FIG. 7 is mounted on a silicon heat sink by junction down using a lead-tin eutectic alloy.
Is represented by the curve (a). The threshold current of pulse oscillation is 1.
It was 5 mA. Further, even at room temperature, the threshold current 35
Pulse oscillation was observed at mA. On the other hand, when the characteristics of the conventional surface emitting laser having no ZnCdS etching stop layer were investigated, IL shown by the curve (b) in FIG.
The characteristics were obtained. The structure of each layer excluding the ZnCdS layer is the same as that of the device of FIG. In this case, the oscillation threshold current was 10.4 mA, which is about seven times that of the device of the present invention. This device did not oscillate at room temperature. Such a reduction in the threshold current is due to the fact that the unevenness of the surface generated during the etching of the light extraction window is reduced by the insertion of the ZnCdS layer, the flatness of the DBR is improved, and the reflectance is improved. Is.

The peaks (a) and (b) in FIG. 9 show the emission spectra of the device having the structure shown in FIG. 7 and the conventional device having no ZnCdS etching stop layer at a threshold current or more. . In the device having the ZnCdS layer, oscillation at a single wavelength is observed.
It can be seen that the element having no S layer oscillates at a plurality of wavelengths due to the resonator length distribution due to uneven etching.
In the device of the present invention, the oscillation occurs at a single wavelength, so that the efficiency of light emission is improved, and as a result, the threshold current is also reduced.

The distributed Bragg reflector (DBR) 47
Instead of this, a light reflecting mirror made of an insulating film and a metal film may be used.

[0053]

As described above, in the present invention, II-VI in the visible range where light is extracted from the substrate side.
In forming a group III semiconductor light emitting device, Zn _x Cd is formed between the substrate and the II-VI group semiconductor laminated structure which is the light emitting region.
_1-x S (0 ≦ x ≦ 1) is arranged as an etching stop layer. By adopting this etching stop layer, the controllability of the etching for forming the light extraction window is improved, and the in-plane uniformity of the thickness of the n-type carrier confinement layer is improved. From this, the present invention has an effect that a II-VI group semiconductor light emitting device in the blue-green region having high light emission efficiency and long life can be easily obtained. Further, when the ZnCdS etching stop layer is used in the semiconductor surface emitting laser, the controllability of the etching of the light extraction window is similarly improved. Therefore, the flatness of the DBR on the substrate side is improved,
The reflectance is improved. Furthermore, the in-plane distribution of the cavity length is reduced, and oscillation at a single wavelength is possible. Due to these effects, the present invention can reduce the threshold current in the blue-green region II-VI group surface emitting laser.

[Brief description of the drawings]

FIG. 1 is a perspective view of a conventional top-emitting semiconductor light emitting device structure using an n-type GaAs substrate.

FIG. 2 is a perspective view of a conventional bottom emission semiconductor light emitting device structure using an n-type GaAs substrate.

FIG. 3 is a cross-sectional view of the semiconductor light emitting device of the present invention cut in parallel with the direction of current flow.

FIG. 4 is an IL characteristic diagram of the semiconductor light emitting device of the present invention and the conventional semiconductor light emitting device.

FIG. 5 is a characteristic diagram showing temporal changes in optical output at room temperature (constant current condition of 3 mA) of the semiconductor light emitting device of the present invention and the conventional semiconductor light emitting device.

FIG. 6 is a cross-sectional view showing a structure of a semiconductor light emitting device of the present invention in which an electrode is formed on a p-type semiconductor layer through a through hole made of an insulating film.

FIG. 7 is a cross-sectional view of the semiconductor surface emitting laser of the present invention cut in parallel with the direction of current flow.

FIG. 8 is an IL characteristic diagram of a semiconductor surface emitting laser of the present invention and a conventional semiconductor surface emitting laser.

FIG. 9 is an emission spectrum diagram of a semiconductor surface emitting laser of the present invention and a conventional semiconductor surface emitting laser at a current equal to or higher than an oscillation threshold.

[Explanation of symbols]

1 n-type GaAs substrate 2 n-type low resistance ZnSe buffer layer 3 n-type ZnMgSSe carrier confinement layer 4 undoped ZnCdSe single quantum well active layer 5 p-type ZnMgSSe carrier confinement layer 6 ZnSe / ZnTe superlattice contact layer 7 palladium / gold electrode 8 Gold / germanium electrode 9 Light extraction window 10 n-type GaAs substrate 12 n-type ZnMgSSe carrier confinement layer 13 undoped ZnCdSe single quantum well active layer 14 p-type ZnMgSSe carrier confinement layer 15 ZnSe / ZnTe superlattice contact layer 16 palladium / gold electrode 17 Titanium / gold electrode 18 n-type GaAs substrate 19 chlorine-doped n-type ZnSe buffer layer 20 chlorine-doped n-type Zn _0.41 Cd _0.59 S etching
Stop layer 21 Chlorine-doped n-type Zn _0.90 Mg _0.10 S _0.18 Se _0.82
Carrier confinement layer 22 Non-doped Zn _0.80 Cd _0.20 Se Single quantum well active layer 23 Nitrogen-doped p-type Zn _0.90 Mg _0.10 S _0.18 Se _0.82
Carrier confinement layer 24 Nitrogen-doped low resistance p-type ZnSe / ZnTe superlattice contact layer 25 Palladium / gold electrode (p-side ohmic electrode) 26 Titanium / gold electrode (n-side ohmic electrode) 27 n-type GaAs substrate 28 Chlorine-doped n-type ZnSe Buffer layer 29 Chlorine-doped n-type Zn _0.41 Cd _0.59 S etching
Stop layer 30 Chlorine-doped n-type Zn _0.90 Mg _0.10 S _0.18 Se _0.82
Carrier confinement layer 31 Non-doped Zn _0.80 Cd _0.20 Se Single quantum well active layer 32 Nitrogen-doped p-type Zn _0.90 Mg _0.10 S _0.18 Se _0.82
Carrier confinement layer 33 Nitrogen-doped low resistance p-type ZnSe / ZnTe superlattice contact layer (contact region) 34 Silicon oxide film current confinement layer (silicon oxide film insulating layer) 35 Palladium / gold electrode (p-side ohmic electrode) 36 Titanium / gold Electrode (n-side ohmic electrode) 37 n-type GaAs substrate 38 chlorine-doped n-type ZnSe buffer layer 39 chlorine-doped n-type Zn _0.41 Cd _0.59 S etching
Stop layer 40 Chlorine-doped n-type Zn _0.90 Mg _0.10 S _0.18 Se _0.82
Carrier confinement layer 41 Non-doped Zn _0.80 Cd _0.20 Se / ZnSe single quantum well active layer 42 Nitrogen-doped p-type Zn _0.90 Mg _0.10 S _0.18 Se _0.82
Carrier confinement layer 43 Nitrogen-doped low resistance p-type ZnSe / ZnTe superlattice contact layer (contact region) 44 Silicon oxide film current confinement layer (silicon oxide film insulating layer) 45 Palladium / gold electrode (p-side ohmic electrode) 46 Titanium / gold Electrode (n-side ohmic electrode) 47, 48 Silicon oxide film / titanium oxide film Dielectric DB
R

Claims (3)

[Claims] 1. A planar semiconductor light emitting device, wherein the light emitting layer is a II-VI group compound semiconductor, wherein Zn _x Cd _{1-x is provided} between the semiconductor substrate on which the semiconductor light emitting device is formed and the light emitting layer.
An etching stop layer made of S (0 ≦ x ≦ 1) is arranged and formed so as to remove a part of the semiconductor substrate and the semiconductor light emitting device from the semiconductor substrate to the etching stop layer. A semiconductor light-emitting device having a window for emitting light. 2. The semiconductor light emitting device according to claim 1, wherein one of a pair of electrodes for current injection is formed on an insulating film having an opening formed on the surface of the semiconductor light emitting device or on the semiconductor light emitting device. A semiconductor light emitting device having a conductivity type different from that of the outermost surface layer and formed on a semiconductor layer having an opening formed on the surface of the semiconductor light emitting device. 3. A semiconductor surface emitting laser whose light emitting layer is a II-VI group compound semiconductor, wherein Zn _x Cd _{1 -x} S is provided between the light emitting layer and a semiconductor substrate on which a semiconductor light emitting element is formed.
An etching stop layer made of (0 ≦ x ≦ 1) is arranged, and light formed so as to remove a part of the semiconductor substrate and the semiconductor light emitting element from the semiconductor substrate to the etching stop layer. An emission window is provided, and a light reflection film or a distributed Bragg reflection mirror, which is one of a pair of light reflection mirrors forming an optical resonator of the semiconductor surface emitting laser, is formed in contact with the etching stop layer. A semiconductor surface emitting laser characterized in that