JPH09102589A - Semiconductor device having capacitor and manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To further increase an effective surface area per unit projected area than a conventional record node electrode by providing a single or a plurality of fins extending mutually separated in the horizontal direction on the surface of the columnar side of a wall body. SOLUTION: In a semiconductor device 1, an interlayer insulating film and an etch-stopper layer 6 are formed on the surface of a semiconductor substrate 2. A record node 10 is formed on the interlayer insulating film 4 and the etch- stopper layer 6 through a connecting hole 8. This record node 10 has a columnar body 12 set up from a semiconductor substrate 2, and a base body 14 extending from this columnar body 12 in the horizontal direction and a wall body 16 set up from a tip part of this base body 14 constitute a cylindrical body 15 with the bottom and the opened top. Further, a fin 18 extending from the inner wall surface of the wall body 16 inwardly in the horizontal direction is formed in the record node 10. Further, a plurality of stages of fins 18 may be provided by mutual separation in the height direction of the wall body 16.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which the storage capacity of a capacitor used in a memory cell such as a DRAM is increased, and a manufacturing method thereof.

[0002]

[Problems to be Solved by the Present Invention and Prior Art] DR
The area of a storage node as one electrode constituting a capacitor element used in a memory cell such as AM is gradually reduced as the generation progresses. However, the capacity (so-called storage capacity) required to stably read data from the memory cell and prevent soft errors does not change significantly. Therefore, how to increase the capacitance value of the capacitor per unit projected area is an important issue in promoting integration.

For one, this problem can be dealt with by increasing the height of the storage node. However, since the height of the storage node becomes a factor for producing a height difference in the chip, it is apt to be formed in the formation of wiring. Occurs. Therefore, conventionally
Development has been promoted from the viewpoint of increasing the effective surface area, and storage nodes of various shapes have been proposed. Typical examples thereof include an initial stack type (not shown), and in the recent mainstream, a fin type shown in FIG. 4 (A) and a cylindrical type shown in (B).

The present invention proposes a new electrode structure capable of further increasing the effective surface area per unit projected area as compared with the conventional recording node electrodes of these shapes, and provides a semiconductor device using the same and a manufacturing method thereof. With the goal.

[0005]

In view of the above-mentioned problems and the prior art, in order to achieve the above-mentioned object, in a semiconductor device having a capacitor of the present invention, one of the capacitor electrodes is erected from a semiconductor substrate. A pillar body, a bottom body extending laterally from the pillar body, and a wall body extending upward from a projecting end portion of the bottom body. The surface of the wall body on the pillar body side is separated from each other in the lateral direction. It is characterized in that a single or a plurality of fins extending to the above are provided.

The entire shape of this capacitor electrode can be made substantially cylindrical. In this case, another feature is that the bottom body and the wall body forming this electrode form a cylindrical body supported by a pillar body standing from the semiconductor substrate. With the capacitor electrode having such a configuration, the effective surface area per unit projected area can be made larger than in the past. For example, FIG.
Compared with the fin type of (A), in the fin type, the fins are formed to extend outward from the support columns, whereas in the case of the present invention, in addition to the support columns, a vertically long wall body that does not significantly affect the projected area. Since the wall is provided with fins, it can be roughly said that the surface area is large by the amount of the wall. Further, as compared with the cylindrical type shown in FIG. 4B, the surface area of the present invention is larger due to the presence of the fins.

A method of manufacturing a semiconductor device having a capacitor of the present invention is characterized by including at least the following eight steps (a) to (h). (A) Step of forming first conductive layer (b) After forming the first insulating layer on the formed first conductive layer, the second conductive layer and the insulating layer are singular in this order. Alternatively, a step of forming a laminated film by repeatedly laminating a plurality of times (c) a step of opening a connection hole reaching from the front surface side to the first conductive layer in the laminated film (d) a spacer layer on the opening side surface of the connection hole Forming and extending the connection hole to the surface of the semiconductor substrate (e) Separating the laminated film and the first conductive layer for each capacitor (f) Forming a third conductive layer on the entire surface Connecting the separated first conductive layer from both end sides and the separated second conductive layer from the separated end face side to the semiconductor substrate through the connection holes respectively. (G) By processing the third conductive layer, While exposing the laminated film on the surface, the third conductive layer is formed for each capacitor. Step of separating (h) Step of selectively removing the insulating layer and the spacer layer from the exposed surface side On the other hand, in order to process the laminated film at one time, a sacrifice layer is laminated instead of the second conductive layer, and after the process, The method of removing the sacrificial layer and surrounding the removed portion with the third conductive layer can also form a capacitor electrode having the same shape as described above. In this case, in the step (b) of forming the laminated film, instead of the second conductive layer, a sacrificial layer that can be simultaneously processed with the insulating layer and that can be selectively removed with respect to the insulating layer and the spacer layer is laminated. In addition, after the step (e), a step of selectively removing the sacrificial layer is provided, and in the next step (f) of connecting each conductive layer to the semiconductor substrate, the third conductive layer is replaced by the sacrificial layer. It is characterized in that a film is formed so as to fill the gap formed by the removal. This makes it easier to manufacture a semiconductor device having a capacitor.

[0008]

BEST MODE FOR CARRYING OUT THE INVENTION A semiconductor device according to the present invention will be described below in detail with reference to the drawings. As this semiconductor device, for example, a semiconductor device (for example, DRAM, FRAM, VRAM, etc.) that constitutes one memory cell by a switching MOSFET and a memory capacitor can be mentioned.

FIG. 1 is a schematic cross-sectional structural view showing a storage node as an example of one electrode constituting a capacitor of a semiconductor device of the present invention. As shown in FIG.
The PSG (phoshosilicate gla
An interlayer insulating film 4 made of ss) and an etch stopper layer 6 made of silicon nitride are formed. Although not shown in the drawing, a MOSFET, a lower electrode wiring layer, etc. are formed on the surface side of the semiconductor substrate 2 below the interlayer insulating film 4, and the surface of the semiconductor substrate 2 is isolated by LOCOS or the like. I am doing it. The etch stopper layer 6 is provided to protect the lower element side when the storage node is processed, as will be described later, and can be omitted if it is not necessary, for example, because the interlayer insulating layer 4 is sufficiently thick.

A connection hole 8 is opened in the interlayer insulating film 4 and the etch stopper layer 6, and a storage node 10 is formed through the connection hole 8. This storage node 10 has a pillar body 12 that stands upright from the semiconductor substrate 2.
A bottomed cylindrical body 15 having an open upper surface is constituted by a bottom body 14 extending laterally from the bottom body 14 and a wall body 16 standing upright from a projecting end portion of the bottom body 14.

Further, the storage node 10 of the present invention is formed with fins 18 extending laterally inward from the inner wall surface of the wall body 16. In the figure, the column body 12 extends long in the center of the cylinder, and the fins 18 face the column body 12.
The pillar 12 is preferable from the meaning of increasing the electrode surface area if it extends to the center of the cylinder as shown in the figure, but it is sufficient as long as it can support at least the bottom body 14, and is not necessarily limited to the figure. Further, the shape of the fin 18 not shown in the figure in a top view is not limited, and may be a ring plate shape connected in the circumferential direction, or may be divided into an arbitrary shape in the middle.
Furthermore, the fins 18 may be provided in a plurality of stages separated from each other in the height direction of the wall body 16.

Although not shown in the drawing, the storage node 10 is coated with a predetermined dielectric film and a plate electrode is formed to complete a capacitor. Further, an interlayer insulating film, an upper electrode wiring layer, an overcoat, etc. are formed. Next, a method of manufacturing a semiconductor device having a capacitor according to the present invention will be described in detail with reference to the drawings.

First Embodiment FIGS. 2 (A) to 2 (F) show one of the manufacturing methods of this embodiment.
FIG. 6 is a vertical cross-sectional structure diagram showing each manufacturing process of the storage node 10 exemplified in FIG. The steps, which are not shown in the figure, prior to the formation of the storage node 10 can be performed in the same manner as in a normal MOS semiconductor device.

As for a DRAM, for example, first,
A semiconductor substrate of a predetermined conductivity type composed of a silicon wafer or the like is prepared, LOCOS oxidation and a gate oxide film are formed, and then a word line and a gate electrode of a MOSFET are formed. An LDD structure MOSFET is completed through shallow ion implantation, sidewall formation, deep ion implantation, and the like. Then, the interlayer insulating layer and the etch stopper layer are formed on the entire surface.

In FIG. 2, reference numerals 4 and 6 denote an interlayer insulating layer and an etch stopper layer formed on the semiconductor substrate 2. As the interlayer insulating layer 4, for example, a PSG film is used. In this embodiment, a PSG film into which about 4.5% by weight of phosphorus (P) has been introduced is formed to a thickness of about 100 nm. In addition, the etch stopper layer 6 is, as described above,
This is to protect the MOSFET (not shown) on the lower layer side when processing the film on the upper layer side, and the material and film thickness are determined in consideration of this. In this embodiment, a silicon nitride film having a thickness of about 50 nm is formed by the CVD method.

Subsequently, as shown in FIG. 3A, a first conductive layer 14a is formed on the etch stopper layer 6. First
As the conductive layer 14a of, a polysilicon film, an α-silicon film, or the like is used. In addition, the first conductive layer 14a is
This film is the bottom body 14 of the storage node 10 in FIG. 1 and is made conductive by introducing impurities such as P. In the present embodiment, for example, an α-silicon film having a thickness of about 50 to 100 nm is formed by the CVD method. The CVD at this time is 0.3
It was carried out at 530 ° C. while introducing P of about wt%.

Further, a laminated film 22 of the second conductive layer 18a and the insulating layers 20a and 20b is formed on the first conductive layer 14a. This formation is performed by first depositing the insulating layer 20a and then repeatedly stacking the second conductive layer 18a and the insulating layer 20b in this order singly or plural times. The second conductive layer 18a is a film that becomes the fin 18 of the storage node 10 in FIG. 1, and is made conductive by introducing impurities such as P. Second conductive layer 18a in the present embodiment
Is, for example, 50 to 100, similarly to the first conductive layer 14a.
An α-silicon film having a thickness of about nm was formed by the CVD method (the same as the amount of P added and the film forming temperature). Insulating layers 20a, 20b
For example, a PSG film or the like is used.

Next, as shown in FIG. 3B, the connection hole 8 is opened relatively wide from the surface side of the laminated film 22 to the first conductive layer 14a. In this embodiment, the first opening of the connection hole 8 can be performed by using, for example, a patterned resist as a mask and a total of three devices.

Specifically, first, the upper insulating layer 20b is formed.
(PSG film) is replaced with an oxide film etching device (for example, RI
Etching is performed by using an E apparatus) using, for example, a C _X H _Y F _Z / CO based etching gas. Next first conductive layer 14
a (α-silicon film) is a so-called Poly-Si etching apparatus, for example, HBr and / or Cl ₂ and / or O ₂
System etching gas (eg
) Is used for etching. In addition, chlorine-based etching gas (for example, C
Cl ₄ , SiCl _4, etc.) and even a fluorine-based gas such as CF ₄ can be used for etching. The lower insulating layer 20a (PSG film) is also etched by the same device and gas system as the upper insulating layer 20b. The thicknesses of the insulating layers 20a and 20b described above are not limited, but as can be seen from the figure, the upper insulating layer 20b is assumed to have a thickness of, for example, 200 nm, assuming that it will be removed to some extent during the etch back.
It is set to be a little thicker.

After that, an insulating layer 21a made of, for example, a PSG film is formed on the entire surface by, for example, about 100 nm,
As shown in FIG. 5C, the spacer layer 21 is formed on the opening side surface of the connection hole 8 by performing the entire etch back from the surface side of the insulating layer 21a. Further, subsequently, the lower first conductive layer 14a, the etch stopper layer 6, the interlayer insulating layer 4 are formed.
Is opened by using a predetermined etching device so that the connection hole 8 reaches the semiconductor substrate 2.

Next, using, for example, a patterned resist as a mask, the laminated film 22 and the first conductive layer 14a are etched to separate them for each capacitor as shown in FIG. . The etching process here is also the same as in the case of FIG. However, the etching in this case is 3 with the laminated film 22.
When the device, the first conductive layer 14a is added, a total of 4 devices are used.

Thereafter, as shown in FIG. 6E, a third conductive layer 12a made of, for example, an .alpha.-silicon film having a thickness of about 100 nm is formed so as to fill the opened connection hole 8. The third conductive layer 12a is a film that will be the pillars 12 and the walls 16 of the recording node 10 in FIG. 1, and is made conductive by introducing impurities such as P. The film forming method and conditions are the same as in the case of the first conductive layer 14a. Thereby, the separated first conductive layer 14a
The (bottom body 14) is connected to the semiconductor substrate 2 through the connection holes 8 from both end sides and the second conductive layer 18a (fin 18) from the separation end face side, respectively.

Next, as shown in FIG. 6F, the entire surface is etched back until the surface of the laminated film 22 is exposed, whereby the third conductive layer 12a is separated for each capacitor. The wall body 16 is formed on the side surface thereof. After that, the insulating layer 20b, the spacer layer 21, and the insulating layer 20a are selectively removed sequentially from the exposed surface side with respect to the storage node 10 by wet etching such as hydrofluoric acid or Vapor etching, and the storage node 10 concerned.
The formation process of is completed.

After that, although not shown in particular, for example, a capacitor dielectric film such as an ONO film, a plate electrode material such as a polysilicon film to which P is added, or an α-silicon film is formed and processed into a predetermined shape to form a capacitor. To complete. Further, the manufacturing of this semiconductor device is completed through various steps such as film formation of an interlayer insulating layer, formation of an upper electrode, film formation of an overcoat film and opening of a bad window.

Second Embodiment This embodiment is shown in FIG. 1 showing the first embodiment described above.
This is an embodiment that facilitates the processing of the laminated film in the connection hole opening step of (B) and the laminated film separation step of (D). In the description here, the same components and forming methods as those of the first embodiment will be denoted by the same reference numerals and description thereof will be omitted.

FIGS. 3A to 3F are schematic sectional structural views showing respective manufacturing processes of the recording node 10 according to the second embodiment. In the present embodiment, first, in the step of forming the laminated film 22 of FIG. 7A, the second conductive layer 18a of FIG.
The sacrificial layer 30 is laminated instead of. The type of film material of the sacrificial layer 30 includes the insulating layers 20a and 20b and the spacer layer 21.
Selected in combination with. As a condition of the sacrificial layer 30, it is necessary that the sacrificial layer 30 can be simultaneously processed with the insulating layers 20a and 20b, and that the insulating layers 20a and 20b and the spacer layer 21 can be selectively removed. Specifically, when a silicon oxide film is used for the insulating layers 20a and 20b and the spacer layer 21 as a combination of film materials suitable for this condition, the sacrifice layer 30 is a silicon oxide film to which phosphorus (P) is added. Can be used. In addition, the insulating layer 2
0a, 20b and the spacer layer 21 have BPSG (boro-phosp
When a hosillcate glass) film is used, a silicon oxide film or a PSG film can be used as the sacrificial layer 30.
Generally, these films are formed by the CVD method,
There is no limitation on the source gas, for example SiH ₄ or TEOS
(Tetraethoxysilane; Si (OC ₂ H ₅ ) ₄ ) or the like is used. Also, if it is within the range satisfying the above conditions,
There is no limitation on the content of phosphorus (P) or boron (B).

Since the film materials of these combinations are all oxide film-based, in the step of opening the connection hole 8 of FIG. 3B and the step of separating the laminated film 22 of FIG.
It is possible to perform etching at a time using _X H _Y F _Z / CO-based etching gas. As a result, in the case of the first embodiment of FIG. 2, etching is performed using a total of 3 to 4 devices, whereas in the present embodiment, 1 to 2 devices are used, and the etching process becomes easier accordingly.

Further, in the present embodiment, a step of removing the sacrificial layer 30 is provided after separating the laminated film 22 in this way. FIG. 6D shows a state after the sacrifice layer 30 is removed. As described above as “combination conditions of film materials”, the sacrificial layer 30 and the other insulating films 20a and 20b.
At this time, only the sacrificial layer 30 is selectively removed because the film qualities of and are different.

Specifically, in the combination of the silicon oxide film (insulating layers 20a and 20b and the spacer layer 21) illustrated above and the silicon oxide film (sacrificial layer 30) added with phosphorus (P), for example, silicon oxide is used. When the film contains about 4.5% by weight of phosphorus, the etching rate with, for example, a hydrogen fluoride solution can be made 10 times or more slower than that of the film containing no phosphorus. In addition, the BPSG film (insulating layers 20a, 20b
Or a spacer layer 21) and a silicon oxide film or a PSG film (sacrificial layer 30) in combination, for example, boron is 5% by weight.
With BPSG containing about a certain amount, the etching rate with a buffered hydrofluoric acid solution (a mixed solution of ammonium fluoride and hydrogen fluoride) can be made extremely slower than that of a normal silicon oxide film or PSG film.

After that, in the next step of coating the third conductive layer 12a, the third conductive layer 12a wraps around the portion where the sacrificial layer 30 has been removed, as shown in FIG. 18 parts of the fins are simultaneously formed. After that,
Similar to the first embodiment, the third conductive layer 12a is separated ((F) in the figure), and then the semiconductor device 1 is completed through various steps.

[0031]

As described above, according to the semiconductor device having a capacitor and the method of manufacturing the same of the present invention, one electrode of a capacitor such as a storage node is of a conventional type such as a so-called fin type or cylindrical type. Therefore, the effective surface area per unit projected area can be further increased.

Further, unlike the conventional fin type, since the fin portion is supported by the surrounding wall body, the strength of the capacitor is improved. As a result, the occupied area of the capacitor required to obtain a desired charge (for example, accumulated charge) can be reduced and the strength can be increased, which can contribute to high integration of the semiconductor device.

Further, according to the method of manufacturing a semiconductor device having a capacitor of the present invention, it is necessary to stack several kinds of films, but since the processing can be easily performed, it is much more complicated than the conventional manufacturing method. A complicated electrode structure can be formed without going through the steps. That is, the surface area of the electrode can be increased without increasing the process cost.

[Brief description of the drawings]

FIG. 1 is a schematic sectional structural view showing a storage node as an example of one electrode constituting a semiconductor device having a capacitor according to the present invention.

FIGS. 2A to 2F are schematic cross-sectional structural views showing respective manufacturing processes of a semiconductor device having a capacitor according to the first embodiment of the present invention.

3A to 3F are schematic cross-sectional structural views showing respective manufacturing processes of a semiconductor device having a capacitor according to a second embodiment of the present invention.

FIG. 3 is a schematic cross-sectional structural view showing an example of a conventional storage node, in which (A) shows a fin type and (B) shows a cylindrical type.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 semiconductor device 2 semiconductor substrate 4 interlayer insulation layer 6 etch stopper layer 8 connection hole 10 storage node 12 pillar body 12a third conductive layer 14 bottom body 14a first conductive layer 16 wall body 18 fin 18a second conductive layer 20a , 20b, 21a Insulating layer 21 Spacer layer 22 Laminated film 30 Sacrificial layer

Claims (4)

[Claims] 1. A large number of capacitors are formed, and one electrode constituting the capacitors is provided with a pillar body standing from a semiconductor substrate, a bottom body extending in the lateral direction from the pillar body, and a standing end portion of the bottom body. In the semiconductor device having a capacitor, the semiconductor device having a capacitor in which a single or a plurality of fins extending laterally apart from each other are provided on a surface of the wall body on the support body side. apparatus. 2. The semiconductor device having a capacitor according to claim 1, wherein a bottom body and a wall body forming the electrode form a cylindrical body supported by a support body standing from a semiconductor substrate. 3. A method of manufacturing a semiconductor device having a large number of capacitors, comprising the steps of forming a first conductive layer, and forming a first insulating layer on the formed first conductive layer. A step of forming a laminated film by repeatedly laminating a second conductive layer and an insulating layer singly or plural times in this order, and connecting the laminated film to the first conductive layer from the front surface side. Forming a hole, forming a spacer layer on the opening side surface of the connection hole, and extending the connection hole to the surface of the semiconductor substrate, and separating the laminated film and the first conductive layer for each capacitor And the step of forming a third conductive layer on the entire surface, thereby separating the first conductive layer from both end sides and the second conductive layer from the separation end surface side through the connection holes, respectively. Connecting to a substrate, and By processing the layer, a step of separating the third conductive layer for each capacitor while exposing the laminated film on the surface, and a step of selectively removing the insulating layer and the spacer layer from the exposed surface side are performed. A method for manufacturing a semiconductor device having at least a capacitor. 4. The method of manufacturing a semiconductor device having a capacitor according to claim 1, wherein in the step of forming the laminated film, simultaneous processing with the insulating layer is possible instead of the second conductive layer. A sacrificial layer capable of being selectively removed is laminated on the insulating layer and the spacer layer, and a selective removing step of the sacrificial layer is provided after the step of separating the laminated film and the first conductive layer. In the step of connecting each of the conductive layers to a semiconductor substrate, the method for manufacturing a semiconductor device having a capacitor, wherein the third conductive layer is coated so as to fill a gap formed by removing the sacrificial layer.