JPH09102548A - Ic trimming circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To trim an IC by zapping an IC chip after the IC chip is assembled (by molding, etc.). SOLUTION: An IC trimming circuit is provided with a plurality of Zener diodes (30A-30C), a group of transistor switches (31A-31C) for selectively zapping the Zener diodes (30A-30C), and a group of gates (32A-32C) for transmitting control signals to the bases of the switches (31A-31C) and the gates (32A-32C) are set to nonoperating states in accordance with a trimming terminating signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a trimming circuit inside an analog IC, and more particularly to a trimming circuit for trimming by zapping after assembling (molding etc.) an IC chip.

[0002]

2. Description of the Related Art As shown in Japanese Patent Laid-Open No. 6-140512, after assembling an IC chip, I
A trimming circuit for trimming the characteristics of the circuit inside C is known. According to the publication, the internal circuit is measured after the IC is assembled, and trimming can be performed based on the result, so that accurate trimming can be performed.

FIG. 2 shows a trimming circuit for such an IC. Data and a clock are applied to pads (IC pins) (28) and (29), and a bus decoder (B2) is used.
It is decoded in 1). According to the output signal decoded by the bus decoder (B21), the switches S21 to S2
Any one of 3 is selected and closed. For example, switch S
It is assumed that only 21 is closed and the switches S22 and S23 are open. When a zapping pulse is applied to the pad P20 in this state, the pad P20, the diode Q27, the zener diode Z21, and the transistor Q2.
A current flows through the path of 4, and the Zener diode Z21 is destroyed. A current does not flow through the Zener diode Z22 and the Zener diode Z23 and remains as it is.

Therefore, the ground level is applied to the base of the transistor Q21, and the transistor Q21 is turned off. Since the power supply voltage Vcc is applied to the bases of the transistors Q22 and Q23, the transistors Q22 and Q23 are turned on. Therefore, a control signal indicating the trimming result is applied to the D / A conversion circuit (1) from the collectors of the transistors Q21 to Q23.

[0005]

However, in the trimming circuit of FIG. 2, when the trimming by zapping is completed and the IC is actually in the operating state, the bus decoder B
There is a fear that the trimming value may fluctuate if 21 malfunctions. That is, when the IC is actually in operation, ON / OFF of each adjustment switch must be determined by whether or not the Zener zap diode is short-circuited. That is, all the switches S21 to S23 need to be closed.

In this state, when the IC is actually in operation, the bus decoder B21 malfunctions, the switch S21 is opened, and the transistor Q24 is turned off, so that the power supply voltage is applied to the transistor Q21. Will end up. Then, what is originally off is turned on, and an incorrect trimming value is applied to the D / A conversion circuit (1).

[0007]

The present invention has been made in view of the above points, and a plurality of zener diodes, a transistor switch group for selectively zapping the plurality of zener diodes, and the transistor switch. A group of gates for switching whether or not to transmit a control signal to the base of the group, and the group of gates is made inoperative according to a trimming end signal.

[0008]

1 shows a trimming circuit for an IC according to the present invention. (30A) to (30C) are zener diodes to be zapping, and (31A) to (31C) are a plurality of zener diodes. Transistor switches for selectively zapping the diodes (30A) to (30C), and (32A) to (32C) that switch whether to transmit a control signal to the bases of the transistor switches (31A) to (31C). , (33)
Is a plurality of Zener diodes (30A) to (30C)
, A power supply line for applying a zapping pulse and a power supply voltage, (34A) to (34C) are comparators,
(35A) to (35C) are OR gates, (36) is a D / A conversion circuit for converting a digital signal indicating a trimming value into an analog signal, and (37) is an output analog signal of the D / A conversion circuit (36). And (38) performs trimming by zapping using serial bus control on the IC (39), and the controlled circuit whose circuit characteristics (for example, filter center frequency, cutoff frequency, resistance value, etc.) are controlled. Tester, (40) is pin (4) from tester (38)
1) A bus line to which data applied through (arrival to data) (a system using 2 pins of data and clock may be used), (42) is an addressing circuit for selecting and fetching necessary data for zapping from the bus line , (43)
Is a serial-parallel conversion circuit for converting serial data from the addressing circuit (42) into parallel data,
(44) includes a Zener diode (45) that is zapped in response to a trimming end signal, and outputs an "L" level control signal for deactivating the AND gates (32A) to (32C). (32A)
To (32C).

First, the data required for zapping will be measured by a tester (38) before zapping will be described. The IC (39) in FIG. 1 is in a state where the so-called assembly is completed and the chip is molded.
Therefore, pins are used to trim the inside of the IC (39). The tester (38) is a controlled circuit (37).
Data for trimming is generated, and the data is supplied from the pin (41) to the bus line (40) inside the IC (39) while riding on the bus line. The addressing circuit (42) determines that the data for trimming the controlled circuit (37) has arrived, and applies the data to the serial-parallel conversion circuit (43).

The serial-parallel conversion circuit (43) converts serial data into parallel data and latches it. The latched parallel data is the signal line a,
It is applied to the D / A conversion circuit (36) from b and c through the OR gates (35A) to (35C). The D / A conversion circuit (36) performs digital / analog conversion, and changes the circuit characteristic of the controlled circuit (37) according to the output analog signal. Then, the output signal indicating the circuit characteristic of the controlled circuit (37) is transmitted through the pin (46) to the tester (38).
Is applied to

The tester (38) has a controlled circuit (37).
It is determined whether or not the output signal indicating the circuit characteristic of is within a predetermined range, and if not, new data having the same direction is generated and applied to the pin (41). After that, the signal is transmitted through the same route as above. As a result of performing this operation several times, data for trimming the controlled circuit (37) is stored in the tester (38).

Next, the operation of storing the data stored in the tester (38) inside the IC (39) using the Zener diodes (30A) to (30C) will be described. Zapping of the Zener diodes (30A) to (30C) is performed by destroying one Zener diode by one zapping pulse.

Now, it is assumed that the Zener diodes (30A) and (30C) are destroyed and the Zener diode (30B) is
Suppose to make use of. At this time, the serial-parallel conversion circuit (43) holds the data of "H, L, H", and starts from the destruction of the Zener diode (30A). The serial-parallel conversion circuit (43) generates an output signal only on the signal line a, and outputs the signal lines b, c.
Does not generate an output signal. An "H" level output signal is generated on the signal line a and applied to the AND gate (32A).

On the other hand, since the control circuit (44) does not operate until the trimming end signal is applied, the transistor (47) is off. Therefore, the signal of "H" level is applied to the AND gate (32A) by the pull-down resistor (48). Therefore, AND gate (3
The output signal of 2A) becomes "H" level and is applied to the base of the transistor switch (31A).

In this state, the tester (38)
A high voltage zapping pulse capable of destroying the Zener diode (30A) is applied to the pin (49) to supply the power line (3
3) is applied. Then Zener diode (30
A current flows through A) and the transistor switch (31A), and the Zener diode (30A) is destroyed. When the Zener diode (30A) is destroyed, the Zener diode (30A) is short-circuited.

Next, a serial / parallel conversion circuit (43)
Generates an output signal only on the signal line c, and does not generate an output signal on the signal lines a and b. An "H" level output signal is generated on the signal line c and the AND gate (32
C). Then, as in the case of the signal line a,
The Zener diode (30C) is destroyed and the Zener diode (30C) is short-circuited.

As a result, the data stored in the tester (38) is transferred to the Zener diodes (30A) to (30A).
Using C), the work to store in the IC (39) is
finish. When the necessary Zener diode destruction is completed, the tester (38) finally ends with the AND gate (32
A) to (32C) are made inoperative. The purpose is
Due to malfunction of the serial-parallel conversion circuit (43), etc.
The "H" level signal is output from AND gates (32A) to (3
2C) to prevent the transistor switches (31A) to (31C) from being erroneously applied.

The operation will be described. When the destruction of the necessary Zener diode is completed, the tester (38) moves from the serial / parallel conversion circuit (43) to the control circuit (4).
A signal of "H" level is applied to 4), and then a high voltage zapping pulse is applied to the pin (49) and applied to the power supply line (33). Then Zener diode (4
5) and a current flows through the transistor (47), and the Zener diode (45) is destroyed.

This completes the preparation for mounting the IC (39) on the set and externally applying the power supply voltage to the pin (49). When the IC (39) is mounted on a set and a power supply voltage is applied to the pin (49) from the outside, it is applied to the power supply line (33). Then Zener diodes (30A), (30C) and (45)
Is short-circuited, the signals of "H, L, H" are applied to the comparators (34A) to (34C), and the signals are applied to D / via the OR gates (35A) to (35C).
It is applied to the A converter (36).

Therefore, according to the circuit of FIG. 1, the controlled circuit (37) can be controlled by the trimming obtained by zapping. Further, since the "L" level signal is applied to the AND gates (32A) to (32C) by the power supply voltage, there is no possibility that the transistor switches (31A) to (31C) will operate erroneously.

By the way, in the explanation of FIG. 1, zener diodes (30A) to (30C) are targeted for zapping.
However, it requires a relatively large current to destroy the Zener diode. For this reason, when designing the mask of the IC, it is necessary to consider so that these wiring paths can withstand a large current. Therefore, a MOS capacitor or a MIS capacitor may be used instead of the Zener diode as an object of zapping. If a voltage of dielectric breakdown voltage (5 to 10 MV / cm) or more is applied to these capacitors, a short-circuit state is created like the Zener diode described above. If it is a MOS capacitor or a MIS capacitor, a through current will flow locally, and a small current will flow.

Further, if the thickness of the oxide film or the nitride film is set to about 200 Å, the breakdown can be achieved at about 20V.

[0023]

As described above, according to the present invention, it is possible to provide a trimming circuit for an IC which is capable of trimming an assembled IC by zapping and which does not change in trimming value due to malfunction of an internal circuit of the IC. it can. Further, according to the present invention, since the MOS capacitance is used as the object of zapping instead of the Zener diode, a large current does not flow at the time of destruction, which is suitable for an IC.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a trimming circuit of an IC of the present invention.

FIG. 2 is a circuit diagram showing a conventional IC trimming circuit.

[Explanation of symbols]

 (30A) and (30C) Zener diode (31A) to (31C) Transistor switch (32A) to (32C) AND gate

Claims (4)

[Claims] 1. A plurality of Zener diodes, a transistor switch group for selectively zapping the plurality of Zener diodes, and a gate group for switching whether to transmit a control signal to the base of the transistor switch group. An IC trimming circuit, characterized in that the gate group is made inoperative according to a trimming end signal. 2. A plurality of Zener diodes, a transistor switch group for selectively zapping the plurality of Zener diodes, a gate group for switching whether to transmit a control signal to the base of the transistor switch group, and trimming. A trimming circuit for an IC, comprising: a control circuit including a Zener diode that is zapping in accordance with the end signal of 1) and applying a control signal to the gate group such that the gate group is in an inoperative state. 3. A plurality of Zener diodes, a transistor switch group for selectively zapping the plurality of Zener diodes, a gate group for switching whether to transmit a control signal to the base of the transistor switch group, and A trimming of an IC, comprising: a plurality of Zener diodes, a power supply line for applying a zapping pulse and a power supply voltage in common, and the gate group being inoperative according to a trimming end signal. circuit. 4. A plurality of MOS capacitors, a transistor switch group for selectively zapping the plurality of MOS capacitors, and a gate group for switching whether to transmit a control signal to the base of the transistor switch group. An IC trimming circuit, characterized in that the gate group is made inoperative according to a trimming end signal.