JPH09102113A - Magnetic storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To detect the change of the effective sensitivity width of a lead core and to surely prevent data destruction at the time of data writing by providing a reference clock generating means, a peak detecting circuit and a core width detecting means. SOLUTION: This device is provided with a MR head 7 having a recording medium 10 and a lead core 20 and a master lock generating/starting pattern 15 as a reference pattern and a core width detecting pattern (a first half 16-1, a latter half 16-2) are recorded. A reference clock generating means is composed of a PLL clock generating circuit 26, a master clock generating circuit 27 and a master clock generating/starting circuit 28 and starts to generates the reference clock with a timing for reading the reference pattern. A peak detecting circuit 22 detects the peak of a lead signal reading the core width detecting pattern. A core width detecting means is composed of a core width detecting timing generating circuit 23, a charge/discharge circuit 24, a differential amplifier 25, ADC 29, MPU 30 and a nonvolantile memory 31, detects the phase difference between the reference clock and the lead signal and detects the effective width of the lead core from the phase difference.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a magnetic storage device such as a magnetic disk device. As a magnetic head of a magnetic disk device, in recent years, an increasing number of devices have adopted an MR head utilizing a magnetoresistive effect (MR effect). The MR head is a new head suitable for reading information written at high recording density and essential for increasing the capacity of the device.

However, the MR head also has a troublesome characteristic which the conventional inductive head does not have.
As one of them, a phenomenon occurs in which the sensitivity of a part of the core is unsteadily lowered or the sensitivity is lost. When the phenomenon as described above occurs, the read output of the head is lowered when reading the data recorded in the user area, which causes a read error.

In addition, an embedded servo system (embedded)
servo system: In a magnetic disk drive that employs a method called servo information (a method in which servo information is embedded in the data surface of a recording medium), the same servo information is used to position the head on the track of read data. Must be read. In this case, if the characteristics of the head become abnormal, accurate position information cannot be detected,
The head cannot be positioned at the center position of the track.

Therefore, in that state, not only the data cannot be read, but there is a risk of destroying the data on the adjacent track when writing the data. For this reason, there has been a demand for the development of a detecting means for detecting a decrease in the sensitivity of the MR head.

[0005]

2. Description of the Related Art A conventional example will be described below with reference to FIGS. §1: Description of MR head ... See FIG. 13. FIG. 13 is an explanatory view of a conventional MR head. FIG. 13A is a head assembly, FIG. 13B is an enlarged view of a core slider, and FIG. FIG. 3 is an enlarged view of FIG. Hereinafter, a conventional MR head will be described with reference to FIG.

The MR head used in the magnetic disk drive is, for example, as shown in the drawing. In this example, the MR head 7 is provided at the tip of the head assembly 2. In this MR head 7, a core slider 3 is provided at the tip of the head assembly 2.
A write element (a magnetic pole and a gap of an inductive write head) WE and a read element RE composed of an MR element are provided at a predetermined distance from each other.

A coil 4 for supplying a write current is provided near the write element WE and the read element RE, and the upper core 5 is sandwiched by the coil 4.
And a lower core 6 is provided.

In the head, when writing data, the write element WE is used to write to the medium, and when reading data, the read element RE is used to read from the medium. In the following description, the read element RE will be referred to as a read core (MR element) and the write element WE will be referred to as a write core.

§2: Description of magnetic disk device FIG. 14 is an explanatory view of a conventional MR head usage state. FIG. 14A shows a normal state, and FIG. Hereinafter, FIG.
A case where the MR head is normal and a case where the MR head is abnormal will be described based on 4.

When the MR head 7 is positioned on the target track on the medium and is in the on-track state, the read core (MR element) 20 and the write core 12 of the MR head 7 are placed.
Is in the position shown in FIG. In this case, the light core 12
Has its center position at the track center position (at a symmetrical position with respect to the track center). Further, the read core (MR element) 20 is located on one track boundary side from the track center. In this state, the lead core (M
R element) 20 and write core 12 read / write normally
Lighting is possible.

However, as shown in FIG.
When the sensitivity of the element 20 is lowered and becomes abnormal, the head is misaligned. If the sensitivity of the entire core of the MR head 7 is uniformly lowered, correct data reading and head position detection can be performed by the AGC circuit. However, if the sensitivity is lowered in a part of the read core 20, the position error appears as it is in the head side position detection that cannot be corrected by the parity check or the ECC.

For example, when half the sensitivity of the lead core (MR element) 20 is lost (dotted line part in FIG. B), only 1/4 of the core width is detected as a position error. That is, when the head is located at the track center and the core width is 4 μm, it is detected as a positional error of 1 μm. In this case, since the positioning control of the MR head 7 always works so that the position error becomes zero, the positioning control unit recognizes the position deviated by 1 μm as the track center,
Read and write operations are started.

In case of read, parity check and EC
Since the correction function by C or the like works, erroneous detection of data can often be prevented, and moreover, re-reading can be performed many times, so that a fatal error is unlikely to occur. However, in the case of writing, there is a high possibility that the data on the adjacent track will be overwritten, and once overwritten, the previous data will be lost.

The reason why the sensitivity of the lead core (MR element) 20 is partially reduced is considered as follows.
That is, the write core 12 (inductive head) is present near the read core (MR element) 20. Therefore, when writing is performed by the write core 12, a high magnetic field is generated from the coil (writing coil), and this high magnetic field influences the magnetic domain structure of the read core (MR element) 20, so that a part of the magnetic domain is generated. May become unstable.

When a part of the magnetic domain of the lead core (MR element) 20 becomes unstable as described above, the lead core (MR element)
Part of the sensitivity of the element 20 is lowered, and normal reading cannot be performed. The partial decrease in sensitivity does not always occur,
It occurs with a certain probability (depending on the structure of the MR element, etc.).

§3: Other Descriptions In the conventional magnetic disk drive, not only the MR head as described above, but also the inductive head absorbs variations in individual heads and variations in signal output due to write tracks. There was an amplifier circuit that adjusts the read output by the (Auto Gain Control) circuit to a constant amplitude.

That is, a waveform having a constant amplitude and a constant pattern is written immediately before the data to be read, and the circuit is amplified so that the head output when the pattern is read becomes a constant level. Further, with respect to user data, in order to guarantee that read data is correct, a check function using parity and a correction function using ECC have been used.

[0018]

The above-mentioned prior art has the following problems. As described above, in the conventional magnetic disk device, in order to absorb the variations in the individual heads and the variations in the signal output due to the write track, the amplification circuit for adjusting the read output by the AGC circuit to a constant amplitude is provided.

That is, a waveform having a constant amplitude and a constant pattern is written immediately before the data to be read, and the circuit is amplified so that the head output when the pattern is read becomes a constant level. Further, with respect to user data, in order to guarantee that read data is correct, a check function using parity and a correction function using ECC have been used.

Therefore, even when the MR head is used,
If the sensitivity of the entire core of the MR head is uniformly lowered, correct data reading and head position detection can be performed by the AGC circuit. However, the partial sensitivity decrease of the core appears as a position error as it is in the parity check or the head side position detection that cannot be corrected by the ECC.

For example, when the sensitivity of half the core is lost, only 1/4 of the core width is detected as a position error. That is, when the head is located at the track center and the core width is 4 μm, it is detected as a positional error of 1 μm. In this case, the control always works so that the position error becomes zero, so that the position deviated by 1 μm is recognized as the track center, and the read and write operations are started.

In case of read, parity check and EC
Since the correction function by C or the like works, erroneous detection of data can be prevented in many cases, and moreover, re-reading can be performed many times, so that a fatal error is unlikely to occur. However, in the case of writing, there is a high possibility that the data on the adjacent track will be overwritten, and once overwritten, the previous data will be lost.

The present invention solves the above-mentioned conventional problems, and makes it possible to detect a change in the effective sensitivity width of the read core (MR element), thereby reliably preventing data destruction during data writing. With the goal.

[0024]

FIG. 1 is a diagram illustrating the principle of the present invention. The present invention is configured as follows to achieve the above object. In the following description, the recording medium is also simply referred to as “medium”.

(1): As shown in FIG. 1, the MR head 7 having a read core (MR element) 20 in the magnetic storage device.
Is provided, and the control unit includes an amplifier 21, a peak detection circuit 22, a core width detection timing generation circuit 23, a charge / discharge circuit 24, a differential amplifier 25, and a PLL clock generation circuit 2.
6, master clock generation start pattern detection circuit 28, master clock generation circuit 27, ADC 29, MPU 30,
A non-volatile memory 31 is provided.

A core width detection pattern composed of the first half 16-1 and the second half 16-2 is recorded on the medium 10, and the pattern is read at the time of reading to perform the core width detection process. In this case, the core width detection processing is performed by utilizing the fact that the phase difference between the master clock and the peak of the read signal from which the core width detection pattern is read changes depending on the effective core width of the read core (MR element) 20.

At the beginning of the core width detection pattern, a master clock generation start pattern 15 is written as a reference pattern indicating the beginning of the pattern, and thereby the master clock (reference clock) is started to be generated.
The front half 16-1 and the rear half 16-2 are symmetrically arranged with respect to the center line 14 of the core width detection pattern.

The magnetic storage device is constructed as follows. (2): In a magnetic storage device including a recording medium, a magnetic head having at least a read core for reading information from the recording medium, and a control unit, the recording medium is a reference pattern for detecting an effective core width of the read core. And a recording medium that records the core width detection pattern that follows,
The control unit starts the generation of a reference clock at the timing of reading the reference pattern from the recording medium, detects the phase difference between the reference clock and the read signal of the core width detection pattern, and detects the phase difference. A core width detecting means for detecting the effective core width of the lead core from the phase difference is provided.

(3): In a magnetic storage device comprising a recording medium, a magnetic head having at least a read core for reading information from the recording medium, and a controller, the recording medium is
The recording medium is composed of a reference pattern for detecting the effective core width of the lead core and a core width detection pattern following it, and the control unit generates a reference clock at the timing when the reference pattern is read from the recording medium. A reference clock generation means for starting the, a peak detection circuit for detecting the peak of the read signal that has read the core width detection pattern, a phase difference between the reference clock and the peak of the read signal is detected, and from the phase difference A core width detecting means for detecting the effective core width of the lead core is provided.

(4): In a magnetic storage device comprising a recording medium, a magnetic head having at least a read core for reading information from the recording medium, and a controller, the recording medium is
The recording medium is composed of a reference pattern for detecting the effective core width of the lead core and a core width detection pattern following it, and the control unit generates a reference clock at the timing when the reference pattern is read from the recording medium. A reference clock generation means for starting the, and a zero-cross detection circuit for detecting a zero-cross point of the signal obtained by removing the high frequency component from the read signal from which the core width detection pattern is read,
Core width detection means is provided for detecting a phase difference between the reference clock and a zero-cross point of the read signal and detecting an effective core width of the read core from the phase difference.

(5): In the magnetic storage device, the core width detecting means causes the duty pulse generating means to generate a duty pulse having a pulse width corresponding to the phase difference, and charges and discharges the capacitor based on the duty pulse. A charging / discharging circuit was provided, and the effective core width of the lead core was detected as the terminal voltage of the capacitor.

(6): In the magnetic memory device, when the core width detection pattern is divided into the first half and the second half, and the effective core width of the lead core becomes narrower than in the normal state, the phase difference in the first half is small. The patterns are symmetrically arranged in the first half and the second half so that the phase difference becomes smaller and the phase difference becomes larger in the latter half.

(7): In the magnetic storage device, when the core width detection pattern is divided into the first half and the second half, and the effective core width of the lead core becomes narrower than in the normal state, the phase difference in the first half is reduced. The patterns are symmetrically arranged in the first half and the second half so that the phase difference becomes larger and the phase difference becomes smaller in the latter half.

(8): In the magnetic memory device, the lead core is composed of a magnetoresistive effect element (MR element) utilizing the magnetoresistive effect. (Operation) The operation of the present invention based on the above configuration will be described.

Action (No. 1) In FIG. 1, the read core (MR element) of the MR head 7
The read signal a output from 20 is amplified by the amplifier 21, and then input to the peak detection circuit 22, the PLL clock generation circuit 26, and the master clock generation start pattern detection circuit 28.

At this time, the PLL clock generation circuit 26 generates the PLL clock d from the servo information and outputs it to the master clock generation circuit 27 and the master clock generation start pattern detection circuit 28. When the master clock generation start pattern detection circuit 28 detects the master clock start pattern, it outputs the master clock generation start pattern detection signal e to start the operation of the master clock generation circuit 27.

Therefore, the master clock generation circuit 27
Is a master clock f synchronized with the PLL clock d.
Is generated at a constant cycle. On the other hand, the peak detection circuit 22 detects the peak of the read signal a, and when the peak is detected, sends the phase pattern peak pulse b to the core width detection timing generation circuit 23.

Then, the core width detection timing generation circuit 2
In step 3, the phase pattern peak pulse b and the master clock f are fetched to generate the core width detection timing.
This core width detection timing is a signal for driving the transistor of the charging / discharging circuit 24, and the master clock f
Is a timing pulse with a duty pulse having a pulse width corresponding to the phase difference of the phase pattern peak pulse b with respect to.

In the charging / discharging circuit 24, the internal transistor is driven by the timing pulse to charge / discharge the capacitor. At this time, a capacitor terminal voltage corresponding to the pulse width of the duty pulse is output, the output voltage is amplified by the differential amplifier 25, converted into a digital signal by the ADC 29, and input to the MPU 30.

The MPU 30 performs a core width detection process from the input data. In this case, the MPU 30 determines whether the effective core width of the read core (MR element) 20 is normal or abnormal by comparing with the data of the correct core width stored in the non-volatile memory 31, and the result information (OK / NG) is output.

As described above, the change in the effective core width of the lead core can be reliably detected with a simple pattern.
Therefore, it is possible to prevent the data destruction of the adjacent track due to the detection of the head position error. Further, in order to guarantee the data write to the track center, it is possible to guarantee that the data can be read without offset seek, and the read error rate can be reduced.

Action (2) The configuration (4) has the following actions. Similarly, the reference clock generation means starts the generation of the reference clock at the timing when the reference pattern is read from the recording medium. Further, the zero-cross detection circuit detects the zero-cross point of the signal obtained by removing the high frequency component from the read signal when the core width detection pattern is read. Then, the core width detecting means detects the phase difference between the reference clock and the zero cross point, and detects the effective core width of the lead core from the phase difference.

With the above arrangement, the change in the core width of the lead core (MR element), that is, the effective sensitivity width of the lead core (MR element) can be reliably detected without performing the head moving operation. Therefore, it is possible to reliably prevent data destruction at the time of writing data.

[0044]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. The embodiment described below is an example applied to a magnetic disk device of the embedded servo system. It should be noted that when the sensitivity of a part of the read core (MR element) that constitutes the MR head is reduced or disappears, the core width seems to have become smaller. Therefore, in the following examples, the effective sensitivity of the read core (MR element) is reduced. The width is referred to as an effective core width, or simply a core width.

(Description of Embodiment 1) Hereinafter, Embodiment 1 will be described with reference to FIGS. The first embodiment is an example of detecting a change in the core width by using the phase difference between the master clock and the peak detection signal.

§1: Description of magnetic disk device--FIG. 2
Reference FIG. 2 is an explanatory diagram of a magnetic disk device, FIG. A is a configuration diagram of a DE, and B is an explanatory diagram of a pattern area on a medium. The magnetic disk device will be described below with reference to FIG.

A DE (disk enclosure) is provided in the magnetic disk device, and a spindle mechanism 9 is provided in this DE. The spindle mechanism 9 is provided with a plurality of magnetic disks (hereinafter also referred to as “medium”) 10. Further, the plurality of media 10 are rotationally driven by the spindle mechanism 9.

Further, the recording information is read / written to / from the medium 10.
There is a head assembly 2 for writing,
A large number of MR heads 7 are provided at the tip of the head assembly 2 in accordance with the recording surface of the medium 10. The head assembly 2 is rotationally driven by the head positioning mechanism,
The MR head 7 provided at the tip of the head assembly 2 is moved in the radial direction of the medium 10 to perform the positioning operation.

By the way, since the magnetic disk device of this embodiment employs the embedded servo system, servo information is recorded (embedded) on the data surface of the medium 10. Then, the servo information is read and the MR
Read / write is performed by positioning the head 7, but in this case, the read of servo information and the read of data are performed by the same read core (MR element).

In this case, when the sensitivity of a part of the lead core is reduced or eliminated, it seems that the core width is reduced. Therefore, in the present embodiment, a magnetic recording pattern (hereinafter referred to as a "core width detection pattern") capable of detecting the core width is written in the pattern recording area 11 between the user data and the pattern is read. Thus, the change in sensitivity of the lead core (MR element), that is, the change in core width is detected.

The writing position of the core width detection pattern may be written by providing a pattern recording area 11 in a radial pattern on the medium surface, just like the servo information in the embedded servo system, or may be written in one position per revolution. good. However, it is not possible to predict when the deterioration of the core sensitivity will occur, so it is best to place it so that it can be checked before writing data.

§2: Pattern explanation on medium ... See FIG. 3 FIG. 3 is an explanatory diagram of patterns on the medium. The pattern on the medium will be described below with reference to FIG. As described above, the core width detection pattern is recorded on the medium 10, and the pattern is read at the time of reading to perform the core width detection process. In this case, the core width is detected by utilizing the fact that the peak phase difference between the master clock and the read signal changes depending on the core width.

Therefore, in order that the phase of the peak of the read signal with respect to the master clock changes depending on the core width, each pattern 19 forming the core width detection pattern 16 has a width narrower than the core width of the read core (MR element) 20. Need to be recorded. In this example, the pattern 19 having a width ¼ that of the lead core 20 is recorded, but the core width can be detected more accurately if the pattern 19 is recorded with a narrow width.

At the beginning of the core width detection pattern 16, a master clock generation start pattern 15 is written as a special pattern indicating the beginning of the pattern, and thereby the master clock is started to be generated.

Master clock generation start pattern 15
Is a pattern (synchronization pattern) for determining the timing of the master clock generation start, and the core width detection pattern 16 is recorded following the master clock generation start pattern 15.

The core width detection pattern 16 includes the first half portion 16-1.
And the latter half 16-2, the core width detection pattern 16
The first half 16-1 and the second half 16-2 with respect to the center line 14 of
The patterns are arranged symmetrically. In this case, the first pattern group 17 and the second pattern group 18 are alternately arranged in the front half 16-1 and the rear half 16-2, respectively,
Each of the pattern groups is composed of five patterns 19.

In the first pattern group 17, all five patterns 19 are N-pole patterns (thick line patterns in the figure), and in the second pattern group 18, all five patterns 19 are S-pole patterns ( Thin line pattern in the figure). Therefore, the read signal when the first pattern group 17 is read and the read signal when the second pattern group 18 is read have opposite polarities (a positive signal and a negative signal).

Then, in both the first and second pattern groups, the five patterns 19 are respectively displaced at predetermined intervals in the illustrated X-axis and Y-axis directions, so that the front half portion 16-1 as a whole has a V-shape. , And the second half 16-2 is arranged in an “inverted V-shape” as a whole. In this way,
In the first half 16-1 and the second half 16-2, the patterns 19 of the first pattern group 17 and the second pattern group 18 are arranged symmetrically with respect to the center line 14 of the core width detection pattern.

§3: Description of control system--see FIG. 4 FIG. 4 is a device block diagram of the first embodiment. The control system of the magnetic disk device will be described below with reference to FIG.

Description of Control System Structure As described above, the magnetic disk device is provided with the MR head 7. Further, the control system of the magnetic disk device includes an amplifier 21, a peak detection circuit 22, a core width detection timing generation circuit 23, a charge / discharge circuit 24, a differential amplifier 25, and a PLL.
Clock generation circuit 26, master clock generation start pattern detection circuit 28, master clock generation circuit 27, analog / digital converter (hereinafter referred to as “ADC”) 2
9, a microprocessor unit (hereinafter referred to as “MPU”) 30, a non-volatile memory 31, etc. are provided. The functions and the like of the respective units are as follows.

(1): The amplifier 21 amplifies the read signal a read by the read core (MR element) of the MR head 7. (2): The peak detection circuit 22 detects the peak of the read signal a amplified by the amplifier 21 when the core width detection pattern 16 is read, and outputs the phase pattern peak pulse b.

(3): The PLL clock generation circuit 26 is a circuit for generating and outputting the PLL clock d from the read signal a (servo information) amplified by the amplifier 21. (4): Master clock generation start pattern detection circuit 28
Is a master clock generation start pattern 1 by inputting the read signal a amplified by the amplifier 21 and the PLL clock d.
5 is detected and a master clock generation start pattern detection signal e is output.

(5): The master clock generation circuit 27 has P
The master clock f synchronized with the PLL clock d is generated and output from the LL clock d and the master clock generation start pattern detection signal e. That is, the generation of the master clock f is started at the timing when the master clock generation start pattern 15 is detected.

(6): Core width detection timing generation circuit 23
Inputs the phase pattern peak pulse b and the master clock f, and detects the core width detection timing (charge / discharge circuit 2
Signal for driving the transistor No. 4).

(7): The charge / discharge circuit 24 turns on / off the internal transistor according to the core width detection timing generated by the core width detection timing generation circuit 23 to charge / discharge the capacitor. Then, the change in the core width of the lead core (MR element) is output as a voltage difference (capacitor terminal voltage) across the capacitor.

(8): The differential amplifier 25 includes the charge / discharge circuit 24
It amplifies the difference voltage (capacitor terminal voltage) across the capacitor output from the. (9): The ADC 29 converts the output signal of the differential amplifier 25 into a digital signal.

(10): The MPU 30 takes in the digital signal converted by the ADC 29, compares it with the data in the non-volatile memory 31 and detects the core width, and the core width is normal (OK).
Or abnormal (NG). Then, the information of the judgment result is output.

(11): The non-volatile memory 31 stores correct (normal) data having a normal core width in advance. A read-only ROM may be used as the non-volatile memory 31, but a non-volatile memory in which information can be written so that the data can be rewritten, such as an EEPROM or a battery-backed S-RA.
You may use M etc.

The PLL clock d is a clock synchronized with the rotation speed of the medium, and in a magnetic disk device, the position information of the magnetic head is generally generated from the servo information. The master clock f is synchronized with the PLL clock d, and has a mechanism capable of absorbing the rotation fluctuation of the medium.

Further, the core width detection timing generation circuit 23 inputs the phase pattern peak pulse b and the master clock f to generate a duty pulse (described later). The duty pulse is the master clock f. Phase pattern peak pulse b
It is a signal that falls at. Then, basically, it is possible to detect the change in the effective sensitivity width of the read core (MR element) (change in the core width) by the change in the pulse width of the duty pulse.

Description of Operation The operation of the control system is as follows. The read signal a output from the read core (MR element) of the MR head 7 is amplified by the amplifier 21, and then the peak detection circuit 22 and the PLL.
It is input to the clock generation circuit 26 and the master clock generation start pattern detection circuit 28.

At this time, the PLL clock generation circuit 26 generates the PLL clock d from the servo information and outputs it to the master clock generation circuit 27 and the master clock generation start pattern detection circuit 28. Further, the master clock generation start pattern detection circuit 28 uses the master clock generation start pattern 1
When 5 is detected, the master clock generation start pattern detection signal e is output and the operation of the master clock generation circuit 27 is started.

Therefore, the master clock generation circuit 27
Is a master clock f synchronized with the PLL clock d.
Is generated at a constant cycle. On the other hand, the peak detection circuit 22 detects the peak of the read signal a, and when the peak is detected, sends the phase pattern peak pulse b to the core width detection timing generation circuit 23.

Then, the core width detection timing generation circuit 2
In step 3, the phase pattern peak pulse b and the master clock f are fetched to generate the core width detection timing.
This core width detection timing is a signal for driving the transistor of the charging / discharging circuit 24, and the master clock f
It includes a duty pulse having a pulse width corresponding to the phase difference of the phase pattern peak pulse b with respect to (the details will be described later).

In the charge / discharge circuit 24, the internal transistor is driven by the signal output from the core width detection timing generation circuit 23 to charge / discharge the capacitor.
At this time, a capacitor terminal voltage corresponding to the pulse width of the duty pulse is output, the output voltage is amplified by the differential amplifier 25, converted into a digital signal by the ADC 29, and input to the MPU 30.

The MPU 30 performs a core width detection process from the input data. In this case, the MPU 30 determines whether the core width is normal or abnormal by comparing with the data of the correct (normal) core width stored in the non-volatile memory 31, and the resulting information (OK / NG) is determined. Output.

As described above, it is possible to reliably detect the change in the core width of the lead core with a simple pattern. Therefore, it is possible to prevent the data destruction of the adjacent track due to the detection of the head position error. Further, in order to guarantee the data write to the track center, it is possible to guarantee that the data can be read without offset seek, and the read error rate can be reduced.

§4: core width detection timing generation circuit,
Description of charge / discharge circuit ... See FIGS. 5 to 7. FIG. 5 is an explanatory diagram of the core width detection timing generation circuit, FIG. 6 is an explanatory diagram of the charge / discharge circuit, and FIG. 7 is a timing chart in the circuits of FIGS. Is. Hereinafter, the core width detection timing generation circuit and the charging / discharging circuit will be described with reference to FIGS.

(1): Description of Core Width Detection Timing Generation Circuit ... See FIG. 5 The core width detection timing generation circuit 23 is a circuit for generating core width detection timing, and is a flip-flop circuit (hereinafter referred to as “FF”). 35, counters 36, 37,
It is composed of inverters 38 and 39 and AND circuits 40 and 41.

In the above circuit, the input signal of the FF 35 is b, f, the output signal of the FF 35 is h, the output signal of the AND circuit 40 is AL, the output signal of the AND circuit 41 is BL, the output of the counter 36 is AH, and the counter 37. Is output as BH.

In this circuit, the phase pattern peak pulse b output from the peak detection circuit 22 is input to the reset terminal of the FF 35, and the master clock f output from the master clock generation circuit 27 is input to the set terminal. Then, the FF 35 outputs the duty pulse h.

The counter 36 has the core width detection pattern 16
It is for detecting the first half portion 16-1 of, and counts by inputting the master clock f. This counter 36
Then, a few pulses of the master clock f from the start of the transmission of the master clock f (the first pulse to the third pulse in this example)
The output AH is set to low level L (AH = L) while counting up to (while the first half portion 16-1 of the core width detection pattern passes), and the signal AH is set to high level H ( AH = H). Further, the counter 36 is reset at the rising edge of the signal BH.

The counter 37 has a core width detection pattern 16
It is for detecting the latter half 16-2 of the above, and the master clock f is input and counted. This counter 37
Then, after the counter 36 has finished counting, while the master clock f is being counted up to several pulses (in this example, the fourth pulse to the sixth pulse) (while the latter half portion 16-2 of the core width detection pattern passes through). ) Sets its output signal BH to a low level L (BH = L), and outputs the signal BH during other periods.
Is a high level H (BH = H). The counter 37 is reset at the rising edge of the signal BH.

The AND circuit 40 is a circuit which passes the duty pulse h only when the output signal of the inverter 38 is at the high level H and does not pass the duty pulse h otherwise. The AND circuit 41 is a circuit that passes the duty pulse h only when the output signal of the inverter 39 is at the high level H, and does not pass the duty pulse h otherwise.

The above circuits generate the signals AL, AH, BL, BH as core width detection timing signals and output them to the charge / discharge circuit 24. In the charging / discharging circuit 24, the signals AL, AH, BL, BH are each inverted by an inverter, and the inverted signals are applied to the bases of the internal transistors.

(2): Description of charge / discharge circuit ... See FIG. 6. The charge / discharge circuit 24 includes transistors Q1, Q2, and Q.
3, Q4 and a capacitor C. The transistors Q1 to Q4 are connected in a bridge type, and a connection point j between the transistors Q1 and Q2 and a transistor Q1 are connected.
A capacitor C is connected between the connection point k of 3 and Q4. The emitters of the transistors Q1 and Q3 are m
They are commonly connected at a point and connected to a power source of voltage V _CC .
Further, the emitters of the transistors Q2 and Q4 are commonly connected at point n, and are connected to GND (ground potential).

The inverted signal of the signal AH is applied to the base of the transistor Q1, the inverted signal of the signal AL is applied to the base of the transistor Q2, and the inverted signal of the signal BH is applied to the base of the transistor Q3. However, the inverted signal of the signal BL is applied to the base of the transistor Q4. Further, outputs (potential difference between both terminals of the capacitor C = terminal voltage of the capacitor C) are taken out from the points j and k of both terminals of the capacitor C, output to the differential amplifier 25 and amplified.

In this example, the j point is +, and the k point is −, and the capacitor C is charged when a current in the j → k direction flows, and the current flows in the opposite direction, the k → j direction. The case of flowing will be described as discharge.

(3): Description of the operation of the core width detection timing generation circuit and the charging / discharging circuit ... See FIG. 7. The core width detection timing generation circuit 2 will now be described with reference to FIG.
3 and the operation of the charging / discharging circuit 24 will be described. In FIG.
Is the master clock f, is the duty pulse h, is the signal AH and the state of the transistor Q1, is the signal BH and the state of the transistor Q3, is the signal AL and the transistor Q.
2 is the state of signal BL and transistor Q4,
Indicates the terminal voltage of the capacitor C.

In the core width detection timing generation circuit 23,
By inputting the phase pattern peak pulse b and the master clock f, the signals AL, AH, B of the core width detection timing are input.
L and BH are generated and output. Then, the charging / discharging circuit 24
Then, the signals AL, AH, BL and BH are inverted by inverters and applied to the bases of the transistors Q1 to Q4.

In this case, the AH signal is at the low level L for a fixed number of pulses (from the first pulse to the third pulse in this example) from the start of transmission of the master clock f, and the inverted signal causes The transistor Q1 is turned off (between the timings t1 and t2 when the first half portion 16-1 passes).

The signal AL of is a duty pulse h while the AH signal is at the low level L,
While the signal BH is at the low level L (the timings t2 to t when the latter half portion 16-2 passes),
3)).

Therefore, between timings t1 and t2 (while the first half portion 16-1 passes), the transistor Q1 is off, the transistor Q3 is on, the transistor Q4 is off, and the duty pulse h is at the high level H. When the transistor Q2 is turned on, Vcc → Q3 → k point →
A current flows through the route of capacitor C → point j → Q2 → GND, and capacitor C is discharged.

The duty pulse h is low level L.
Then, no current flows through the capacitor C, and the charge remains. That is, between the timings t1 and t2,
The capacitor C is intermittently discharged by the duty pulse.

On the other hand, between the timings t2 and t3 (while the latter half 16-2 passes), the transistor Q1 is on, the transistor Q3 is off, the transistor Q2 is off, and the duty pulse h is at the high level H. When the transistor Q4 is turned on, Vcc → Q1 → j point →
A current flows through the route of capacitor C → k point → Q4 → GND, and the capacitor C is charged.

The duty pulse h is low level L.
When, the electric current does not flow through the capacitor C and the electric charge remains. That is, the capacitor C is intermittently charged by the duty pulse h between the timings t2 and t3. In this way, the capacitor C repeatedly charges and discharges and outputs its terminal voltage. If you do this,
The width of the duty pulse h is output as a potential difference (terminal voltage) between both terminals of the capacitor C, and the core width can be detected.

§5: Operational explanation 1 based on timing chart (normal)-see FIG. 8 FIG. 8 is a timing chart of the first embodiment (normal). The operation of the control system circuit when the read core (MR element) is normal will be described below with reference to FIG.

In FIG. 8, is a master clock generation start pattern and core width detection pattern, is a read signal waveform, is a PLL clock (PLL CLOCK), is a master clock (MASTER CLOCK), is a duty pulse (DUTY PULSE), Indicates the capacitor terminal voltage.

In this example, it is assumed that the master clock generation start pattern 15 shown in FIG. 3 and the core width detection pattern 16 following it are recorded on the medium (see FIG. 8).

When the above-mentioned pattern on the medium is read by the read core 20 of the MR head 7, the read core (MR element)
The read signal a output from 20 becomes a signal having the waveform shown in. The signal waveform of the read signal a is reversed between positive and negative when the first pattern group 17 is read and when the second pattern group 18 is read.

The peak of the positive signal waveform of the read signal a is P
1, P2, P3, P4, P5, and P6, when the read core (MR element) 20 is normal, the peaks P1, P2, P3, P4, P5, and P6 of the positive signal waveform of the read signal a.
Occurs at substantially the center of the first pattern group 17 and the second pattern group 18. Therefore, the peak of the read signal a occurs at the same timing in both the first half 16-1 and the second half 16-2.

Further, the master clock of is generated at a constant cycle in synchronization with the PLL clock of the master clock generation start pattern 15. The duty pulse of rises in synchronization with the master clock of
Is a pulse that falls at the peaks P1 to P6 of the read signal a.

Therefore, the core width detection timing generation circuit 2
The pulse width of the duty pulse h generated in 3 depends on the phase difference φ1 of the peaks P1 to P6 of the read signal a with respect to the master clock f. Therefore, the lead core (M
If the R element) 20 is normal, the phase difference φ1 is constant, and as a result, the pulse width of the duty pulse is constant.

Then, in the charge / discharge circuit 24, the transistor is driven by the signal generated by the core width detection timing generation circuit 23 to charge / discharge the capacitor C. In this case, between the timings t1 and t2 (while passing through the first half portion 16-1), three duty pulses h having a constant pulse width are provided.
As a result, the capacitor C is discharged, and during the timing t2 to t3 (while the latter half 16-2 passes), the capacitor C is charged by three duty pulses h having a constant pulse width.

In this case, since the pulse width of the duty pulse h is constant, the discharging amount and the charging amount of the capacitor C become equal, and the capacitor terminal voltage becomes the same at the timing t1 and the timing t3. Therefore, MPU3
0 determines that the core width is normal and outputs the information (OK).

§6: Operation explanation 2 by timing chart (at the time of abnormality) (see FIG. 9) FIG. 9 is a timing chart of the first embodiment (at the time of abnormality). The operation when the lead core (MR element) becomes abnormal will be described below with reference to FIG.

Also in this example, it is assumed that the master clock generation start pattern 15 shown in FIG. 3 and the core width detection pattern 16 following it are recorded on the medium (see FIG. 9). Then, it is assumed that the lead core (MR element) 20 becomes abnormal and the effective core width is halved. When the read core (MR element) 20 of the MR head 7 reads a pattern on the medium, the read signal a output from the read core (MR element) 20 becomes a signal having the waveform shown in.

In this case, when the core width detection pattern 16 is read by the lead core (MR element) 20 whose effective core width is halved, the center of each pattern of the first pattern group 17 and the second pattern group 18 is read. The pattern 19 and part of the patterns on both sides of the pattern 19 cannot be read (the outer pattern cannot be read).

Therefore, the amplitude of the read signal a becomes small, and the phase difference of the phase pattern peak pulse b with respect to the master clock f changes. That is, the read signal a
The positions of the peaks P1 to P6 are shifted.

Now, the phase difference of the peaks P1, P2, P3 of the read signal a obtained from the first half 16-1 with respect to the master clock f is φ3, and the peaks P3, P4 of the read signal a obtained from the second half 16-2, When the phase difference of P5 with respect to the master clock f is φ4, the relationship of φ3 <φ1 <φ4 is established. That is, the phase difference φ3 becomes smaller in the first half portion 16-1 and the phase difference φ4 becomes larger in the latter half portion 16-2.

By the way, the pulse width of the duty pulse h depends on the phase difference between the master clock f and the peaks P1 to P6 of the read signal a. For this reason,
When the lead core (MR element) 20 becomes abnormal as described above, the phase difference changes (φ3 <φ1 <φ4) and the pulse width of the duty pulse h changes.

Then, in the charge / discharge circuit 24, the transistors Q1 to Q4 are driven by the signal generated by the core width detection timing generation circuit 23 to charge / discharge the capacitor C. In this case, between timings t1 and t2 (the first half 16
(While −1 passes), the electric charge of the capacitor C is discharged by the three duty pulses h, and the timing t2 to t3.
During the period (while the latter half portion 16-2 passes), the capacitor C is charged by the three duty pulses h.

Then, between the timings t1 and t2, the pulse width of the duty pulse becomes small, and the timing t
Since the pulse width of the duty pulse becomes large between 2 and t3, the charge amount of the capacitor C becomes larger than the discharge amount.

Therefore, the timing t1 and the timing t
The capacitor terminal voltages of 3 and 3 are different, and the difference voltage is V _d1 amplified by the differential amplifier 25, converted into a digital signal by the ADC 29, and input to the MPU 30. Then, the MPU 30 judges that the core width is abnormal by comparing with the data in the nonvolatile memory 31, and outputs the information (NG).

(Explanation of Second Embodiment) §1: Explanation of Control System ... See FIG. 10 FIG. 10 is a block diagram of an apparatus according to the second embodiment. Hereinafter, FIG.
Based on 0, the control system of the magnetic disk device will be described.

Description of Configuration of Control System The second embodiment is an example in which the peak detection circuit 22 of the first embodiment is replaced with a low-pass filter 45 and a zero-cross detection circuit 46, and other configurations are the same as those of the first embodiment. Is. As shown in the figure, the magnetic disk device is provided with an MR head 7.
The control system of the magnetic disk device includes an amplifier 21, a low-pass filter 45, a zero-cross detection circuit 46, a core width detection timing generation circuit 23, a charge / discharge circuit 24, a differential amplifier 25, an ADC 29, an MPU 30, and a non-volatile memory. Three
1 etc. are provided.

The low pass filter 45 includes the amplifier 21
It is a filter that removes the high-frequency component of the read signal a output from and passes only the low-frequency component. The zero-cross detection circuit 46 detects the zero-cross point of the read signal a passing through the low-pass filter 45 and outputs the zero-cross detection signal g. The other configuration is the same as that of the first embodiment.

Description of Operation The operation of the control system is as follows. The read signal a from the MR head 7 is amplified by the amplifier 21 and input to the low pass filter 45, the PLL clock generation circuit 26, and the master clock generation start pattern detection circuit 28. Also,
The signal that has passed through the low-pass filter 45 is input to the zero-cross detection circuit 46, where the zero-cross point of the read signal a is detected and the zero-cross detection pulse g is sent to the core width detection timing generation circuit 23.

When the master clock generation start pattern detection circuit 28 detects the master clock generation start pattern, it outputs a master clock generation start pattern detection signal e to start operating the master clock generation circuit 27. The master clock generation circuit 27 generates a master clock f, which is synchronized with the PLL clock d generated by the PLL clock generation circuit 26, at a constant cycle and sends it to the core width detection timing generation circuit 23.

On the other hand, the core width detection timing generation circuit 23
Then, the zero-cross detection pulse g from the zero-cross detection circuit 46 and the master clock f from the master clock generation circuit 27 are input to generate the core width detection timing,
It is sent to the charging / discharging circuit 24.

Then, similarly to the first embodiment, the charge / discharge circuit 24 drives the internal transistor at the core width detection timing to charge / discharge the capacitor. At this time, the terminal voltage of the capacitor C corresponding to the pulse width of the duty pulse h is output, the output voltage is amplified by the differential amplifier 25, converted into a digital signal by the ADC 29, and input to the MPU 30.

The MPU 30 performs a core width detection process from the input signal. In this case, the MPU 30 compares with the correct data stored in the non-volatile memory 31,
Determines whether the core width is normal or abnormal, and displays the information (OK
/ NG) is output.

§2: Description of Operation by Timing Chart ... See FIG. 11 FIG. 11 is a timing chart of the second embodiment (when an abnormality occurs). The operation of the second embodiment will be described below with reference to FIG. In FIG. 11, is a read signal waveform and is a PLL
Clock (PLL CLOCK) is the master clock (MASTER
CLOCK), is a duty pulse (DUTY PULSE),
Indicates the capacitor terminal voltage.

In this example, it is assumed that the master clock generation start pattern 15 shown in FIG. 3 and the core width detection pattern 16 following it are recorded on the medium.
When the read core (MR element) 20 of the MR head 7 reads a pattern on the medium, the read core (MR element) 20
The read signal a output from is a signal having the waveform shown in.

In this case, when the core width detection pattern 16 is read by the lead core (MR element) 20 whose effective core width is halved, the center of each pattern of the first pattern group 17 and the second pattern group 18 is read. The pattern 19 and part of the patterns on both sides of the pattern 19 cannot be read (the outer pattern cannot be read).

Therefore, as shown in the figure, the amplitude of the read signal a (solid line waveform) becomes small, and the master clock f
The phase difference of the zero cross detection signal g with respect to changes. That is, the position of the zero-cross detection signal g is displaced. In addition,
In the waveform of the read signal a, the solid line waveform is the output waveform of the amplifier 21, the dotted line waveform is the output waveform of the low-pass filter 45, and the zero-cross points of the output waveform of the low-pass filter 45 are indicated by g1 to g6. There is.

Now, when the read core (MR element) 20 is normal, the phase difference of the zero cross signal g obtained from the core width detection pattern with respect to the master clock f is set to φ5, and the effective core width of the read core (MR element) 20 is halved. In this case, the zero-cross detection signal g obtained from the first half section 16-1
The phase difference with respect to the master clock f of φ7, the latter half 16
If the phase difference of the zero-cross detection signal g obtained from -2 with respect to the master clock f is φ8, then φ7 <φ5 <φ8
It becomes a relationship.

That is, when the effective core width of the lead core (MR element) 20 becomes half, the phase difference φ7 becomes small in the first half portion 16-1 and the phase difference φ8 becomes in the second half portion 16-2.
Becomes larger.

By the way, the pulse width of the duty pulse h depends on the phase difference between the master clock f and the zero cross points g1 to g6 of the read signal a. Therefore, when the lead core (MR element) 20 becomes abnormal and the effective core width becomes half, for example, the phase difference changes (φ
7 <φ5 <φ8), and the pulse width of the duty pulse h changes accordingly.

In the charge / discharge circuit 24, the transistors Q1 to Q4 are driven by the signal generated by the core width detection timing generation circuit 23 to charge / discharge the capacitor C. In this case, between timings t1 and t2 (the first half 16
(While −1 passes), the electric charge of the capacitor C is discharged by the three duty pulses h, and the timing t2 to t3.
During the period (while the latter half portion 16-2 passes), the capacitor C is charged by the three duty pulses h.

Since the pulse width of the duty pulse h becomes smaller between the timings t1 and t2, and the pulse width of the duty pulse h becomes larger between the timings t2 and t3, the charge amount of the capacitor C is larger than the discharge amount. Become.

Therefore, the timing t1 and the timing t
The capacitor terminal voltages of 3 and 3 are different, and the difference voltage is Vd amplified by the differential amplifier 25, converted into a digital signal by the ADC 29, and input to the MPU 30. Then, the MPU 30 judges that the core width is abnormal by comparing with the data in the nonvolatile memory 31, and outputs the information (NG).

(Explanation of Third Embodiment) FIG. 12 is a timing chart of the third embodiment (at the time of abnormality). In the third embodiment, the arrangement of the core width detection pattern 16 of the first embodiment is the first half 16
-1 and the latter half part 16-2 are replaced with each other, and other configurations are the same as those in the first embodiment.

Hereinafter, based on FIG. 12, the lead core (MR
The operation when the element becomes abnormal will be described. In this example, the master clock generation start pattern 15 and the subsequent core width detection pattern 16 shown in FIG. 3 are recorded on the medium, but the core width detection pattern 16 is the first half portion 16.
-1 and the latter half 16-2 are exchanged (see FIG. 12).

It is assumed that the lead core (MR element) 20 becomes abnormal and the effective core width is halved. When the read core (MR element) 20 of the MR head 7 reads a pattern on the medium, the read signal a output from the read core (MR element) 20 becomes a signal having the waveform shown in.

In this case, when the core width detection pattern 16 is read by the lead core (MR element) 20 whose effective core width is halved, the center of each pattern of the first pattern group 17 and the second pattern group 18 is read. The pattern 19 and part of the patterns on both sides of the pattern 19 cannot be read (the outer pattern cannot be read).

Therefore, the amplitude of the read signal a becomes small and the phase difference of the phase pattern peak pulse b with respect to the master clock f changes. That is, the read signal a
The positions of the peaks P1 to P6 are shifted.

Now, let us say that the phase difference between the peaks P1 to P6 of the read signal a obtained from the core width detection pattern 16 and the master clock f when the read core (MR element) 20 is normal is φ10.

When the core width of the read core (MR element) 20 is halved, the phase difference between the peaks P1, P2, and P3 of the read signal a obtained from the first half 16-1 with respect to the master clock f is φ11. If the phase difference between the peaks P4, P5, and P6 of the read signal a obtained from the latter half section 16-2 with respect to the master clock f is φ12, then φ12
<Φ10 <φ11. That is, the first half 16-
1, the phase difference φ11 increases, and in the latter half 16-2, the phase difference φ12 decreases.

By the way, the pulse width of the duty pulse h depends on the phase difference between the master clock f and the peaks P1 to P6 of the read signal a. For this reason,
When the lead core (MR element) 20 becomes abnormal as described above, the phase difference changes (φ12 <φ10 <φ11),
The pulse width of the duty pulse h is changed.

Then, in the charge / discharge circuit 24, the transistors Q1 to Q4 are driven by the signal generated by the core width detection timing generation circuit 23 to charge / discharge the capacitor C. In this case, between timings t1 and t2 (the first half 16
(While −1 passes), the electric charge of the capacitor C is discharged by the three duty pulses h, and the timing t2 to t3.
During the period (while the latter half portion 16-2 passes), the capacitor C is charged by the three duty pulses h.

Then, the pulse width of the duty pulse h increases between the timings t1 and t2, and the pulse width of the duty pulse h decreases between the timings t2 and t3, so that the discharge amount of the capacitor C is larger than the charge amount. Become.

Therefore, the timing t1 and the timing t
The capacitor terminal voltages of 3 and 3 are different, and the voltage difference is V _d2 amplified by the differential amplifier 25, converted into a digital signal by the ADC 29, and input to the MPU 30. Then, the MPU 30 judges that the core width is abnormal by comparing with the data in the nonvolatile memory 31, and outputs the information (NG).

(Other Embodiments) The embodiments have been described above, but the present invention can be implemented as follows. (1): The capacitor of the charging / discharging circuit may have the charging and discharging directions described in the above embodiments reversed. That is, since the directions of the currents flowing through the capacitors are reversed between the first half and the second half of the core width detection pattern, charging is performed when current flows in either direction, and discharging is performed when current flows in the other direction. It should be done.

(2): The circuit of the control example can be commonly used as a conventional head position detecting circuit for detecting the head position by detecting the phase of the pattern on the medium surface. Therefore, when shared with the above circuit, it can be realized by adding only the core width detection timing generation circuit.

[0146]

As described above, the present invention has the following effects. (1): Since the change in the effective sensitivity width (core width) of the read core (MR element) that constitutes the magnetic head can be detected without moving the head, it is always possible to write a pattern on the medium. It is possible to check. Therefore, it is possible to reliably prevent data destruction and improve the reliability of the device.

(2): Since the core width is detected by the phase difference of the pattern, it can be detected even when the automatic level adjusting mechanism of the signal by the AGC circuit is working. (3): The core width detection patterns are symmetrically arranged in the first half and the second half. Then, the core width value is obtained by discharging the capacitor in the pattern of the first half, charging the capacitor in the pattern of the second half, and finally extracting the capacitor terminal voltage. By doing so, the phase difference is canceled out in the first half and the second half, so that the resolution of the core width detection can be secured even if the cycle of the PLL clock is long.

In addition to the above effects, the following effects are obtained corresponding to each claim. (4): In claim 1, the recording medium is composed of a recording medium on which the reference pattern and the core width detection pattern are recorded, and the control unit is caused to start generating the reference clock at the timing when the reference pattern is read from the recording medium. A core width detecting means for detecting a phase difference between the reference clock and a read signal obtained by reading the core width detection pattern and detecting an effective core width of the read core from the phase difference is provided.

Therefore, a change in the effective sensitivity width (core width) of the read core (MR element) constituting the magnetic head can be detected by a simple circuit without moving the head. Therefore, if you write the pattern on the medium,
It is always possible to check. Therefore, it is possible to reliably prevent data destruction and improve the reliability of the device.

(5) According to a second aspect of the present invention, the recording medium comprises a recording medium on which the reference pattern and the core width detection pattern are recorded, and the control unit includes a reference clock generating means, a peak detection circuit, and a reference clock. A core width detecting means for detecting a phase difference from the peak of the read signal and detecting an effective core width of the read core from the phase difference is provided.

Therefore, the effective sensitivity width (core width) of the read core (MR element) constituting the magnetic head is changed by using the phase difference between the reference clock and the read signal peak without moving the head. It can be detected with a simple circuit. Therefore, if the pattern is written on the medium, it is possible to always check. Therefore, it is possible to reliably prevent data destruction and improve the reliability of the device.

(6) According to a third aspect of the present invention, the recording medium is composed of a recording medium on which the reference pattern and the core width detection pattern are recorded, and the control unit includes a reference clock generating means, a zero-cross detection circuit, and the reference clock. And a core width detection means for detecting a phase difference between the zero cross point of the read signal and the effective core width of the read core from the phase difference.

Therefore, the change in the effective sensitivity width (core width) of the read core (MR element) forming the magnetic head is utilized without utilizing the head moving operation to utilize the phase difference between the reference clock and the zero cross point of the read signal. It can be detected with a simple circuit. Therefore, if the pattern is written on the medium, it is possible to always check. Therefore, it is possible to reliably prevent data destruction and improve the reliability of the device.

(7): In claim 4, the core width detecting means is
A duty pulse generating means for generating a duty pulse having a pulse width corresponding to the phase difference and a charging / discharging circuit for charging / discharging the capacitor based on the duty pulse are provided, and the effective core width of the lead core is detected as a terminal voltage of the capacitor. I did it. Therefore, the core width can be detected easily and reliably by charging / discharging the capacitor with the duty pulse.

(8): In claim 5, when the core width detection pattern is divided into the first half and the second half, and the effective core width of the lead core becomes narrower than in the normal state, the phase difference becomes small in the first half, The patterns are symmetrically arranged in the first half and the second half so that the phase difference becomes large in the second half.
Therefore, since the phase difference is canceled out in the first half and the second half,
Even if the cycle of the PLL clock is long, the resolution of core width detection can be secured.

(9) In claim 6, when the core width detection pattern is divided into the first half and the second half and the effective core width of the lead core becomes narrower than in the normal state, the phase difference becomes large in the first half. In the latter half part, the patterns are symmetrically arranged in the first half part and the second half part so that the phase difference becomes small.
Therefore, since the phase difference is canceled out in the first half and the second half,
Even if the cycle of the PLL clock is long, the resolution of core width detection can be secured.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is an explanatory diagram of a magnetic disk device according to a first embodiment.

FIG. 3 is an explanatory diagram of patterns on the medium according to the first embodiment.

FIG. 4 is a device block diagram of the first embodiment.

FIG. 5 is an explanatory diagram of a core width detection timing generation circuit according to the first embodiment.

FIG. 6 is an explanatory diagram of a charge / discharge circuit of the first embodiment.

FIG. 7 is a timing chart in the circuits of FIGS. 5 and 6.

FIG. 8 is a timing chart (normal state) of the first embodiment.

FIG. 9 is a timing chart (at the time of abnormality) of the first embodiment.

FIG. 10 is a device block diagram of a second embodiment.

FIG. 11 is a timing chart of the second embodiment (at the time of abnormality).

FIG. 12 is a timing chart of Example 3 (at the time of abnormality).

FIG. 13 is an explanatory diagram of a conventional MR head.

FIG. 14 is a diagram illustrating a conventional MR head usage state.

[Explanation of symbols]

 7 MR Head 16 Core Width Detection Pattern 16-1 First Half 16-2 Second Half 17 First Pattern Group 18 Second Pattern Group 19 Pattern 20 Lead Core (MR Element) 21 Amplifier 22 Peak Detection Circuit 23 Core Width Detection Timing Generation Circuit 24 Charge / discharge circuit 25 Differential amplifier 26 PLL clock generation circuit 27 Master clock generation circuit 28 Master clock generation start pattern detection circuit 29 ADC (analog / digital converter) 30 MPU 31 Nonvolatile memory

Claims (7)

[Claims] 1. A magnetic storage device comprising a recording medium, a magnetic head having at least a read core for reading information from the recording medium, and a controller, wherein the recording medium is a reference for detecting an effective core width of the read core. A recording medium that records a pattern and a core width detection pattern following the pattern, and causes the control unit to start generating a reference clock at the timing when the reference pattern is read from the recording medium. A magnetic storage device comprising: a core width detection unit that detects a phase difference from a read signal from which a detection pattern is read, and detects an effective core width of the read core from the phase difference. 2. A magnetic storage device comprising a recording medium, a magnetic head having at least a read core for reading information from the recording medium, and a controller, wherein the recording medium is a reference for detecting an effective core width of the read core. A recording medium on which a pattern and a core width detection pattern following the recording medium are recorded, and the control unit includes a reference clock generation unit for starting generation of a reference clock at a timing when the reference pattern is read from the recording medium; A peak detection circuit that detects the peak of the read signal from which the detection pattern is read, and a core width detection unit that detects the phase difference between the reference clock and the peak of the read signal and detects the effective core width of the read core from the phase difference. A magnetic storage device comprising: 3. A magnetic storage device comprising a recording medium, a magnetic head having at least a read core for reading information from the recording medium, and a controller, wherein the recording medium is a reference for detecting an effective core width of the read core. A recording medium on which a pattern and a core width detection pattern following the recording medium are recorded, and the control unit includes a reference clock generation unit for starting generation of a reference clock at a timing when the reference pattern is read from the recording medium; A zero-cross detection circuit for detecting a zero-cross point of a signal obtained by removing a high frequency component from a read signal from which a detection pattern is read, and a phase difference between the reference clock and a zero-cross point of the read signal, and the lead core from the phase difference. Storage device having core width detection means for detecting the effective core width of 4. The core width detecting means includes duty pulse generating means for generating a duty pulse having a pulse width corresponding to the phase difference, and a charging / discharging circuit for charging / discharging a capacitor based on the duty pulse. The magnetic storage device according to claim 1, 2 or 3, wherein the effective core width of the lead core is detected as a terminal voltage of the capacitor. 5. The core width detection pattern is divided into a first half portion and a second half portion, and when the effective core width of the lead core becomes narrower than in a normal state, the phase difference becomes small in the first half portion,
4. The magnetic memory device according to claim 1, 2 or 3, wherein patterns are symmetrically arranged in the first half and the second half so that the phase difference becomes large in the second half. 6. The core width detection pattern is divided into a first half portion and a second half portion, and when the effective core width of the lead core becomes narrower than in a normal state, the phase difference becomes large in the first half portion,
4. The magnetic storage device according to claim 1, wherein the patterns are symmetrically arranged in the first half and the second half so that the phase difference becomes smaller in the latter half. 7. The magnetic memory device according to claim 1, wherein the lead core is composed of a magnetoresistive effect element (MR element) utilizing a magnetoresistive effect.