JPH07334948A - Disk device - Google Patents

Abstract

PURPOSE:To detect a demodulating signal synchronized correctly with a phase servo pattern without being influenced by adjacent patterns. CONSTITUTION:A zero-cross detection signal to be used for detecting a head position is outputted by detecting the zero-cross timing of the read-out signal of the servo information from a servo head means 18 with a zero-cross detecting means 112. The bluntness of a zero-cross due to noise and adjacent cylinder patterns is improved by providing a low-pass filter means 1010 in the front stage of the zero-cross detecting means 112.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a disk device for detecting the position of a head by determining the phase of servo information recorded on the disk surface, and more particularly to detecting the head position by detecting the zero cross of the servo information read waveform. Disk device. A magnetic disk device is a storage device in which a head is moved in the radial direction of a rotating magnetic disk to position it on a target track, and the magnetic head reads data from and writes data to the track of the magnetic disk. In this magnetic disk device, it is essential to improve the recording density, especially the track density, in order to increase the storage capacity and reduce the size.

In addition, the seek time of the head for speeding up is
Performance of around 10 mm is required. Therefore, a digital circuit using a high speed processor is adopted as the head positioning circuit. When this digital servo circuit is used, it is sufficient to detect the position only at the sampling timing, and the position detection circuit of the servo head is required to be different from the analog servo position detection circuit.

[0003]

2. Description of the Related Art Generally, a widely used two-phase servo pattern has a problem that the frequency band of a position signal demodulation circuit becomes higher as the track density of a magnetic disk becomes higher, which makes it weak against noise. there were. In the two-phase type servo pattern, the peak of the waveform obtained by reading the servo information recorded on the servo surface of the magnetic disk is detected, and the position is detected by the height of the detected peak.
However, although the peak height is obtained continuously, there is a problem that the influence of noise and the level fluctuation of the magnetic disk medium surface directly affect the amount of position detection.

Therefore, a method of recording a servo pattern as phase information and detecting the position by the phase difference of the servo information is disclosed in US Pat. No. 4,549,232 and US Pat. No. 4,642,562.
Specification (Corresponding Japanese Patent Application, 1985, No. 104
No. 72) and the like. FIG. 16 shows a conventional phase servo pattern. The phase servo pattern divides the servo surface of the magnetic disk into four cylinder units of 0, 1, 2, 3, and records servo information having different phases in the circumferential direction of each cylinder. That is, one phase servo pattern includes the first field EVEN1 and the second field EVEN1.
It is divided into a field ODD and a third field EVEN2. First and third fields EVEN1, EVEN
A servo pattern of the same phase is recorded in 2 and a pattern of the opposite phase is recorded in the second field ODD so that the position of the moving head can be read at the center position of the second field ODD.

FIG. 17 shows detection of a phase difference in the first and third fields EVEN1 and EVEN2 of FIG.
Here, the servo pattern is recorded with four cycles of the reference clock as one cycle, and the case where the positions of the cylinders numbered 0 to 3 in the four cylinders can be detected is taken as an example. Assuming that the reference phase of the reference clock is the phase indicated by the thick line in the figure, when the head is at the position 600 that is the center of the second cylinder, the phase difference between the clock reference phase and the read pulse of the phase servo pattern is the phase difference signal. As shown by 610, the servo pattern period is ½. In addition, the position where the head is the center of the first cylinder 62
When it is 0, the phase difference between the clock reference phase and the read pulse of the servo pattern is 1 as in the phase difference signal 630.
/ 4 cycles.

When the head is at the position 640 which is the center of the third cylinder, the phase difference between the reference phase and the read pulse of the servo pattern is 3 as shown by the phase difference signal 650.
/ 4 cycles. Further, when the head is located at the center of the 0th cylinder, the phase difference between the clock reference phase and the read pulse of the servo pattern becomes zero or one cycle. FIG. 18 shows the detection of the phase difference in the second field ODD. For example, when the head is at the position 660 that is the center of the second cylinder, the phase difference between the clock reference phase and the read pulse of the servo pattern is 1/2 as in the phase difference detection signal 670.
It becomes a cycle. Further, when the head is at the position 680 which is the center of the third cylinder, the phase difference between the clock reference phase and the read pulse of the servo pattern is the phase difference detection signal 69.
It becomes 1/4 cycle like 0. Therefore, by detecting this phase difference, it is possible to detect at which position of the cylinders 0 to 3 the magnetic head is located.

According to the head position detection using this phase servo pattern, the peak of the read waveform from the servo surface is detected to detect the phase difference with respect to the clock reference phase a plurality of times,
The average phase difference is used as a position signal. Since the phase difference is detected a plurality of times, the position signal cannot be obtained continuously, but the averaging is less susceptible to noise. Further, if the level fluctuation of the disk medium surface does not become the fluctuation of peak detection, the position can be detected with high accuracy.
Furthermore, in the digital positioning control of the head,
Since it is only necessary to obtain position information for each sampling cycle,
Position detection using a phase servo pattern is suitable because continuous information is not required.

In the conventional device, a clock source having a fixed phase such as a crystal oscillator is used. Therefore, if there is a fluctuation in the rotation of the disk, the phase difference from the servo pattern cannot be accurately detected, and the position detection accuracy is reduced. descend. Also, the crystal oscillator
The oscillation frequency fluctuates depending on the temperature, and thus the phase of the clock reference fluctuates, so that the phase difference from the servo pattern cannot be accurately detected, and the position detection accuracy decreases.

Further, in the conventional apparatus, since the dedicated processor performs the position detection processing by calculating the average value after detecting the phase difference, if the seek speed becomes faster, the processing of the processor will not be in time, making it difficult to perform high-speed seek. It was
Further, in the conventional device, when the head moves in the range of 4 cylinders from No. 0 to No. 3, the phase difference is 0 to 1 cycle (4
Clock) range. For this reason, the second cylinder at the center has a continuous change width of the phase difference of 4 clocks, but the other cylinders 0, 1, 3 have a small change width of the phase difference. As a result, the head position detection tooth mark in the core control becomes narrow, and seek control is difficult.

In order to solve such a problem, the inventor of the present application has proposed a "servo position detecting device for a disk device" of Japanese Patent Application No. 5-54977 (corresponding US Patent Application No. 08/194663). There is. In this disk device, a training area in which timing information is recorded is provided in front of the servo area of the disk, and a P is a clock generation source.
The LL circuit is phase-synchronized to generate a reference clock synchronized with the servo pattern of the disk. Therefore, a reference clock having a prescribed phase can be generated irrespective of the fluctuation of the rotation of the disk and the fluctuation of the environmental temperature, and the phase difference from the servo pattern is accurately detected to improve the detection accuracy of the head position.

Further, the position signal detection processing is performed in the first to third steps.
The duty ratio is 0 depending on the head position in the field.
Converted to a duty pulse that changes in the range of 100%,
Using this duty pulse, the capacitor is charged, discharged, and switched in the order of the first to third fields and integrated, and the head position signal is detected as the integrated voltage of the capacitor.

The phase servo information is such that the sum of the first and third fields is substantially the same as that of the second field. Therefore, in the on-track condition to the target cylinder,
The duty ratio of the first to third fields is 50%, 50
%, 50%, and the integrated voltage becomes zero. By the analog detection of the position signal by the integration circuit, the processor only needs to AD-convert the integration signal and read it, and the position detection corresponding to the high speed seek can be performed.

Further, by automatically performing so-called cylinder switching for selecting a reference clock corresponding to a target cylinder from a plurality of reference clocks having different phases, whichever of the 0th to 3rd cylinders becomes the target cylinder, A position signal that constantly changes in the range of ± 2 cylinders as the center cylinder is obtained as the center cylinder, and cores control and on-track control are ensured.

[0014]

However, in the disk device already proposed, the peak of the read signal of the phase servo information obtained from the servo head is detected to create the head position signal. The peak detection has a problem that it is weak against noise and jitter is likely to occur. That is, in the peak detection, the peak detection signal is obtained by detecting the zero cross of the signal obtained by differentiating the read signal at the timing of the gate signal obtained by level-slicing the read signal obtained from the servo head.

However, the phase servo information recorded on the servo surface is a pattern having a phase shift of 0.5 cylinder, as shown in FIG. 16, and the read signal by the servo head is read from the adjacent servo zones. Affected, the signal amplitude becomes small and the peak part becomes blunt. FIG. 19 (A)
Shows a read signal 1160 of the phase servo pattern in the target cylinder, a pattern read signal 1170 of the adjacent cylinder shifted by +0.5 cylinder, and a pattern read signal 1180 of the adjacent cylinder shifted by -0.5 cylinder. The read signal actually obtained from the servo head is the read signal 1 shown in FIG.
It becomes 200.

Therefore, the read signal 1200 is differentiated as shown in FIG. 19C, and the peak is detected from the zero cross of the differentiated signal 1210. However, the waveform portion 122
As shown by enlarging 0, at the zero-cross point 1230, waveform distortion in which the slope of the waveform is blunt occurs, which causes phase jitter. As a result, there is a problem that the positioning accuracy of the head deteriorates.

An object of the present invention is to provide a disk device capable of position detection using phase servo information that is resistant to noise and jitter.

[0018]

FIG. 1 is a diagram for explaining the principle of the present invention. First, the present invention, on the servo surface of the disk medium,
Servo information having one phase change is recorded in each of a plurality of servo frames arranged in the circumferential direction of each cylinder with a plurality of cylinders as one unit, and phase servo information having an opposite phase change is recorded. The target is a disk device that detects the head position from the phase servo information.

With regard to such a disk device, in the present invention, the zero-cross detecting means 112 for detecting the zero-cross timing of the read signal of the servo information by the servo head means 18 and outputting the zero-cross detection signal used for the head position detection. Is provided. Further, the low-pass filter unit 1 is provided in front of the zero-cross detection unit 112.
010 is provided.

[0020]

According to such a constitution of the present invention, the following actions can be obtained. The recording pattern of the phase servo information is recorded such that the phases are different at 0.5 cylinder pitch. For this reason, the read signal of the target cylinder is affected by the recording patterns on both sides, which are shifted by 0.5 cylinder, and the signal waveform becomes smaller or the peak is rounded. In peak detection, jitter is added to the peak detection pulse as the demodulation signal. Will be generated.

Therefore, the demodulated signal is obtained by detecting the zero cross of the read signal. With zero-cross detection, it is possible to obtain a zero-cross detection pulse as a demodulation signal that is accurately synchronized with the phase pattern without being affected by the rounding of the peak portion due to the adjacent phase patterns. Furthermore, by providing a low-pass filter in the preceding stage, it is possible to reduce noise in the read signal, accelerate the rising edge of the signal at the zero-cross portion, and further improve the accuracy of the demodulated signal synchronized with the recording pattern of the phase servo.

[0022]

【Example】

<Contents> 1. Hardware configuration 2. Position signal generation circuit 3. Servo frame 4. Position detection by reading the phase servo pattern 1. Hardware Configuration FIG. 2 shows the overall configuration of the disk device of the present invention. The disk device of the present invention comprises a disk enclosure 10 and a drive controller 12. The disk enclosure 10 includes a spindle motor 14 for rotating a disk, a voice coil motor for moving a head (hereinafter,
A "VCM") 16 is provided. Further, in order to read the information on the servo surface of the magnetic disk, the servo head 1
8 and a servo head IC 22 are provided.

Further, data heads 20-1 to 20-n and a data head IC 24 are provided for reading and writing information on a plurality of data surfaces. Data heads 20-1 to 20
Each of -n includes a write head and a read head integrally in the head portion. A magnetic head is used as the write head, and an MR head using a magnetoresistive element is used as the read head.

The core width of the write head and the read head provided in the servo head 18 and the data heads 20-1 to 20-n is the largest in the servo head 18, and the core width of the write head is the second largest. In addition, the read head (MR head) has the smallest core width. For example, when the track pitch on the data surface is 7 μm, the core width of the servo head 18 is almost equal to the track pitch.
μm. On the other hand, the write head provided in the data head has a core width of 6 μm, and the core width of the MR head as a read head is about half that of 3 μm.

The drive controller 12 is provided with a control processor 26 as an overall control unit. The control processor 26 is coupled to the upper disk control unit via the interface circuit 28, receives various commands such as a seek command, a read command, and a write command, and executes a corresponding process. A drive processor 30 that executes head positioning control is provided under the control processor 26. A digital signal processor is used as the drive processor 30. A position signal generating circuit 36 is provided to detect the head position for the drive processor 30.

The position signal generating circuit 36 includes the servo head 1
8 read signals are input. In the present invention, the phase servo information is recorded on the data surface of the disk medium, and the position signal creation circuit 36 creates the position detection signal indicating the head position based on the read signal of this phase servo information. The position signal from the position signal generating circuit 36 is converted into digital data by the AD converter 38 and taken into the drive processor 30.

The drive processor 30 receives the spindle motor 14 via the DA converter 32 and the driver 34.
To control. Further, the VCM 16 is driven via the DA converter 40 and the driver 42 to control the position of the head. The head positioning control by the drive processor 30 includes seek control for moving the head to the target cylinder based on the seek command and on-track control for maintaining the on-track state when the head reaches the target cylinder.

Here, the seek control is composed of a coarse control and a fine control. The coace control is a control for moving the head immediately before the target cylinder according to the target speed pattern. The fine control is control for switching the speed control to the position servo control and pulling the head into the target cylinder when the cylinder reaches just before the target cylinder, for example, 0.5 cylinder before, by the coace control.

On the other hand, in order to read / write data from / to the data surface of the disk medium, the encoding / decoding circuit 4
4, a demodulation circuit 48 and a bias current control circuit 46 are provided. As these read / write circuits, known circuits can be used as they are. Further, in the present invention, with respect to a specific cylinder, that is, a user area on the data surface of the disk medium, an inner guard band area located at an end portion on the inner side and an outer guard band area located on the outer side,
The equivalent phase servo pattern corresponding to the phase servo pattern on the servo surface is recorded. Since the phase servo pattern on the data surface is read by the read head provided in the data head to detect the head position, the read signal of the read head from the data head 24 passes through the demodulation circuit 48 and the position signal generation circuit 36. Is being supplied to. 2. Position Signal Generation Circuit FIG. 3 shows an embodiment of the position signal generation circuit 30 provided in the drive controller 12 of FIG. The servo head 18, the data head 20, the drive processor 30, and the DA converter 38 related to the position signal generating circuit are also shown.

In FIG. 3, the read signal of the servo surface read by the servo head 18 is amplified by the AGC amplifier 1000, then noise-removed and waveform equalized by the low-pass filter 1010, and then input to the peak detection circuit 100. ,
A peak detection pulse (lead pulse) that detects the peak timing of the read waveform is output. Here, magnetic recording and reading on the servo surface and the data surface of the disk are
As shown in FIG.

FIG. 4A shows a write signal.
As shown in (B), the polarity of the medium is magnetized to the N pole at the rising edge of the write signal, and the polarity of the medium is magnetized to the S pole at the falling edge of the write signal. As shown in FIG. 4C, the read signal obtained by reading the magnetization state of the medium has a positive read waveform at the magnetized portion of the N pole and a negative read waveform at the magnetized portion of the S pole. To be In an actual servo pattern, the interval between the N pole and the S pole is very short, so the read waveform in FIG. 4C is a continuous sine waveform.

FIG. 4D is a simplified representation of the magnetized state of the medium of FIG. 4B. The magnetized portion of the N pole is indicated by the solid line 21.
2 and the magnetized portion of the S pole is shown by a dotted line 214.
The track recording state of the following phase servo pattern is represented by a solid line 212 indicating the N pole magnetization state and a dotted line 214 indicating the S pole magnetization state. The peak detection circuit 100 of FIG. 3 functioning as a part of the read pulse detection means is shown in FIG.
The peak timing of the read waveform of the read signal in (C) is detected, and the peak detection pulse rising at the peak timing is output. Specifically, the peak detection pulse is generated based on the gate signal obtained by slicing the read waveform at a constant level and the differential pulse.

FIG. 5 shows an embodiment of the peak detection circuit 100. The operational amplifiers 1020 and 1030 form a slice circuit. Amplified by the AGC amplifier 100 shown in FIG.
The read signal E01 from which noise has been removed by the low-pass filter 1010 is input to the operational amplifiers 1020 and 1030. A fixed slice voltage Vs is set to the operational amplifiers 1020 and 1030.

The operational amplifier 1020 for non-inverting amplification uses the slice voltage V on the plus side with reference to 0 V which is the midpoint voltage.
s is set and the positive amplitude portion of the input read signal E01 is sliced with the slice voltage Es to obtain a slice signal E0.
3 is output. On the other hand, an operational amplifier 1 that performs inverting amplification
A slice voltage 030 sets a slice voltage of −Vs with reference to 0V as a midpoint, and outputs a slice signal E04 obtained by slicing the negative read waveform of the input read signal E0 with the slice voltage −Vs.

On the other hand, the read signal E01 is applied to the differentiating circuit 1040.
Are differentiated by and input to the zero-cross detection circuit 1050. The differential waveform obtained by differentiating the read signal E01 is the read signal E
Since the zero cross occurs at the peak portion of 0, this zero cross is detected by the zero cross detection circuit 1050. The zero-cross detection signal E05 is a signal obtained by detecting the peak timing of the read signal E01.

The slice signal E03 is input to the D terminal of the D-FF 1060, and the slice signal E04 is input to the D-FF 1060.
It is also input to the D terminal of 70. Here, D-FF10
The clock terminal C of 70 is an inverting input. D-FF10
The zero-cross detection signal E05 is applied to the clock terminals of 60 and 1070. The slice signals E03 and Eo4 function as gate signals. When the zero-cross detection signal E05 also rises to the logic level 1 after the slice signal E03 rises to the logic level 1, the D-FF 1060
Is performed and the Q output becomes the logic level 1.
Further, when the zero-cross detection signal E05 falls to the logic level 0 after the slice signal E04 rises to the logic level 1, the setting operation of the D-FF 1070 is performed and the Q output becomes the logic level 1.

The OR circuit 1080 is a D-FF 1060,1.
The Q output of 070 is ORed to trigger the one-shot multivibrator 1090 to output the peak detection signal E06 having a predetermined pulse width. The peak detection signal E04 is fed back to the reset terminals R of the D-FFs 1060 and 1070 and reset for the next peak detection. The operation of this peak detection circuit will be further clarified from the timing charts of FIGS. The read signal from the servo head has waveform distortion as shown in FIG. 6 (A), but by passing through the filter 1010 shown in FIG. 3, it becomes the filter output signal E01 shown in FIG. 6 (B), which is Input to peak detection circuit. Filter output signal E01
In contrast, the slice voltages + Vs and −Vs are set in the operational amplifiers 1020 and 1030.

As a result, the operational amplifier 1020 has the configuration shown in FIG.
The slice signal E03 shown in (D) is output as a gate signal. The operational amplifier 1030 also outputs the slice signal E04 shown in FIG. 6E as a gate signal. On the other hand, the differential signal E02 from the differentiating circuit 1040 is
As shown in FIG. 6C, the peak timing of the read signal has a zero cross. This differential signal E02 is input to the zero-cross detection circuit 1050, and the zero-cross detection signal E05 shown in FIG. 6 (F) synchronized with the zero-cross is output.

In the zero-cross detection circuit 1050, the differential signal E0 of FIG. 6C is input to the positive input terminal and the signal obtained by inverting the differential signal E02 is input to the negative input terminal when viewed from the midpoint voltage of zero volts. The zero-cross detection signal E5, which is regarded as being input and rises to the logic level 1 in the positive half cycle of the differential signal E02 as a comparison output of the input signals of the plus input and the minus input, is shown in FIG.
Output as shown in (F).

The D-FF 1060 has the zero-cross detection signal E when the slice signal E03 is at the logic level 1.
When 05 rises to the logic level 1, the Q output becomes the logic level 1 and one-shot through the OR circuit 1080.
Peak detection pulse E0 from multivibrator 1090
One 6 is output. Then, when the zero-cross detection signal E05 falls to the logic level 0 in the next zero-cross detection after the slice signal E04 rises to the logic 1, DF
The setting operation of F1070 is performed, the Q output becomes the logic level 1, the one-shot multivibrator 1090 is triggered via the OR circuit 1080, and the next peak detection pulse E06 is output.

The output of the peak detection circuit 100 is given to the PLL circuit 102 and the marker detection circuit 104.
The PLL circuit 102 oscillates the reference clock in synchronization with the peak detection pulse based on the reading of the timing signal recorded in the training area at the beginning of the servo frame which will be described later. The oscillation frequency of the PLL circuit 102 is 20 MHz in this embodiment,
Therefore, one clock period τ becomes 50 nsec. The marker detection circuit 104 detects a marker signal in a marker area subsequent to the training area of the servo frame.

Guard band index detection circuit 10
5 detects a guard band signal and an index signal in the guard band / index region following the marker region. The marker detection circuit 104 outputs the marker search signal E.
When 1 is received, it becomes operable. Also, the guard band
The index detection circuit 105 also receives the guard band search signal E3 to enter the guard band detection state, and receives the index search signal E4 to enter the index detection state.

The marker detection circuit 104 outputs a marker detection signal E2. The first outer guard band detection signal OGB1 and the second outer guard band OGB are output from the guard band index detection circuit 105.
2. The index signal INDEX is output. PLL
The counter 106 starts the PLL circuit 102 from the time when the marker detection signal E2 from the marker detection circuit 104 is obtained.
Count the clock. Therefore, the PLL counter 1
The value of 06 provides a count value indicating the information recording position in the guard band index part and the servo pattern part after the marker detection time as a starting point.

On the other hand, the output of the servo head 18 is given to the zero cross detection circuit 112 which functions as a part of the read pulse detection means through the selection circuit 116. In the present invention, for the phase servo read signal of the servo pattern portion provided at the end of the servo frame, zero-cross detection is performed instead of peak detection. By this zero-cross detection, the read signal of the phase servo can be surely obtained even if noise is mixed.

FIG. 7 shows an embodiment of the zero cross detection circuit 112. The zero cross detection circuit 112 is an operational amplifier 115.
0, and the read signal E01 from the low-pass filter 1010 at the previous stage is input to the non-inverting input terminal (plus input terminal) and the inverting input terminal (minus input terminal) of the operational amplifier 1150 by AC coupling via capacitors 1110 and 1120, respectively. is doing. Capacitors 1110, 1120
For the input of the operational amplifier 1150 that follows, a resistor 11
A constant reference voltage Vref is applied as a bias voltage via 30, 1140.

The operation of the zero-cross detection circuit 112 is shown in FIG.
It is clear from the timing charts of (A) to (D). The read signal in FIG. 8A is the low-pass filter 1010.
Is a signal before passing through, causing waveform distortion in which the zero cross is rounded. This read signal is passed through the low pass filter 10
When 10 is passed, as shown in FIG. 8B, the rising of the zero cross can be accelerated.

The read signal E01 is supplied as a differential signal of two signal lines, and the capacitors 1110 and 1120 are provided.
Read signal E input to operational amplifier 1150 by AC coupling of
When 01 is viewed with reference to the midpoint voltage set by the reference voltage Vref, the non-inverting input terminal (plus) side has a signal waveform shown in FIG. 8B. On the other hand, the inverting input terminal (minus) side becomes an input signal obtained by inverting the non-inverting input signal, as shown in FIG.

Therefore, the operational amplifier 1150 operates as a comparator for comparing the non-inverted input signal with the inverted inverted input signal. Therefore, the zero-crossing detection pulse E16 of FIG. 8D having the logic level 1 is output for the half cycle period in which the non-inverted input signal exceeds the inverted input signal. The embodiment of the zero-cross detection circuit shown in FIG. 7 has the same circuit configuration as the zero-cross detection circuit 1050 used in the peak detection circuit shown in FIG.

Referring again to FIG. 3, the zero-cross detection circuit 112 detects the zero-cross timing between the positive read waveform of the N pole and the negative read waveform of the S pole in the read signal of FIG. 4C. It will be. Therefore, the zero-cross detection necessarily has a phase delay in the detection timing with respect to the peak detection of the read waveform. That is, with respect to the reference clock by the PLL circuit 102, the synchronization control by peak detection is performed, and originally, the read pulse by the reading of the phase servo also needs to be synchronized with the clock of the PLL circuit 102. Inevitably, a phase delay occurs with respect to the reference clock.

The phase delay due to this zero-cross detection is adjusted by the variable delay circuit 114 and the shifter 108, and it becomes possible to create a duty pulse with a duty ratio of 50% at which the integrated voltage becomes zero in the on-track state.
Here, the shifter 108 is the second of the PLL counter 106.
The rising edge of the pulse signal obtained by dividing the reference clock of the PLL circuit 102 obtained as a bit output by a quarter is set to 0.
The delay is digitally adjusted in the range of 3 steps from 3 to 3τ. On the other hand, the variable delay circuit 114 delays the rising timing of the zero-cross detection circuit 112 in an analog manner by selectively connecting a plurality of analog delay elements.

The master clock generation circuit 110 generates a master clock having a period 4τ by dividing the reference clock having a phase determined corresponding to the target cylinder into quarters and outputs it as a master clock signal E10. Switching of the master clock having a phase corresponding to the target cylinder is performed by a cylinder switching signal E30 from the drive processor 36.

The so-called cylinder switching by the cylinder switching signal E30 is a master clock having a phase corresponding to the target cylinder in which the head is currently located in the on-track control. On the other hand, at the time of seek control, the actual speed obtained at the previous head position and the current head position, and further the acceleration are added to create the master clock of the phase corresponding to the target cylinder at the predicted next predicted position. Switch to do.

The duty pulse generation circuit 120 is a set / reset circuit, and the master clock generation circuit 110.
Master clock signal E1 corresponding to the target cylinder from
It is set at the rising edge of 0 (reference phase), and the selection circuit 11
It is reset at the trailing edge (detection phase) of the zero-crossing detection pulse obtained via signal 8. From the duty pulse generation circuit 120, when the servo head 18 is on-track, the first field (EVEN) of the phase servo pattern is generated.
1), the second field (ODD1), the third field (ODD2), and the fourth field (EVEN2), a duty pulse E19 having a duty ratio of 50%, 50%, 50%, 50% is output.

Duty pulse E19 from duty pulse generating circuit 120 is applied to integrating circuit 124. The integrating circuit 124 basically includes a capacitor 126.
And four switch elements 128, 130, 132 and 134 bridge-connected to the capacitor 126. Lower switch element 1 for capacitor 126
32 and 134 are on / off controlled by a duty pulse E19. On the other hand, the switching elements 128 and 130 on the upper side of the capacitor 126 are switching-controlled according to the first to fourth fields of the phase servo pattern.

Assuming that the polarities of the position signals extracted from both ends of the capacitor 126 are positive on the right side and negative on the left side as shown in the figure, the switching elements 128, 130, 132, and 134 in the first to fourth fields are switched. The integration operation by is as follows. First, in the first field and the fourth field (EVEN1, 2), the switch element 128 on the upper side of the capacitor 126 is turned on and 130 is turned off. In this state, the duty pulse E19 turns on / off the switch element 130. Therefore, the capacitor 126 is charged along the path indicated by the solid line,
The position signal seen by the voltage across the capacitor 126 increases to the negative side.

On the other hand, the second and third fields (ODD
In 1 and 2, the switch element 130 on the upper side of the capacitor 126 is turned on and 128 is turned off. In this state, the switch element 132 is turned on / off by the duty pulse E19. Therefore, the capacitor 126 is charged by the path indicated by the broken line, and the position signal seen with the polarity shown in the figure increases to the plus side.

In the on-track state for the target cylinder, the duty pulse E19 has a duty ratio of 50% for all fields, and the number of pulses in each field is the same. Therefore, when the integration operation of the duty pulses for four fields is completed, The integrated voltage of the capacitor 126 becomes zero. If the servo head deviates from the state where it is on-track to the target cylinder, the duty ratio becomes 50
%, The voltage corresponding to the change of the duty ratio is obtained in the capacitor 126.

Specifically, when the servo head 18 moves in the minus direction with respect to the target cylinder, that is, in the outer side,
The duty ratios of the first and fourth fields (EVEN1, 2) decrease, and conversely the second and third fields (OD
The duty ratio of D1, 2) increases. On the other hand, when the servo head 18 moves in the positive direction with respect to the target cylinder, that is, toward the inner side, the duty ratios of the first and fourth fields (EVEN1, 2) increase, and the second and third fields (ODD1) increase. , 2), the duty ratio decreases.

Capacitor 126 in integrating circuit 124
The switching control of the upper switching elements 128 and 130 for each field is performed by the output signal E from the coincidence detection circuit 122.
5, E6, E7, E8. Match detection circuit 1
Reference numeral 22 determines whether the count value of the PLL counter 106 matches a predetermined value and outputs a signal corresponding to each matching position.

That is, in addition to the search signals E1, E3, E4 for the marker detection circuit 104 and the guard band index detection circuit 105, the demodulation mode generator 122-
1, the demodulation mode signal E indicating the first to fourth fields
5 is output. Further, the half mode generation unit 122-2 outputs the half mode signal E6 indicating the position signal detection time point which is the boundary between the second field and the third field.
In addition, the data window generator 122-3
In the fourth field period, the data window signal E7 that makes the duty pulse to the integrating circuit 124 effective is output.

Further, the discharge control unit 122-4 controls the first to
The discharge control signal E8 for discharging and resetting the capacitor 126 is output at a timing other than the duty pulse generation period over the fourth field. The discharge reset by the discharge control signal E8 turns off the switch elements 128 and 130 provided in the integration circuit 124 and turns off the switch elements 132 and 13.
4 will be turned on.

The position signal E40 obtained as the voltage across the capacitor 126 of the integrating circuit 124 is taken into the drive processor 30 by the interrupt signal E9 obtained by the AD converter 38 at the end timing of the servo frame. On the other hand, in the present invention, the phase servo pattern is written also in the inner guard band area (IGB1) and the outer guard band area (OGB1) of the data surface. In order to enable detection, the data head 20
The read signal of the read head 410 provided in the above is input to the zero-cross detection circuit 112 via the selection circuit 116.

The read head 410 to the selection circuit 11
Similarly to the servo head 18 side, the AGC amplifier and the low-pass filter may be provided for the input line 6 as well. The selection circuit 116 is switched by the control signal E31 from the drive processor 30. That is, in normal servo control, the selection circuit 116 causes the servo head 1
It has been switched to the 8 side. On the other hand, when reading the phase servo pattern on the data surface, switching is performed to the data head 20 side in units of a predetermined number of servo frames in one rotation of the cylinder.

That is, the phase servo information on the data surface is read while discretely switching to the data head 20 for on-track control based on the phase servo information on the servo surface, and for example, thermal offset measurement or yaw angle offset measurement is performed. Further, according to the present invention, since the disk writer has a function of writing the phase servo pattern on the data surface after the phase servo information is written on the servo surface by the servo writer, the write signal for writing is used as a master signal. It is created by the clock creation circuit 110 and supplied to the write head 400 of the data head 20 to write the servo information on the data surface.

Further, a selection circuit 118 is provided in order to generate a pseudo duty pulse having an arbitrary duty ratio by the duty pulse generation circuit 120 and generate a position signal in the integration circuit 124. Selection circuit 118
Is a pseudo read pulse from the drive processor 30 and the zero-cross detection circuit 112 according to the control signal E32.
The zero-cross detection pulse obtained more is switched.

The duty pulse is generated by the drive processor 30 by generating a pseudo read pulse.
It is used to measure the duty ratio of the actual duty pulse used for adjusting the duty of 50% performed by the shifter 108 and the variable delay circuit 114. 3. Servo frame FIG. 9 shows a 1 recorded on the servo surface of the disk device of the present invention.
The servo information for cylinders is expanded and shown on a straight line. The servo area 154 for one rotation of the disk is divided into 216 sections to form 216 servo frames 156. In the present invention, the number of clocks in the servo area 154 for one rotation of the disk is fixedly determined.

One servo frame 156 has a training section 158 and a marker section 16 as shown in an enlarged view.
0, a guard band index section 162, and a servo pattern section 164. When the start position of the servo frame 156 is set to zero in each area, the training unit 158 sets the count value of the reference clock of 20 MHz to 0 to 112.
8, the marker section 160 has count values of 1128 to 1160, the guard band index section 162 has count values of 1160 to 1268, and the servo pattern section 164 has count values of 1268 to 1512.

FIG. 10, FIG. 11, FIG. 12 and FIG.
A training unit 158 provided on the servo frame 156,
Marker part 160, guard band / index part 16
2 and the magnetic recording state of the servo pattern portion 164. Here, with respect to the training unit 158 of FIG. 10A, the marker unit 160 of FIG. 10B, and the guard band index unit 162 of FIG. 11, the reference clock 166 is shown on a scale of 4τ that is a 4-clock cycle. There is. On the other hand, in the servo pattern portion 164 of FIGS. 12 and 13, the reference clock 166 is shown on a scale of 1τ which is one clock cycle.

Training area 15 shown in FIG.
Reference numeral 8 records a timing signal for synchronizing the phase of the PLL circuit 102 shown in FIG. By reading the timing signal of the training unit 158 and obtaining the peak detection pulse with 4τ, the PLL circuit 102 can perform 1τ = 50 ns, that is, 20 MHz synchronous oscillation in synchronization with the actual disk rotation.

FIG. 10B shows the marker section 160 following the training section 158. The marker unit 160 plays a role of determining a position in the servo frame,
Upon detection of the marker, the count operation of the PLL counter 106 provided in FIG. 3 is started, and the match detection circuit 122 makes various match determinations. From the marker section 160, “LHHHH
A read signal of “LHLHLH” is obtained, and among these, marker detection is performed by detecting the match of the 6-bit pattern of “L □ HH □ L □ L □ L □” illustrated. FIG. 11 shows the guard band index section 162. In the present invention, the guard band index section 162 includes the first majority decision section 174, the second majority decision section 176, and the third majority decision section 1.
The same signal is repeatedly recorded in each of the three areas 78.

The guard band index detection circuit 105 shown in FIG.
Three first to third majority decision units 1 obtained from the read signal of No. 2
Among the 74, 176, 178, if two or more pieces of matching information are obtained, it is determined that the guard band and index are detected, and the guard band and index detection performance is improved.

The servo surface is arranged radially from the inner side to the inner guard band area (IGB1) 180 and the user area 1.
82, first outer guard band region (OGB1) 18
4 and second outer guard band region (OGB2) 1
It is divided into 86. Index information 188, 19
0 and 192 are provided in the inner guard band region 180, the user region 182, and the first and second outer guard band regions 184 and 186.

12 and 13 show details of the servo pattern portion 164 in which the phase servo pattern is recorded. This servo pattern portion 164 has a first field 200, a second field 202 shown in FIG. 12, and a third field shown in FIG.
It is composed of a field 204 and a fourth field 206. In the following drawings, as shown in parentheses, the first field 200 is "EVEN1", the second field 202 is "ODD1", the third field 204 is "ODD2", and the fourth field 206 is " EVEN2 "
I am trying.

The lengths of the areas from the first field to the fourth field are such that unused portions 194, 196, 208 and 20 are used.
Except for 1, they have the same length. Specifically, when 4τ for four periods of the reference clock is used as a reference length, each field has a length of 4τ × 10. The first and fourth fields 200 and 206, which are EVEN1 and EVEN2, have a pattern in which the phase is shifted by 1τ each time 0.5 cylinder is moved in the increasing direction (inner direction) on the plus side of the cylinder number,
Writing is done in 8τ cycles.

On the other hand, the second and third fields 202 and 204, which are the ODD1 and ODD2, are written so as to have a phase shift in the opposite direction. Also, each phase servo pattern is repeated every four cylinders. 4. Position Detection by Reading Phase Servo Pattern FIG. 14 shows the coincidence detection circuit 12 of FIG. 3 when the phase servo pattern of the servo surface is read by the disk device of the present invention.
2 shows a timing chart of each signal output from No. 2 for one servo frame. When the synchronization of the PLL circuit 102 by the timing signal read from the head training area is completed in the reading of the servo frame, FIG.
The marker detection signal E2 shown in 4 (B) is output from the marker detection circuit 104 upon detection of the marker area. This marker detection signal E2 puts the PLL counter 106 into the operating state as shown in FIG. 14C, and starts counting the clock signal E0 from the PLL circuit 102.

Here, in the period from the marker detection to the reading of the last position signal of the frame, the PLL counter 106 is used.
The hexadecimal count value of is determined to be 180H. Therefore, in the period until the hexadecimal count value 180H is obtained, the counter operation is performed. Further, as shown in FIG. 14A, the marker search signal E1 that enables the detection operation of the marker detection circuit 104 is also output for the same period.

Then, the guard band shown in FIG.
The index detection signal E3 is a hexadecimal count value 0 to B0H
Obtained over a period of. At this time, the effective guard band index search signal E in FIG.
4 rises and prohibits the detection operation of the guard band index detection circuit 105. Guard band index search signal E4 has risen to H level 1
The period of B0H to 148H in the hexadecimal count value is the reading period of the servo pattern unit 164.

During the reading period of the servo pattern portion 164, the coincidence detection circuit 122 operates in the first field EVEN.
The demodulation mode signal E5 of FIG. 14 (F) which changes depending on the first, second and third fields ODD1 and OVEN2, and the fourth field EVEN2 is output, and the switch element 128 above the capacitor 126 provided in the integrating circuit 124, 130 is selectively turned on / off in each field period. In addition, FIG.
A half mode signal E6 that gives a position detection point that is the midpoint of the servo pattern portion 164 shown in (G) is output.

The interrupt signal E9 shown in FIG. 14H is generated until the next training section 158 after the servo pattern section 164 is completed. At this timing, the drive processor 30 causes the AD converter 38 to operate. A position signal determined by the converted voltage across the capacitor 126 of the integrating circuit 124 is fetched. Further, as shown in FIG.
The discharge control signal E8, which is effective during the period other than the generation period of the servo pattern portion 164 and the interrupt signal E9, is output,
The capacitor 126 of the integrating circuit 124 is in a discharge reset state, that is, a zero voltage state.

FIG. 15 shows the phase servo pattern of the servo surface, the master clock, the read pulse by the zero cross detection, the duty pulse, and the change of the terminal voltage of the capacitor 126 by the integrating circuit 124 based on the duty pulse by the disk device of the present invention. There is. Here, the servo pattern on the servo surface is repeated for four cylinders with cylinder numbers 0 to 3.

It is now assumed that the servo head 18 is on-track to the central second cylinder. In this state, it is selected as a master clock having a reference phase advanced by 4τ with respect to the phase servo pattern recorded in cylinder number 2. Therefore, the duty pulse E19 shown in FIG. 15B is set at the rising edge of the reference clock every 4τ, and is reset by the reading of the phase servo pattern by the servo head 18. Since it is in the on-track state, the first to fourth fields EVEN1, O
The duty ratio is 50% for any of DD1, ODD2, and EVEN2.

When the duty ratio is 50%, the capacitor 126 of the integrating circuit 124 is first charged in the negative direction in the first field EVEN1. Then, it is charged in the positive direction in the second field ODD2 and becomes 0.
After passing V, the third field ODD2 is further charged in the positive direction. Finally, in the fourth field EVEN2, as in the first field EVEN1, the negative voltage is charged, and the capacitor voltage becomes zero voltage indicating on-track when the reading of the phase servo pattern is completed.

When the servo head 18 seeks in the negative direction and on-tracks to the cylinder number 1 or 0, the master clock having the reference phase advanced by 4τ with respect to the phase servo pattern of each track is selected. A duty pulse E19 having a duty ratio of 50% is similarly obtained. This also applies to the case where the servo head 18 is sought for the cylinder number 3 in the plus direction. Then, a head position signal that linearly changes according to the head position can be generated at a position of ± 2 cylinders with respect to the on-track cylinder position.

The present invention is not limited by the numerical values shown in the embodiments.

[0085]

As described above, according to the present invention,
Even if the read signal of the phase servo pattern recorded with different phases at 0.5 cylinder pitch is affected by the recording patterns on both sides and the signal waveform becomes smaller or the peak is blunted, the zero cross of the read signal is generated. Since the demodulated signal is detected and obtained, the zero-cross detection pulse as a demodulated signal that is accurately synchronized with the phase pattern can be obtained without being affected by the adjacent cylinder.

Furthermore, by providing a low-pass filter in the preceding stage, it is possible to reduce the noise of the read signal, accelerate the rising edge of the signal at the zero cross portion, and further improve the accuracy of the demodulated signal synchronized with the recording pattern of the phase servo.

[Brief description of drawings]

FIG. 1 is an explanatory view of the principle of the present invention.

FIG. 2 is a block diagram showing a hardware configuration of the present invention.

3 is a block diagram showing an embodiment of the position signal generating circuit of FIG.

FIG. 4 is an explanatory diagram of magnetic recording of a servo pattern.

5 is a circuit diagram showing an embodiment of the peak detection circuit of FIG.

6 is a timing chart showing the peak detection operation of FIG.

7 is a circuit diagram showing an embodiment of the zero crox detection circuit of FIG.

8 is a timing chart showing the zero-cross detection operation of FIG.

FIG. 9 is an explanatory diagram of a servo frame of the present invention recorded on a servo surface.

FIG. 10 is an explanatory diagram of a magnetic recording pattern in the training section and the marker section in FIG.

11 is an explanatory diagram of a magnetic recording pattern in a guard band index section of FIG.

12 is an explanatory diagram of a magnetic recording pattern of the first two fields in the servo pattern portion of FIG.

13 is an explanatory diagram of a magnetic recording pattern of the latter two fields in the servo pattern portion of FIG.

14 is a timing chart showing a determination state of a servo frame by the coincidence determination circuit of FIG.

FIG. 15 is an explanatory diagram showing position detection during on-track.

FIG. 16 is an explanatory diagram of a conventional phase servo pattern.

FIG. 17 is a first and third field EVEN when on-tracking to each of cylinder numbers 1, 2 and 3 in FIG.
Timing chart showing duty pulse at 1 and 2

FIG. 18 is a timing chart showing duty pulses in the second field ODD when on-tracking to cylinder numbers 2 and 3 in FIG. 16;

FIG. 19 is a time chart showing a problem of peak detection of a phase servo read signal.

[Explanation of symbols]

 1: Duty adjusting means 2: Duty measuring means 3: Read pulse detecting means 10: Disk enclosure 12: Drive controller 14: Spindle motor 16: Voice coil motor (VCM) 18: Servo head 20, 20-1 to 20-n: Data head 22: Servo head IC 24: Data head IC 26: Control processor (MPU) 28: Interface circuit 30: Drive processor (DSP) 32, 40: DA converter 34, 42: Driver 36: Position signal generation circuit 38: AD Converter 44: Encoding / decoding circuit 46: Bias current control circuit 48: Demodulation circuit 50, 50-1 to 50-11: Magnetic disk 52: Case 54: Rotating shafts 56-1, 56-2: Bearing 58: Head Actuator 60: Sha 62: Block 64: Coil 66-1 to 66-11: Arm 70: Servo system automatic adjusting unit 72: Data surface phase information writing unit 74: Data surface bit data writing / reading unit 76: Yaw angle offset measuring unit 78 : Yaw angle offset correction unit 80: VCM DAC center value adjustment unit 82: Rezero processing unit 84: Duty delay adjustment processing unit 86: Integral circuit adjustment processing unit 88: Seek control unit 90: Cylinder switching control unit 92: Position prediction process Part 94: Thermal offset measurement part 96: Thermal offset correction part 98: Padding processing part 100: Peak detection circuit 102: PLL circuit 104: Marker detection circuit 105: Guard band / index detection circuit 106: PLL counter 108: Shifter 110: Master Clock generation circuit 112: Zero cross detection times 114: Variable delay circuits 116, 118: Selection circuit 120: Duty pulse generation circuit 122: Match detection circuit 122-1: Demodulation mode generation unit 122-2: Half mode generation unit 122-3: Data window generation unit 122-4: Discharge control unit 124: Integrator circuit 126: Capacitor 156: Servo frame 158: Training unit 160: Marker unit 162: Guard band index unit 164: Servo pattern unit 174: First majority decision unit 176: Second majority decision unit 178: Third Majority determination unit 200: First field (EVEN1) 202: Second field (ODD1) 204: Third field (ODD2) 206: Fourth field (EVEN2) 300, 302, 304: D-FF 1000: AGC amplifier 1010: Low pass fill

Claims (2)

[Claims] 1. Servo information having one phase change is recorded on each of a plurality of servo frames arranged on the data surface of a disk medium in the circumferential direction of a plurality of cylinders as a unit, and the opposite is true. In a disk device for recording phase servo information having a phase change and reading the phase servo information by a servo head means (18) to detect a head position, a read signal of the servo area by the servo head means (18) A disk device, which is provided with a zero-cross detection means (112) for detecting the zero-cross timing of the above and outputting a zero-cross detection pulse used for detecting the head position. 2. The disk device according to claim 1, wherein a low-pass filter means (1010) is provided in front of the zero-cross detecting means (112).