JP2727028B2 - Defect detection device for magnetic recording media - Google Patents

Description

The present invention relates to an apparatus for detecting a defect in a magnetic recording medium such as a magnetic disk and a magnetic tape.

[Prior art] A magnetic material is applied or plated on the surface of a recording medium such as a magnetic disk or a magnetic tape. However, an error occurs in a reproduced signal due to a variation in applied or plated state and a mechanical finished state of the surface. May occur. The errors include a positive modulation error, a negative modulation error, a missing error, an extra error, and the like.

Positive modulation error (P-MOD error)
Is an error in which the reproduced signal is higher than the output average value over a wide range. For example, when write data as shown in FIG. 10A is recorded, a voltage portion higher than the output average value occurs in a reproduced signal over a wide range (shown in FIG. 10B).

Negative modulation error (N-MOD error)
Is an error in which the reproduced signal is lower than the output average value over a wide range. For example, when write data as shown in FIG. 10A is recorded, a voltage portion lower than the output average value occurs in a reproduced signal over a wide range (shown in FIG. 10C).

The above P-MOD error and N-MOD error are detected when the magnetic layer has uneven thickness. In other words, a P-MOD error occurs when the thickness is partially large, and an N-MOD error occurs when the thickness is partially thin.

The missing error is an error in which the level of the reproduction signal drops below a predetermined level. For example, when write data as shown in FIG. 10A is recorded, a level drop portion occurs in the reproduced signal (shown in FIG. 10D).

An extra error is an error in which a solitary wave occurs in a reproduced signal in a portion where no signal is to be generated. For example, when write data as shown in FIG. 10E is recorded, a solitary wave of a predetermined level is generated in the reproduced signal (shown in FIG. 10F).

The above-described missing error or extra error is detected when there is a minute scratch or pinhole on the medium surface, or when foreign matter is mixed.

Conventionally, there have been proposed various devices for detecting a defect in a magnetic recording medium by detecting an error in a reproduction signal as described above.

[Problems to be Solved by the Invention] By the way, although detailed description is omitted, some of the above-mentioned devices use a detection pulse of a zero-cross point of a reproduction signal for detecting an N-MOD error or a missing error.

The use of a zero-cross point detection pulse to detect an N-MOD error or missing error may cause jitters in the playback signal due to fluctuations in motor rotation, etc. This is because there is an advantage that can be detected.

The detection circuit for the zero-crossing point generally uses a comparator having hysteresis because noise is mixed in the reproduction signal of the magnetic recording medium. Therefore, when the level of the reproduction signal is minute or at zero voltage, it is impossible to detect the zero cross point, and as a result, it is impossible to detect the N-MOD error and the missing error.

In order to prevent this, it has been proposed to prepare a PLL oscillator, supply a zero-cross point detection pulse as a reference signal, and use the output signal of this oscillator instead of the zero-cross pulse.

According to this, even when the zero-cross point is not detected, the output signal of the oscillator exists, so that the N-MOD error and the missing error can be detected.

However, since the output signal of the oscillator is not stabilized for a predetermined period after the reproduction signal for which an error is to be detected is supplied, accurate error detection is impossible. The use of the PLL oscillator complicates the circuit configuration.

Therefore, the present invention is intended to enable accurate error detection without complicating the circuit configuration.

[Means for Solving the Problems] The present invention relates to a zero-cross detection circuit for detecting a zero-cross point from a reproduction signal from a magnetic recording medium on which write data is recorded in synchronization with a write clock, and comparing the reproduction signal with a reference voltage. The error of the reproduction signal is detected based on the output signal of the voltage comparison circuit and the zero cross detection circuit and the voltage detection circuit. And an error detection circuit for detecting an error in a reproduction signal using a write clock.

[Operation] The write clock is a stable clock,
The signal is synchronized with the reproduction signal.

Therefore, by using the write clock instead of the zero-cross point detection signal, accurate error detection can be performed without complicating the circuit configuration.

Embodiment Hereinafter, an embodiment of the present invention will be described with reference to the drawings. This example is applied to an apparatus for detecting a defect of a magnetic disk (hard disk).

FIG. 1 is a block diagram showing the overall configuration of the embodiment.

In FIG. 1, reference numeral 1 denotes a magnetic disk, and 2 denotes a magnetic head.

The signal Sr reproduced from the magnetic disk 1 by the magnetic head 2 is amplified by the head amplifier 3, further amplified by the interface amplifier 4, and supplied to the read / write tester 5.

The write data WDATA, the write current control signal Swcac, and the write control signal Swcnt output from the read / write tester 5 are supplied to the head amplifier 3, and the write data WD is applied to the magnetic disk 1 by the magnetic head 2.
The ATA is recorded with a predetermined write current.

6 is a spindle motor for rotating the magnetic disk 1, and 7 is an index signal S IND and a sector signal S SEC (FIG. 2A,
B). These signals S
IND, S SEC is supplied to the read / write tester 5 via the controller 8.

Further, the rotation speed of the spindle motor 6 is controlled by the controller 8, and the position of the magnetic head 2 is further controlled via the step motor driver 9.

The read / write tester 5 supplies the controller 8 with a seek signal S seek signal.
Is moved to the target position, a seek completion signal S cmse is supplied from the controller 8 to the read / write tester 5.

FIG. 3 shows the configuration of a read / write tester.

In the figure, 101 is an MPU, 102 is a local bus buffer, and 103 is a local bus connected to the MPU 101 via the local bus buffer 102.

A write control circuit 104 is supplied with a write clock WCLK from the local bus 103.
The operation of the write control circuit 104 is controlled by the MPU 101 via the local bus 103. The write control circuit 104 outputs write data WDATA of a predetermined pattern in synchronization with the write clock WCLK, and also outputs a write control signal Swcnt, which is sent to the head amplifier 3 (shown in FIG. 1) as described above. Supplied.

Reference numeral 105 denotes a write current control circuit. The operation of the write current control circuit 105 is performed via the local bus 103.
It is controlled by the MPU 101. This write current control circuit
A write current control signal Swcac is output from 105 and supplied to the head amplifier 3 as described above.

Further, the reproduction signal Sr from the interface amplifier 4 (shown in FIG. 1) is amplified by the amplifier 106, and then supplied to the low-pass filter 107 to perform noise removal.
The signal is supplied to the envelope detection circuit 108. The envelope signal S ENV of the reproduction signal Sr output from the envelope detection circuit 108 is supplied to a slice level setting circuit 109.

The slice level setting circuit 109 is configured as shown in FIG.

In the figure, the envelope signal S ENV from the envelope detection circuit 108 is supplied to the fixed terminal on the a side of the changeover switch 201. The fixed terminal on the b side of the changeover switch 201 has a DC voltage V REF, for example, +
2V is supplied. This changeover of the changeover switch 201
It is controlled by the MPU 101 (not shown in FIG. 4) via the local bus 103.

The output signal of the changeover switch 201 is supplied to a voltage / frequency converter (VF converter) 203, and a pulse having a frequency proportional to the input voltage output from the VF converter 203 is supplied to an AND gate 204. The gate signal S GATE (shown in FIG. 2C) having a pulse width of one index period is supplied from the local bus 103 to the AND gate 204 during the slice level setting operation.

The pulses gated by the AND gate 204 are supplied to an accumulator 205 and are sequentially accumulated. Accumulator 2
The accumulated data ND output from 05 is supplied to the MPU 101 via the local bus 103.

Here, when the rotation of the magnetic disk 1 is set to a predetermined rotation, for example, 3600 rpm, with the changeover switch 201 connected to the b side, the VF converter 203 calculates the accumulated data ND of the accumulator 205 for one index period. Predetermined value ND RE
F, for example, set to 2000.

The reset of the accumulator 205 is controlled by the MPU 101 via the local bus 103.

Also, the accumulated data N output from the accumulator 205
D is supplied to the D / A converter 206. This D / A converter 206
When accumulated data ND is ND REF, DC voltage 2V
REF (V REF is a DC voltage supplied to the terminal 202) is set to be output.

The output signals of the D / A converter 206 are P-MOD error, N
-D / A converter 207 for setting slice level to detect MOD error, missing error and extra error
Reference voltage (full-scale voltage) for P, 207N, 207M, 207E
Supplied as These D / A converters 207P, 207N, 207
In this example, a 12-bit configuration is used as M and 207E.

The D / A converters 207P, 207N, 207M, and 207E are supplied with 12-bit data DSLP, DSLN, DSLM, DSLE, respectively, for setting a slice level from the local bus 103.

Then, an output signal of the D / A converter 207P and a signal obtained by inverting the output signal by the inverter 208P are derived as slice level signals PML + and PML- for detecting a P-MOD error.

The output signal of the D / A converter 207N and the signal obtained by inverting the output signal by the inverter 208N are derived as slice level signals NML + and NML- for detecting an N-MOD error.

Further, the output signal of the D / A converter 207M and a signal obtained by inverting the output signal by the inverter 208M are derived as slice level signals MISL + and MISL- for detecting a missing error.

Further, an output signal of the D / A converter 207E and a signal obtained by inverting the output signal by the inverter 208E are derived as slice level signals EXTL + and EXTL− for detecting an extra error.

In the above configuration, when setting a slice level for error detection, first, the changeover switch 201 is connected to the b side, and the DC voltage V REF is supplied to the VF converter 203. Further, the AND gate 203 has a value obtained by rotating the magnetic disk 1 at the rotation speed at the time of error detection.
Gate signal S GATE having a pulse width during the index period
(Shown in FIG. 2C).

Then, in the MPU 101, the slice level data D SLP, D SLN, D SLM, and DS are used as the accumulated data ND for one index period output from the accumulator 205 as ND REF ′.
LE is calculated as follows.

D SLP = Do / 2 × Dp [%] × ND REF / ND REF ′ D SLN = Do / 2 × Dn [%] × ND REF / ND REF ′ D SLM = Do / 2 × Dm [%] × ND REF / ND REF ′ D SLE = Do / 2 × De [%] × ND REF / ND REF ′ (1) where Do is a full-scale voltage from the 12-bit D / A converters 207P to 207E. Input data when output,
Do = [111111111111].

Dp [%], Dn [%], Dm [%], De [%]
Assuming that the average voltage (track average voltage) of the envelope signal S ENV in one index period is 100 [%], this is a slice level for detecting a P-MOD error, an N-MOD error, a missing error, and an extra error. . For example, Dp = 130, Dn = 80, Dm = 55, and De = 30.

In the equation (1), the reason why the coefficient of 1/2 is added is that the D / A converter 206 receives 2 V at the input of the accumulated data of ND REF as described above.
REF DC voltage is output, and this D / A
This is because converter 206 substantially doubles the voltage.

The reason for providing the term of ND REF / ND REF ′ in equation (1) is as follows.

That is, one index period differs depending on the rotation speed of the magnetic disk 1. If the one index period is different, even if the track average voltage is the same, the accumulated data ND from the accumulator 205 becomes different, and the D / A converter 206 causes the D / A converters 207P to 207E to change.
The value of the DC voltage supplied as the reference voltage differs.

Incidentally, ND REF and ND REF 'are those when the changeover switch 201 is connected to the b side. That is, ND REF corresponds to one index period of the magnetic disk 1 at, for example, 3600 rpm, and ND REF 'corresponds to one index period of the rotation speed of the magnetic disk 1 at the time of setting the slice level, that is, when an error is detected. I have.

Therefore, by providing the term of ND REF / ND REF ', the D / A converter
The slice-level data D supplied to the D / A converters 207P to 207E so as to cancel the fluctuation of the reference voltage to 07P to 207E.
SLP, D SLN, DSLM, DSLE will be corrected.

The slice-level data D SL calculated as described above
P, D SLN, D SLM, and D SLE are each connected to the local bus 103
Is supplied to the D / A converters 207P, 207N, 207M, 207E via the.

Next, the accumulated data ND of the accumulator 205 is reset, and the changeover switch 201 is connected to the a side.

Further, a track of the magnetic disk 1 for which an error is to be detected is reproduced, and an envelope signal S ENV corresponding to the reproduced signal Sr is supplied to the V-F
The signal is supplied to the converter 203, and the AND gate 204 is supplied with a gate signal S GATE (shown in FIG. 2C) having a pulse width of one index period.

Then, the accumulated data ND for one index period output from the accumulator 205 is supplied to the D / A converter 206,
A DC voltage corresponding to the accumulated data ND is output from the D / A converter 206 and supplied as a reference voltage to the D / A converters 207P to 207E.

As a result, the D / A converters 207P, 207N, 207M, and 207E output Dp [%], Dn
Voltages of [%], Dm [%], and De [%] are output, and slice level signals PML + to EXTL- are formed.

In the state where the slice level is set by the slice level setting circuit 109, a track of the magnetic disk 1 whose error is to be detected is reproduced as described later, and an error is detected from the reproduction signal Sr. If the rotation speed of the magnetic disk 1 is not changed, the calculation of the slice level data only needs to be performed once and the error of the reproduction signal Sr of each track can be continuously detected.

Returning to FIG. 3, the slice level signals PML + to EXTL− output from the slice level setting circuit 109 are supplied to the error detection circuit 110. This error detection circuit 110 includes:
Reproduced signal Sr from which noise has been removed by low-pass filter 107
Is supplied.

The error detection circuit 110 detects a P-MOD error, an N-MOD error, a missing error, and an extra error from the reproduction signal Sr. FIG. 5 shows the configuration of the error detection circuit 110.

In the figure, slice level signals PML + and PML- for detecting a P-MOD error are supplied to a comparator 301P, respectively.
The positive side of a and the negative side of the comparator 301Pb are supplied as comparison reference voltages. The reproduction signal Sr is supplied to the negative side of the comparator 301Pa and the positive side of the comparator 301Pb. From the comparator 301Pa, the reproduction signal Sr is output as the signal PML +
When it becomes larger, a negative pulse is output. The comparator 301Pb outputs a negative pulse when the reproduction signal Sr becomes smaller than the signal PML−.

The output signals of comparators 301Pa and 301Pb are P-MOD
It is supplied to the error pulse generation circuit 302P. In this error pulse generation circuit 302P, comparators 301Pa and 301Pb
The output pulse is synthesized and this is the P-MOD
It is output as an error pulse Ppm.

When detecting a P-MOD error, an N-MOD error, and a missing error, the MPU 101 controls the write control circuit 104 and the write current control circuit 105 (see FIG. 3). Is written with write data WDATA whose level changes every predetermined period, for example, every one clock period in synchronization with the write clock WCLK (shown in FIGS. 6 to 8A and B).

In the above configuration, if the reproduced signal Sr is as shown in FIG. 6C, the output signals of the comparators 301Pa and 301Pb are as shown in FIGS. Then, from the error pulse generation circuit 302P, as shown in FIG.
An error pulse Ppm is output.

In FIG. 5, slice level signals NML + and NML− for detecting an N-MOD error are supplied to the positive side of the comparator 301Na and the negative side of the comparator 301Nb, respectively, as comparison reference voltages. The reproduction signal Sr is supplied to the negative side of the comparator 301Na and the positive side of the comparator 301Nb. From the comparator 301Na, the reproduced signal Sr
When it becomes larger than ML +, a negative pulse is output. The comparator 301Nb outputs a negative pulse when the reproduction signal Sr becomes smaller than the signal NML−.

The output signals of comparators 301Na and 301Nb are N-MOD
It is supplied to the error pulse generation circuit 302N.

The reproduction signal Sr is supplied to the positive side of the comparator 303, and zero voltage is supplied to its negative side. comparator
The signal 303 outputs a high level when the reproduction signal Sr is higher than zero voltage, and outputs a low level signal when the reproduction signal Sr is lower.

The output signal of the comparator 303 is supplied to the zero cross pulse generation circuit 304. Zero cross pulse generation circuit 304
Outputs a zero-cross pulse ZCK synchronized with the rise and fall of the output signal of the comparator 303. This pulse ZCK is supplied to the error pulse generation circuit 302N.

The error pulse generation circuit 302N includes a comparator 30
An RS flip-flop which is set by a pulse output from 1Na and 301Nb and reset by a pulse ZCK is provided. Then, a negative pulse is output from the error pulse generation circuit 302N at the timing when the pulse ZCK is supplied in the reset state. The output signal of the error pulse generation circuit 302N is supplied to an AND gate 305.

The pulse ZCK output from the zero-cross pulse generation circuit 304 is supplied to the clock miss circuit 306. The clock miss circuit 306 is also supplied with the write clock WCLK. The clock miss circuit 306 includes an RS flip-flop that is set by the pulse ZCK and reset by the write clock WCLK. Then, a negative pulse is output from the clock miss circuit 306 at the timing when the write clock is supplied in the reset state. The output signal of the clock miss circuit 306 is supplied to the AND gate 305.

In the AND gate 305, a pulse output from the error pulse generation circuit 302N and a pulse output from the clock miss circuit 306 are combined, and this is output as an N-MOD error pulse Pnm.

In the above configuration, if the reproduced signal Sr is as shown in FIG. 7C, the output signals of the comparators 301Na and 301Nb are as shown in FIGS. The output signal of the comparator 303 is as shown in FIG. D, and the zero cross pulse ZCK is output from the zero cross pulse generation circuit 304 as shown in FIG. Therefore, the output signal of the RS flip-flop in the error pulse generation circuit 302N is as shown in FIG.
2N, a pulse ZCK is generated as shown in FIG. 1 and a negative pulse is output at a portion where the level of the reproduction signal Sr falls within the range of NML + to NML-, and this is supplied to the AND gate 305.

Also, the output signal of the RS flip-flop in the clock miss circuit 306 is as shown in FIG. 10J, and the pulse ZCK is not generated from the clock miss circuit 306 as shown in FIG. A negative pulse is output at a portion where the level falls within the range of NML + to NML-, and this is supplied to the AND gate 305.

Accordingly, the N-MOD error pulse Pnm is output from the AND gate 305 as shown in FIG.

In FIG. 5, slice level signals MISL + and MISL- for detecting a missing error are supplied to the positive side of the comparator 301Ma and the negative side of the comparator 301Mb, respectively, as comparison reference voltages. The reproduction signal Sr is provided on the negative side of the comparator 301Ma and the positive side of the comparator 301Mb.
Is supplied. From the comparator 301Ma, the reproduction signal Sr
Is greater than the signal MISL +, a negative pulse is output. The reproduction signal Sr is output from the comparator 301Mb by the signal MISL.
When it becomes smaller, a negative pulse is output.

The output signals of the comparators 301Ma and 301Mb are supplied to a missing error pulse generation circuit 302M. This error pulse generation circuit 302M has a zero cross pulse generation circuit
The zero cross pulse ZCK output from 304 is supplied.

The error pulse generation circuit 302M includes a comparator 30
An RS flip-flop that is set by the pulses output from 1Ma and 301Mb and reset by the pulse ZCK is provided. Then, a negative pulse is output from the error pulse generation circuit 302M at the timing when the pulse ZCK is supplied in the reset state. The output signal of the error pulse generation circuit 302M is supplied to an AND gate 307.

The output signal of the clock miss circuit 306 is supplied to the AND gate 307. In the AND gate 307, a pulse output from the error pulse generation circuit 302M and a pulse output from the clock miss circuit 306 are synthesized, and this is supplied to the AND gate 308 as a missing error pulse Pmi.

In the above configuration, if the reproduced signal Sr is as shown in FIG. 8C, the output signals of the comparators 301Ma and 301Mb are as shown in FIGS. The output signal of the comparator 303 is as shown in FIG. D, and the zero cross pulse ZCK is output from the zero cross pulse generation circuit 304 as shown in FIG. Therefore, the output signal of the RS flip-flop in the error pulse generation circuit 302M is as shown in FIG.
From 302M, a pulse ZCK is generated as shown in FIG.
In addition, a negative pulse is output at a portion where the level of the reproduction signal Sr falls within the range of MISL + to MISL-,
Supplied to 7.

Also, the output signal of the RS flip-flop in the clock miss circuit 306 is as shown in FIG. 10J, and the pulse ZCK is not generated from the clock miss circuit 306 as shown in FIG. A negative pulse is output at a portion where the level falls within the range of MISL + to MISL-, and this is supplied to the AND gate 307.

Therefore, the missing error pulse Pmi is output from the AND gate 307 as shown in FIG.

In FIG. 5, slice level signals EXTL + and EXTL− for detecting an extra error are supplied to the positive side of the comparator 301Ea and the negative side of the comparator 301Eb, respectively, as comparison reference voltages. The reproduction signal Sr is provided on the negative side of the comparator 301Ea and the positive side of the comparator 301Eb.
Is supplied. From the comparator 301Ea, the reproduction signal Sr
Is greater than the signal EXTL +, a negative pulse is output. The comparator 301Eb outputs the reproduction signal Sr from the signal EXTL.
When it becomes smaller, a negative pulse is output.

Output signals of the comparators 301Ea and 301Eb are supplied to an extra error pulse generation circuit 302E. In this error pulse generation circuit 302E, comparators 301Ea and 301Ea
The pulses output from 01Eb are combined and supplied to the AND gate 308 as an extra error pulse Pex.

By the way, when detecting an extra error, MPU1
The write control circuit 104 and the write current control circuit 105 are controlled by 01 (see FIG. 3), and write data WDATA of a certain level is written to each track of the magnetic disk 1 (shown in FIG. 9A). That is, the detection of the extra error is not performed simultaneously with the detection of the P-MOD error, the N-MOD error, and the missing error.

In the above configuration, assuming that the reproduced signal Sr is as shown in FIG. 9B, the output signals of the comparators 301Ea and 301Eb are as shown in FIGS. Then, an extra error pulse Pex is output from the error pulse generation circuit 302E as shown in FIG.

Note that the missing error pulse Pmi output from the AND gate 307 and the extra error pulse Pex output from the error pulse generation circuit 302E are supplied to the AND gate 308. As described above, the detection of the missing error and the extra error is performed as described above. Are not performed simultaneously, and either the missing error pulse Pmi or the extra error pulse Pex is output from the AND gate 308.

Returning to FIG. 3, P output from the error detection circuit 110
The -MOD error pulse Ppm is supplied to the modulation window control circuit 111. In the window control circuit 111, a window pulse which rises at the first P-MOD error pulse Ppm and falls after a predetermined period Tw is formed (shown in FIG. 6G), and the P-MOD error pulse Ppm in this period Tw is formed.
Are counted. If the count value at the time when the window pulse falls is equal to or greater than a predetermined value, it is determined that there is a P-MOD error, and a P-MOD error detection pulse is output (shown in FIG. 7H). The error detection pulse is supplied to the modulation error write control circuit 112.

In the error write control circuit 112, when a P-MOD error detection pulse is supplied, a write enable signal MWE is output, P-MOD error information is written in the modulation error memory 113, and the status register
Reference numeral 114 denotes a state in which there is a P-MOD error.

The N-MOD error pulse Pnm output from the error detection circuit 110 is supplied to the modulation window control circuit 111. In this window control circuit 111, the first NM
A window pulse that rises at the OD error pulse Pnm and falls after a predetermined period Tw is formed (shown in FIG. 7M),
The number of N-MOD error pulses Pnm in this period Tw is counted. If the count value at the time of the fall of the window pulse is equal to or more than a predetermined value, it is determined that there is an N-MOD error, and an N-MOD error detection pulse is output (shown in FIG. N). The error detection pulse is supplied to the modulation error write control circuit 112.

In the error write control circuit 112, when an N-MOD error detection pulse is supplied, a write enable signal MWE is output, the information of the N-MOD error is written in the modulation error memory 113, and the status register
Reference numeral 114 denotes an N-MOD error.

FIG. 3 shows only one window control circuit 111 and one write control circuit 112 for simplicity of the drawing. However, FIG. 3 corresponds to each system of the P-MOD error and the N-MOD error. It is provided.

Further, the missing error pulse Pmi or extra error pulse Pex output from the error detection circuit 110 is supplied to the length counter 115. In the length counter 115, the counter counts up every time the error pulse Pmi or Pex is supplied.

Reference numeral 116 denotes a position counter. This position counter 1
The start signal Sst corresponding to the index signal S IND (shown in FIG. 2A) is supplied to the counter 16 from the local bus 103 as a reset signal of the counter. Further, a write clock WCLK is supplied to the position counter 116, and the position counter 116 is counted up every time the clock WCLK is supplied.
That is, the count output of the position counter 116 indicates the position of the track on which the error is to be detected.

Further, the error pulse Pmi or Pex output from the error detection circuit 110 is supplied to the sishing / extra error write control circuit 117. This error write control circuit 112
Is constituted by, for example, a retrigger type mono-multi vibrator. The error write control circuit 117 outputs a pulse that rises at the first supplied error pulse and falls when the error pulse is no longer supplied (shown in FIGS. 8M and 9F). It is supplied to the missing / extra error memory 118 as a write enable signal EWE.

The count output of the length counter 115 and the count output of the position counter 116 are supplied to the error memory 118. Then, at the time when the write enable signal EWE falls, the respective count values (length data, position data) are written to the error memory 118. The length counter 115 is supplied with the write enable signal EWE, and is reset immediately after the count value is written.

The write enable signal EWE from the error write control circuit 117 is supplied to the status register 114,
The status register 114 is in a state where a missing error or an extra error is present.

Note that the track is reproduced using the error detection, and after the error detection is completed as described above, the MP
U101 checks the status of the status register 114, and when the status is in an error state, the corresponding error memory 11
Error information is read out from 3, 118, and the error state is displayed on the monitor 119, for example.

Then, in the same manner as described above, the reproduction of the next track is sequentially performed, and the error detection is performed by the circuits below the error detection circuit 110.

FIG. 3 does not show signals existing between the encoder and the controller 7 as shown in FIG. 1 for simplification of the drawing.

Thus, in the present example, the error detection circuit 110 uses N
When detecting a MOD error and a missing error, the zero cross pulse ZCK from the zero cross pulse generation circuit 304 is used to output an error pulse Pmi or Pex. On the other hand, when the reproduction signal Sr has a zero voltage and the zero cross pulse ZCK cannot be obtained, the error pulse Pmi or Pex is output using the write clock WCLK (see FIGS. 5 and 8). In other words, if the zero-cross pulse ZCK cannot be obtained, a PLL oscillator is prepared as in the past, and the oscillation signal is not used in place of the zero-cross pulse ZCK. Since it is synchronized with Sr, accurate error detection can be performed without complicating the circuit configuration,
As a result, a defect of the magnetic disk 1 can be accurately detected.

Further, in this example, when setting the slice level, the slice level setting circuit 109 first supplies a stable DC voltage V REF to the VF converter 203 and rotates the magnetic disk 1 at the same rotation speed as that at the time of error detection. , Accumulator 205 accumulates data for one index period ND RE
F ′ is obtained, and a stable DC voltage V REF is supplied to the VF converter 203.
And the accumulated data ND RE of the accumulator 205 when the magnetic disk 1 is rotated at a predetermined rotation speed.
The slice level data DSLP, DSNL, DSLM and DSLE are corrected in accordance with the ratio between F and the above-described accumulated data NDREF '(see equation (1) and FIG. 4). As a result, the number of rotations of the magnetic disk 1 changes and the one index period changes. Even if it fluctuates, accurate slice level signals PML + to EXTL- corresponding to the track average voltage can be obtained. Slice level data D SLP, D SLN, D
The calculation in the MPU 101 for obtaining the SLM and the D SLE need only be performed once at the beginning if the rotation speed is the same, and it is not necessary to perform the calculation every time an error is detected in each track, thereby increasing the processing speed of error detection. be able to. That is, in this example, as described above, the processing speed of error detection can be increased without requiring a circuit for separately measuring one index period.

In the above-described embodiment, an example of an apparatus for detecting a defect of a magnetic disk (hard) has been described.
Of course, the present invention can be similarly applied to an apparatus for inspecting a defect of another magnetic recording medium such as a floppy disk or a magnetic tape.

[Effects of the Invention] As described above, according to the present invention, when there is no detection signal of the zero crossing point, an error is detected by using a write clock synchronized with a reproduction signal, so that the circuit configuration is complicated. , It is possible to perform accurate error detection, and it is possible to accurately detect defects in the magnetic recording medium.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the entire embodiment of the present invention, FIG. 2 is a diagram showing the timing of an index signal and the like, FIG. 3 is a block diagram of a read / write tester, and FIG. FIG. 5 is a configuration diagram of an error detection circuit, FIG. 6 to FIG. 9 are diagrams showing various error detection operations,
FIG. 10 is a diagram for explaining various errors that occur in a reproduced signal. DESCRIPTION OF SYMBOLS 1 ... Magnetic disk 2 ... Magnetic head 5 ... Read / write tester 7 ... Encoder 8 ... Controller 101 ... MPU 108 ... Envelope detection circuit 109 ... Slice level setting circuit 110 ... Error detection circuit 201 ... … Changeover switch 202… Voltage / frequency converter 205… Accumulator 206, 207P, 207N, 207M, 207E… D / A converter 302P… P-MOD error pulse generation circuit 302N… N-MOD error pulse generation circuit 302M …… Missing error pulse generation circuit 302E …… Extra error pulse generation circuit 304 …… Zero cross pulse generation circuit 306 …… Clock miss circuit

Claims (1)

(57) [Claims] A zero-cross detection circuit for detecting a zero-cross point from a reproduction signal from a magnetic recording medium on which write data is recorded in synchronization with a write clock; a voltage comparison circuit for comparing the reproduction signal with a reference voltage; Based on the output signals of the zero-cross detection circuit and the voltage detection circuit, an error in the reproduction signal is detected. When the zero-cross detection circuit does not detect a zero-cross point from the reproduction signal, An error detection circuit for detecting an error in the reproduction signal using a write clock; and a defect detection device for a magnetic recording medium.