JPH09101835A - Low-noise and high-reliable information processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce unnecessary radiation noise by multiplexing constitutional elements to be driven by clocks and distributing a clock consisting of a different frequency component to a certain constitutional element. SOLUTION: Respective parts (a) to (c) in a clock generation part 1 respectively apply clock outputs 2 to 4 to corresponding data processors 5 to 7 as their operation references, and when abnormality is generated in any one of the processors 5 to 7, respective outputs 8 to 10 from the processors 5 to 7 are inputted to a collation part 11, which detects whether all the three outputs 8 to 10 coincide with each other or not. The detection output 12 of the collation part 12 is outputted to the external to inform of whether the processors 5 to 7 are in normal operation states or abnormality is generated. Since frequency components respectively generated from constitutional elements can be dispersed, the level of an unnecessary radiation noise can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus which is required to have high performance and high reliability, and more particularly to an information processing apparatus which has a low output level of unnecessary radiation noise.

[0002]

2. Description of the Related Art Semiconductor integrated circuits having various functions are components of an information processing device. These semiconductor integrated circuits may lose their expected functions due to physical causes such as deterioration of internal functional elements, disconnection or short-circuiting of inter-element wiring, or mixing of various noises. As a result of such a semiconductor integrated circuit failure, the system may lose its function.

Transportation, aviation, space, automobile, medical care, electric power,
In financial online, plant control, etc., if the electronic devices and computer systems used lose their functions, they will suffer a great deal of damage or even be fatal to human life. Therefore, the issue of how to secure the reliability of the semiconductor integrated circuit is important.

On the other hand, as the speed of semiconductor integrated circuits has increased, the problem of unnecessary radiation noise of control equipment and the like has been taken up in recent years. Regulation of radiated noise of electronic devices is being implemented worldwide, and manufacturers are making efforts to reduce radiated noise.

There are two methodologies for increasing the reliability of equipment. The first is a fault avoidance that seeks to improve the reliability of the components themselves.
e) Technology, and the second is fault tolerance, which anticipates that a component will fail and introduces redundancy to minimize the adverse effects of the failure.
tolerance) technology. In fact, efforts are being made to achieve high reliability by combining these two approaches.

In order to realize fault tolerance, it is necessary to detect an error caused by a failure. It is well known that a component is multiplexed and the same operation is performed, and when a plurality of outputs are compared and collated to detect a mismatch, it is considered that an error has occurred. As a method for improving the reliability of information processing devices, "Fault Tolerant System Theory" edited by The Institute of Electronics, Information and Communication Engineers, June 1990,
Several implementation methods are known in the art, as described on pages 246-250.

[0007]

The following problems arise when trying to achieve high reliability by multiplexing.

Conventionally, it has been premised that the multiplexed components are operated with clocks having the same specifications. When the constituent elements are multiplexed, they are operated with clocks having the same frequency component. However, a particular problem with unnecessary radiation noise is noise based on harmonic components up to high-order (integer multiple) of the clock frequency. This is because the operation of each part in the device is defined based on the clock. Therefore, there is a problem that noise components of a specific frequency are piled up and strengthened only by multiplexing.

[0009]

The present invention is to solve the above-mentioned problems. That is, while suppressing the output level of the unnecessary radiation noise, the constituent elements are multiplexed to realize high reliability.

The present invention comprises the following means. That is, it is a clock generating unit that distributes a clock having a frequency component different from the other components to at least one of the components of the multiplex configuration that operates with a clock.

By the above means, the components of the electronic equipment are multiplexed and the components are operated by the clocks having different frequency components, so that the frequency components generated from each component can be dispersed.

Therefore, the present invention makes it possible to reduce the level of unnecessary radiation noise in a highly reliable information processing apparatus.

[0013]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

Although the present embodiment has a triple system configuration, it does not limit the present invention, and a double system or a four system is used.
It may be a heavy system or more.

FIG. 1 is a block diagram of an embodiment showing an outline of the present invention.

The data processing devices 5, 6 and 7 respectively perform the same predetermined processing, and are expected to output the same result to the outputs 8, 9 and 10 as long as the normal operation is continued. . On the other hand, the data processing device 5,
If an error occurs in either 6 or 7, the output is 8, 9,
Expect 10 discrepancies to occur. The collating unit 11 detects whether or not all the three outputs 8, 9 and 10 are coincident with each other, and the output 12 notifies the outside of whether the normal operation state or the abnormality has occurred. . In addition,
The collating unit 11 outputs one of the outputs 8, 9 and 10 to the other 2
If it is possible to detect that there is no match with the other party, a majority vote can be made and the operating rate of the system can be increased. The clock generator 1 has the features of the present invention. The clock outputs a, b and c (2, 3, 4) are given to the data processing devices 5, 6 and 7, respectively, and serve as a reference for operation. In the prior art, clocks having the same frequency component are given to the data processing devices 5, 6 and 7, but in the present invention, at least one clock output has a different frequency component from the other.

An embodiment of the clock generator will be described below.

FIG. 2 is an embodiment showing the internal configuration of the clock generator 1 in FIG.

Clock outputs 22, 23, 24 correspond to clock outputs 2, 3, 4 in FIG. In this embodiment, the clock outputs 22, 23 and 24 have the same frequency, but the duty ratios (ratio of high potential level time and low potential level time) are different from each other. It is well known from signal processing theory that the output level of the frequency component (an integer multiple of the original oscillation frequency) of the rectangular wave changes by changing the duty ratio.

The clock generation circuits 13, 14 and 15 are original oscillation circuits, and the three have the same frequency and the same duty ratio (high potential level time: low potential level time = 50%: 50).
%) Is output (16, 17, 18). On the other hand, the duty adjusting circuits 19, 20, and 21 output clocks having different duty ratios. The duty adjusting circuit 19 in the figure shows one embodiment thereof, and can be constructed by connecting the diode 25, the capacitor 26, the resistor 27 and the Schmitt trigger type buffer 29 as shown in the figure. The high potential level time at the connection point 28 can be determined by the values of the capacitor 26 and the resistor 27. The Schmitt trigger type buffer 29 is for shaping the waveform. To output clocks with different duty ratios, the duty adjusting circuits 19, 20, 2
1 The time constants of the capacitors and resistors may be different.

As an improvement of this embodiment, the clock generation circuits 13, 14 and 15 may be combined into one clock generation circuit to reduce the cost. Alternatively, the reliability may be increased by multiplexing. Alternatively, the duty adjusting circuits 19, 20, 2
One of them may be omitted, and the output of the original oscillator circuit may be used as it is to reduce the cost.

FIG. 3 is another embodiment showing the internal structure of the clock generator 1 in FIG.

The clock outputs 36, 37 and 38 correspond to the clock outputs 2, 3 and 4 in FIG. In this embodiment, the clock outputs 36, 37 and 38 have the same duty ratio but different frequencies. It is well known from signal processing theory that the frequency component of a rectangular wave changes depending on the frequency.

The clock generator circuits 33, 34 and 35 are original oscillator circuits, and are crystal oscillators X'tal 30 and X'tal.
The three output clocks having different frequencies f1, f2, and f3 depending on the difference in capacity of 31, X'tal 32 (3
6, 37, 38).

Note that this embodiment may be used in combination with the above-mentioned first embodiment to diversify the duty ratio.

FIG. 4 shows still another embodiment showing the internal structure of the clock generating means 1 in FIG.

The clock outputs 54, 55, 56 correspond to the clock outputs 2, 3, 4 in FIG. In this embodiment, the clock outputs 54, 55 and 56 are made to have different frequency components in time series according to a predetermined procedure. According to this embodiment, each component has the same processing speed and power consumption on average, and the load can be evenly distributed.

The clock generation circuits 39, 40 and 41 are original oscillation circuits, and the three output the same frequency clocks (42, 43 and 44). Random number generation circuits 45, 46, 47
Follows a predetermined procedure and does not output the same value at the same time. The outputs 51, 52 and 53 of the random number generating circuits 45, 46 and 47 are connected as frequency division ratio inputs of the frequency dividing circuits 48, 49 and 50 for dividing the clock. The frequency dividing circuits 48, 49 and 50 divide the clocks 42, 43 and 44 in accordance with these frequency dividing ratio inputs and generate outputs. In this way, the clock outputs 54, 55, 56 can be such that they do not output the same frequency at the same time.

FIG. 5 shows the frequency dividing circuit 4 of the embodiment shown in FIG.
8 shows the details of the random number generation circuit A45.

The random number generation circuit 45 includes a frequency divider 64, a counter 65, a power-on reset circuit 67, and a code conversion circuit 6.
It consists of eight. The counter 65 is generally called a 3-bit Johnson counter, and the output 75 is sequentially
Six values of 000, 100, 110, 111, 011 and 001 (binary notation) are repeatedly output. Frequency divider 64
Divides the clock 42 by 1/16, and its output 74 is connected to the clock input of the counter 65 to update the value of the counter 65. The power-on reset circuit outputs a reset signal when the power is turned on, is connected to the counter 65 (66), and sets the counter value to 000 at startup. The code conversion circuit 68 outputs the output 75 of the counter 65.
The pseudo random number (4 bits) is output (51) based on the above. As shown in the figure, the output value was determined corresponding to the input value. For example, the input value 000, the output value 0100,
An output value of 1000 is immediately output for an input value of 100.

The frequency dividing circuit 48 includes a counter 63 and a comparator 5.
9, a latch 60, D flip-flops 58 and 62, an exclusive OR gate 61, and an inverter gate 57. The counter 63 is a 4-bit binary counter that sequentially counts up with the inverted clock signal 69. On the other hand, the output 51 of the random number generation circuit is the latch 60.
Hold by. The comparator 59 outputs the output 7 of the counter 63.
2 is compared with the value of the output 73 of the latch 60, and when they match, the output 98 is asserted. Exclusive OR gate 61 and D flip-flop 62 when output 98 is asserted.
This causes the output 54 to perform an inversion operation. The asserted output of the comparator 59 is made to appear at the output 70 via the D flip-flop 58.
Is reset to 0000. Further, the latch 60 newly takes in the value of the output 51 of the random number generation circuit.

FIG. 6 is a time chart showing the operation of the configuration shown in FIGS.

The numbers in parentheses in the figure correspond to those in FIG.

The random number generation circuits 45, 46, 47 update the output value every 16 cycles of the input clocks 42, 43, 44. Output value (RND51, RND5 in FIG. 5
2, RND53) is a pseudo random value {7, 5, 4, 8, 6,
3} in order. It was set to take different initial values "4, 6, 7" when the operation was started up. The frequency divider circuit samples the value of the frequency division ratio input immediately after inverting the output (changing from high level to low level or from low level to high level), and next time the clock is counted by the sampled value. The output inversion timing is set. The clock outputs 54, 55 and 56 thus obtained do not have the same period at the same time as shown in the figure, and the same frequency components do not strengthen each other.

The pseudo random number setting value and the frequency dividing method of this embodiment do not limit the present invention, and may be set so that clock outputs do not output the same frequency component at the same time. For example, the duty may be changed each time instead of the frequency division method in which the frequency is changed.

FIG. 7 shows the periphery of the collating unit 11 in FIG. 1 in more detail.

The output interfaces of the data processing devices 5, 6, 7 are data outputs 76, 79, 82, data ready signal outputs 77, 80, 83, and weight inputs 78, 78.
81 and 84 are provided. The data ready signal is asserted when the data output is valid. At this time, if the wait input is asserted, the state of outputting the data is maintained. Such interfaces are found in many microprocessors.

Now, according to the present invention, the outputs of the three data processing devices 5, 6 and 7 operating with different frequency clocks output data at different timings. The present embodiment shows a structure in which waiting is performed by data ready and wait for collation, and a period in which the data outputs 76, 79, and 82 are simultaneously asserted is provided. The waiting control circuit 93 is the control circuit,
For the data processing device that asserted data ready earlier than others, the wait is asserted to extend the data output. When receiving the data ready from the plurality of data processing devices, the determination circuit 92 is notified.

The comparators 85, 86, 87 compare and collate the three data outputs 76, 79, 82. Based on the comparison results 88, 89, 90, the determination circuit 92 determines that the plurality of data processing devices that output matching outputs are normal and outputs which data processing device is normal / abnormal. (12).

FIG. 8 shows an example of how to use the output of the configuration 96 shown in FIG.

Outputs 8, 9, of the data processing devices 5, 6, 7
10 is selected by the selection circuit 94. Only the output regarded as normal is output to the outside by the signal 12 notified from the collating unit.

[0042]

According to the present invention, if the components of the electronic equipment are multiplexed, the frequency components generated from the respective components can be dispersed.

Therefore, the present invention enables a reduction in the level of unnecessary radiation noise in a highly reliable information processing device.

Further, since the operation timings of the constituent elements are different, the effect of suppressing the occurrence rate of the same error due to external noise can be expected.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a block diagram showing the configuration of an embodiment of a clock generation unit.

FIG. 3 is a block diagram showing the configuration of an embodiment of a clock generation unit.

FIG. 4 is a block diagram showing a configuration of an embodiment of a clock generation unit.

FIG. 5 is a block diagram showing the configuration of an embodiment of a clock generator.

FIG. 6 is a time chart showing an operation example of the clock generating means.

FIG. 7 is a block diagram showing the configuration of an embodiment of a matching unit.

FIG. 8 is a block diagram showing a configuration of an example.

[Explanation of symbols]

1 ... Clock generator, 5, 6, 7 ... Data processing device, 1
1 ... collation unit, 19, 20, 21 ... duty adjustment circuit,
48, 49, 50 ... Dividing circuit.

 ──────────────────────────────────────────────────の Continuing on the front page (72) Inventor Takashi Hotta 7-1-1, Omika-cho, Hitachi City, Ibaraki Prefecture Within Hitachi Research Laboratory, Hitachi, Ltd.

Claims (6)

[Claims] 1. An information processing apparatus, comprising: a component configured to operate with a clock in a multiplexed configuration, and having means for distributing a clock having a frequency component different from the other components to at least one component. 2. The information processing apparatus according to claim 1, further comprising means for distributing to the at least one component a clock having a predetermined duty ratio different from the others. 3. The information processing apparatus according to claim 1, further comprising means for distributing a clock having a frequency different from a predetermined one to the at least one constituent element. 4. The information processing apparatus according to claim 2, wherein frequencies of clocks to the constituent elements are different from each other and are predetermined. 5. An information processing apparatus, wherein clocks to at least one constituent element have frequency components which are time-sequentially different according to a predetermined procedure. 6. The information processing apparatus according to claim 5, wherein the information processing apparatus has a plurality of components having a multiplex structure.