JPH0897423A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE: To provide a method of manufacturing MOS transistor wherein the short channel effect can readily be restrained. CONSTITUTION: A groove 105aa is formed in a silicon nitride film 104 and an N-type ion implantation region 121a of low concentration is formed by ion implantation of arsenic at an angle of γ to a sidewall of the groove 15aa. A gate oxide film 122a is formed in a bottom part of the groove 105aa, a gate electrode 123a for filling the groove 105aa is formed, the silicon nitride film 104 is removed, a spacer 124a is formed and an N<+> -type diffusion layer 125aa is formed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a MOS transistor having an LDD structure.

[0002]

2. Description of the Related Art A semiconductor device including a MOS transistor is miniaturized, for example, by reducing the gate length of the MOS transistor. Although the current driving capability of the MOS transistor is increased by shortening the gate length, if the source / drain region of the MOS transistor is formed only from the high-concentration impurity diffusion layer, the electric field strength at the drain end on the channel region side is The rise in temperature intensifies the generation of hot carriers, and these hot carriers are likely to be injected into the gate insulating film. As a result, the transistor characteristics are deteriorated, such as the fluctuation of the threshold voltage and the reduction of the current driving capability. An LDD structure is usually adopted to suppress the generation of hot carriers.

When the design rule becomes a submicron rule, it becomes important to consider the fine structure of the LDD structure itself. In the normal LDD structure, the boundary between the low-concentration diffusion layer and the high-concentration diffusion layer in the source / drain region forming the LDD structure is not directly under the gate electrode, but directly under the spacer made of an insulating film formed on the side surface of the gate electrode. Exists in at least part of the low-concentration diffusion layer. This structure firstly causes problems in current drive capability. The low-concentration diffusion layer located immediately below the spacer has a reduced transconductance between the drain region and the source region, which lowers the current driving capability. Also,
When the boundary between the low-concentration diffusion layer and the high-concentration diffusion layer in the source / drain region of the LDD structure is located directly under the spacer, the injection of hot carriers into the gate oxide film is low, but the injection of hot carriers into the spacer is low. Therefore, it becomes difficult to sufficiently suppress the deterioration of the transistor characteristics.

To solve these problems, there is a gate overlap LDD structure. An example of this gate-overlap LDD structure is different from a normal LDD structure as disclosed in Japanese Patent Laid-Open No. 1-307266, and the low-concentration diffusion layer also has a boundary between the low-concentration diffusion layer and the high-concentration diffusion layer. Is also provided directly below the gate electrode.

Referring to FIG. 11 which is a sectional view of a main manufacturing process of a semiconductor device, a summary of a method of manufacturing a MOS transistor having a gate overlap LDD structure described in the above publication is as follows.

First, a field oxide film 203 is formed in an element isolation region on the surface of a P-type silicon substrate 201, and a gate oxide film 222 is formed in an element formation region. Before or after forming the gate oxide film 222, boron ion implantation for threshold control is performed. Then, the gate electrode 223 is formed. The width (gate length) of the gate electrode 223 is L. After that, the field oxide film 2
03 and the gate electrode 223 as a mask, ion implantation of low-concentration N-type impurities is performed at an angle of θ with respect to a vertical line to the surface of the P-type silicon substrate 201 to form an N-type ion implantation region 221a. FIG. 11A].

Next, a silicon oxide film (not shown) having a desired film thickness is formed on the entire surface. This silicon oxide film is etched back by anisotropic etching, and the gate electrode 22
The spacer 224 is formed on the side surface of the No. 3 side. Using the field oxide film 203, the gate electrode 223 and the spacer 224 as a mask, ion implantation of high-concentration N-type impurities is performed substantially perpendicularly to the surface of the P-type silicon substrate 201.
Further heat treatment is performed. By this series of processing, N
^{A +} type diffusion layer 225 is formed, and the N type ion implantation region 221a is converted into an N ⁻ type diffusion layer 221b.
Source / drain regions composed of the ⁻ type diffusion layer 221b and the N ⁺ type diffusion layer 225 are formed [FIG. 11 (b)].

[0008]

The MOS transistor having the gate overlap LDD structure described in the above publication has the N ⁺ type diffusion layer 225 and the N ⁻ type diffusion layer 22.
Since the boundary of 1b is directly under the gate electrode 223, etc., the decrease of the mutual conductance between the drain region and the source region is surely suppressed. However, as estimated from the shape of the N-type ion implantation region 221a (see FIG. 11A), there is a concern that the short channel effect is likely to occur. In order to verify this, the present inventor tried a simulation in the case where this MOS transistor was created under the following conditions.

The P-type silicon substrate 201 has a (100) plane orientation and contains 5.0 × 10 ¹⁶ cm ⁻³ boron as a P-type impurity. The gate oxide film 222 is formed by thermal oxidation and has a film thickness of 10 nm. Ion implantation of boron for threshold control is performed before forming the gate oxide film 222 under the conditions of 30 keV, 4.0 to 6.0 × 10 ¹² c.
m ^-2 . The gate electrode 223 is made of an N ⁺ type polycrystalline silicon film and has L = 0.6 μm. 70 keV,
Arsenic is ion-implanted under the conditions of 8.0 × 10 ¹³ cm ^-2 and θ≈50 ° to form the N-type ion-implanted region 221a. The width of the spacer 224 is about 100 nm. 70
After ion implantation of arsenic under the conditions of keV and 3.0 × 10 ¹⁵ cm ⁻² , heat treatment is performed at 900 ° C. for 10 minutes in a nitrogen atmosphere, and N ⁺ type diffusion layer 225 (and N ⁻ type diffusion layer 221
b) is formed.

At this time, the profile of arsenic near the drain edge is as shown in FIG. The side surface and the bottom surface of the N ⁺ type diffusion layer 225 in the drain region (and the source region) are covered with the N ⁻ type diffusion layer 221b, and X _j (junction depth) of this drain region is approximately 0.16 μm. N
^The overlap between the ⁻ type diffusion layer 221b and the gate electrode 223 is about 0.16 μm, and the overlap between the N ⁺ type diffusion layer 225 and the gate electrode 223 is about 0.1 μm. Two findings can be obtained from this profile. First of all, the position in the depth direction of the N ⁻ type diffusion layer 221b immediately below the gate electrode 223 does not change.
That is, the source region side N ^- type diffusion layer 221b and the drain region side N ^- type diffusion layer 221b and the interval does not change much in the depth direction. Second, the end of the N ⁻ type diffusion layer 221b, the N ⁺ type diffusion layer 225, and the N ⁻ type diffusion layer 221b.
The distance from the boundary position of is small. That is, the impurity concentration gradient during this period is high.

From the first feature of the above profile of arsenic near the drain edge, the inferred event becomes clear. The depletion layer generated when a voltage is applied to the drain region has a great influence on the depletion layer generated when a voltage is applied to the gate electrode 223. For example, punch-through occurs at a deep position from the gate oxide film 222 in the channel region. It tends to occur and the short channel effect increases. Further, from the second feature, the position where the electric field strength is highest on the drain side is directly under the gate electrode, and hot carriers are injected into the gate oxide film 222 (although it is improved as compared with the conventional normal LDD structure). Avoidance is not enough.

Therefore, an object of the method of manufacturing a semiconductor device of the present invention is to provide an MO having a gate overlap LDD structure.
It is an object of the present invention to provide a manufacturing method that makes it possible to suppress the short channel effect and suppress the injection of hot carriers into the gate insulating film in the S transistor.

[0013]

According to a first aspect of a method of manufacturing a semiconductor device of the present invention, a field oxide film and a pad oxide film are formed in an element isolation region and an element formation region on the surface of a silicon substrate of one conductivity type. Then, a step of forming a silicon nitride film of a predetermined thickness on the surface of the silicon substrate to cover the surface of the field oxide film and the pad oxide film, and a selective difference with respect to the silicon nitride film using the photoresist film pattern as a mask. Forming a groove in the silicon nitride film that has a predetermined width and a desired length in a certain direction across the device formation region through the pad oxide film by means of isotropic etching; Ion-implanting a low-concentration impurity of opposite conductivity type into the surface of the silicon substrate from a direction orthogonal to the direction and forming a predetermined angle with respect to the side wall of the groove; Removing the pad oxide film on the bottom surface of the, and forming a gate oxide film by thermal oxidation, forming a gate electrode having a form of filling the groove, and selectively removing the silicon nitride film, A step of forming an insulating film on the entire surface and etching back the insulating film to form a spacer made of the insulating film on the side surface of the gate electrode, and using the field oxide film, the spacer and the gate electrode as a mask, And ion-implanting the opposite conductivity type impurity into the element forming region.

Preferably, a second groove having a width different from the predetermined width is formed together with the groove, the second groove is covered with a second photoresist film pattern, and the low-concentration reverse conductivity type impurity is formed. Are ion-implanted into the surface of the silicon substrate to remove the second photoresist film pattern.

According to a second aspect of the semiconductor device of the present invention, a field oxide film and a pad oxide film are formed in an element isolation region and an element formation region on the surface of a one conductivity type silicon substrate, and the field oxide film and the pad oxide film are formed. The pad oxide film is formed by a step of forming a silicon nitride film of a predetermined thickness on the surface of the silicon substrate to cover the surface of the oxide film and by selective anisotropic etching of the silicon nitride film using the photoresist film pattern as a mask. Forming a groove having a predetermined width and a desired length in a certain direction in the silicon nitride film across the element formation region via
A step of ion-implanting a low-concentration impurity of opposite conductivity type into the surface of this silicon substrate from a direction orthogonal to the above-mentioned fixed direction and forming a predetermined angle with respect to the sidewall of the groove, and forming a silicon oxide film on the entire surface. , A step of etching back the silicon oxide film to form a spacer made of the silicon oxide film on the side wall of the groove, forming a gate oxide film by thermal oxidation, and forming a gate electrode having a state of burying the groove. And a step of selectively removing the silicon nitride film, and a step of ion-implanting a high-concentration impurity of opposite conductivity type into the element formation region using the field oxide film, the spacer and the gate electrode as a mask. It is characterized by having.

Preferably, after the silicon nitride film is selectively removed, an insulating film is formed on the entire surface, the insulating film is etched back, and a second spacer made of the insulating film is formed on the side surface of the gate electrode. There is a step of forming.

According to a third aspect of the method of manufacturing a semiconductor device of the present invention, a field oxide film and a pad oxide film are formed in an element isolation region and an element formation region on the surface of a one conductivity type silicon substrate, and the field oxide film is formed. And a step of forming a silicon nitride film having a first predetermined thickness on the surface of the silicon substrate to cover the surface of the pad oxide film, and using the first photoresist film pattern made of the first photoresist film as a mask. By the anisotropic etching selective to the silicon nitride film, it crosses over the element forming region through the pad oxide film and has a predetermined width and is bent in the first direction and the second direction. And forming a second photoresist film having a desired film thickness on the entire surface of the silicon nitride film and forming a groove having a length of at least on the portion having the first direction. A second photoresist film pattern having an opening for the groove is formed, and the second photoresist film pattern is anisotropically etched until a second predetermined film thickness smaller than the first predetermined film thickness is obtained. And a step of selectively etching back by
And removing the second photoresist film pattern by ion-implanting a low-concentration impurity of opposite conductivity type into the surface of the silicon substrate from a direction forming a predetermined angle with respect to the side wall of the groove. And a third film with the required film thickness on the entire surface
Forming a photoresist film, forming a third photoresist film pattern having an opening for at least the groove in the portion having the second direction, and forming a second photoresist film thinner than the first predetermined film thickness. A step of selectively etching back the third photoresist film pattern by anisotropic etching until a predetermined film thickness is obtained, and a sidewall of the groove at a portion orthogonal to the second direction and having the second direction. A step of ion-implanting a low-concentration opposite conductivity type impurity into the surface of the silicon substrate from a direction forming the predetermined angle to remove the third photoresist film pattern, and the pad on the bottom surface of the groove. A step of removing the oxide film and forming a gate oxide film by thermal oxidation, a step of forming a gate electrode having a state of burying the groove, and a step of selectively removing the silicon nitride film to completely cover the entire surface. Forming a film and etching back the insulating film to form a spacer made of the insulating film on the side surface of the gate electrode; and using the field oxide film, the spacer and the gate electrode as a mask, a high-concentration reverse conductivity And ion-implanting type impurities into the element formation region.

Preferably, the etching back for the second and third photoresist film patterns is plasma etching by microwave excitation in which an RF bias is applied to the silicon substrate and a gas containing at least oxygen gas is used as an etching gas. Is.

[0019]

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a plan view of the manufacturing process of the semiconductor device.
2 and FIG. 3 which is a sectional view taken along line XX of FIG. 1 or 2, the first embodiment of the present invention is as follows.

First, in the element formation region and the element isolation region on the surface of the P-type silicon substrate 101 having the (100) plane orientation and containing 5.0 × 10 ¹⁶ cm ⁻³ of boron as the P-type impurity, the film thickness is formed. A pad oxide film 102 and a field oxide film 103 having a thickness of about 10 nm are formed. The field oxide film 103 is formed by a selective oxidation method using a silicon nitride film (not shown) as a mask.
After 03 is formed, this silicon nitride film is removed by etching. As the pad oxide film 102, the one provided before forming the field oxide film 103 may be used as it is, or may be newly formed after forming the field oxide film 103. Next, a predetermined film thickness H (for example, 0.42 μ
The silicon nitride film 104 of m) is formed on the entire surface. Next, the silicon nitride film 1 is anisotropically etched by using a first photoresist film pattern (not shown) as a mask.
04 is selectively etched to form the first groove 105aa and the second groove 105ab. Subsequently, boron ion implantation for threshold control is performed at 30 keV, 4.0.
It is carried out under the condition of ˜6.0 × 10 ¹² cm ⁻² . Groove 105
aa has a predetermined width L (for example, 0.6 μm), and has a desired length in a certain direction. On the other hand, the groove 105a
b has a width different from L (for example, a width wider than L), and the direction of the groove 105ab does not always face the above-mentioned fixed direction. As will be described later, the grooves 105aa and 105ab have MOs having different channel lengths.
The gate electrode of the S transistor is formed [FIG. 1 (a), FIG. 3 (a)].

After removing the first photoresist film pattern, the groove 105ab is covered with the second photoresist film pattern 111a. The purpose is to make the channel length of the MOS transistor formed in the groove 105ab having L different from L different from the channel length of the MOS transistor formed in the groove 105aa. Next, it goes straight in the above-mentioned fixed direction and (previously) forms a predetermined angle θ with respect to the (two) side walls of the groove 105aa in this fixed direction.
70ke from (two) directions (eg 50 °)
Arsenic of V, 8.0 × 10 ¹³ cm ⁻² is ion-implanted, and an N-type ion-implanted region 121a is formed on the surface of the P-type silicon substrate 101 immediately below (two) sidewalls of the groove 105aa in a certain direction.
Is formed. (Details will be described later) At this time, tan
θ ≦ (L / H) [FIG. 1 (b), FIG. 3 (b)]. The photoresist film pattern 111a is formed in the groove 105a.
At the time of the above-mentioned ion implantation for a, it is necessary to be separated by a distance that does not serve as a mask.

Next, the photoresist film pattern 11 is formed.
1a is removed and the pad oxide film 102 on the bottom surface of the trenches 105aa and 105ab is formed using the silicon nitride film 104 as a mask.
Are etched away. For example, thermal oxidation at 750 ° C. forms the gate oxide film 122a with a film thickness of about 10 nm. By this thermal oxidation, the N-type ion implantation region 12 is formed.
The arsenic of 1a is activated and converted into the N ⁻ type diffusion layer 121aa. At this temperature, arsenic is activated, but thermal diffusion is scarcely performed. Then, the groove 10
Gate electrodes 123aa and 123ab having a state of burying 5aa and 105ab are formed. These gate electrodes 123aa and 123ab are made of N ⁺ type polycrystalline silicon film, refractory metal silicide film, refractory metal polycide film or refractory metal film [FIG. 2 (a), FIG. 3].
(C)]. In the manufacturing method described in JP-A-1-307266, the N-type ion implantation region (see FIG. 11A)
The constituent material of the gate electrode cannot be ignored in the ion implantation for forming the. On the other hand, the selection of the constituent material of the gate electrodes 123aa and 123ab in the present embodiment does not depend on the formation conditions of the N-type ion implantation region 121a. The pad oxide film 102 on the bottom surfaces of the trenches 105aa and 105ab is removed and a new gate oxide film 122 is formed.
The reason for forming a is that the pad oxide film 102 in this portion removes the pollution caused by the direct contact with the photoresist film and the damage caused by the ion implantation.

Next, the silicon nitride film 104 is selectively removed by, for example, hot phosphoric acid. Then, a silicon oxide film (not shown) having a film thickness of about 0.1 μm is formed on the entire surface by low pressure vapor deposition (LPCVD) or plasma excited vapor deposition (PECVD) having excellent step coverage. .
This silicon oxide film (and the pad oxide film 102) is etched back by anisotropic etching, and the gate electrode 1
Spacers 124a made of the silicon oxide film and having a width of about 0.1 μm are left on the side surfaces of 23aa and 123ab. Next, the field oxide film 103 and the gate electrode 123
Using the aa, 123ab and the spacer 124a as a mask, an element forming region on the surface of the P-type silicon substrate 101 (generally perpendicular to the surface of the P-type silicon substrate 101) is formed.
Ion implantation of arsenic is performed under the conditions of 0 keV and 3.0 × 10 ¹⁵ cm ⁻² . Furthermore, in a nitrogen atmosphere, 900 ° C, 1
A heat treatment of 0 minutes is performed. By these series of processing,
N ⁺ type diffusion layers 125aa and 125ab are formed, and the N ⁻ type diffusion layer 121aa undergoes thermal diffusion of arsenic to form N ^−.
It becomes the type diffusion layer 121ab. As a result, a MOS transistor having a gate overlap LDD structure including a source / drain region composed of the N ⁻ type diffusion layer 121ab and the N ⁺ type diffusion layer 125aa, a gate oxide film 122a and a gate electrode 123aa, and an N ⁺ type diffusion layer. Layer 12
A non-LDD structure MOS transistor including a source / drain region composed only of 5ab, a gate oxide film 122a and a gate electrode 123ab is formed. Since the N-type ion implantation region 121a is not formed in the non-LDD structure MOS transistor, the channel length as well as the channel length of the MOS transistor is different from the channel length of the MOS transistor of the gate overlap LDD structure. [Fig. 2 (b), Fig. 3
(D)].

FIG. 4A, which is a schematic sectional view of the step of forming the N-type ion implantation region, and the gate overlap L.
Referring to FIG. 4B showing the arsenic concentration distribution (profile) in the vicinity of the drain end of the MOS transistor having the DD structure, with reference to FIG. 4B, the conditions for forming the N-type ion implantation region in this embodiment and the effect of this embodiment. And explain.

(Thickness of the silicon nitride film 104) H≈0.
42 μm, (width of groove 105aa) L≈0.6 μm,
Only the region of ΔL≈0.1 μm from the lower end of the side wall of the groove 105aa is implanted into the silicon nitride film 104 without being masked. At this time, tan θ = (L−ΔL) /
Since it becomes H, θ≈50 ° [FIG. 4 (a)].
In addition, this L is M of the gate overlap LDD structure.
It is equal to the gate length (width of the gate electrode) of the OS transistor. Arsenic ions are implanted at this angle to form the N-type ion implantation region 121a, and the N ⁺ -type diffusion layer 125ab is formed.
Arsenic ion implantation for formation is performed under the above conditions,
When the heat treatment for activation is performed under the above conditions, the simulation result of the arsenic profile near the drain edge is as shown in FIG.

From FIG. 4B, the following can be obtained. The overlap between the gate electrode 123aa and the N ⁻ type diffusion layer 121ab becomes maximum at the interface between the gate oxide film 122a and the P type silicon substrate 10, and the value is about 0.18.
μm (about twice ΔL). N ⁻ type diffusion layer 121ab on the source region side and N ⁻ type diffusion layer 121 on the drain region side
The distance from ab (in the channel region) is as described in JP-A-1-
Gate overlap LD disclosed in Japanese Patent No. 307266
Unlike the MOS transistor having the D structure, the width becomes wider as the depth from the interface increases. The overlap between the gate electrode 123aa and the N ⁺ type diffusion layer 125aa at the interface is about 0.04 μm. This gate electrode 123aa
The maximum value of the overlap between the N ⁺ -type diffusion layer 125aa and the N ⁺ -type diffusion layer 125aa is at a depth of about 0.04 μm from this interface.
It is about 0.06 μm. The drain region near the gate electrode 123aa (N ⁻ -type diffusion layers 121ab and N ⁺
X _j of the type diffusion layer 125aa) is about 0.16 μm, but this drain region (N ⁺ type diffusion layer 125) at a position sufficiently separated from the gate electrode 123aa.
X _j of about 0.14 μm)
Is. Although it differs numerically depending on ion implantation conditions, etc.,
From a series of simulations, θ may be in the range of 40 ° to 60 ° to have the above tendency. The upper limit of ΔL is determined by the value of L and the target channel length. Δ
The lower limit of L is ion implantation conditions (including θ) for forming the N-type ion implantation region 121a, ion implantation conditions and heat treatment conditions for forming the N ⁺ -type diffusion layer 125aa, and the spacer 121.
Although it depends on the film thickness of a, etc., it is preferably a positive value in the above case.

From the shape of the source / drain regions as shown in FIG. 4B, it becomes clear that the MOS transistor of the gate overlap LDD structure according to this embodiment has the following effects. First, the gate electrode 123aa
N for ^- -type diffusion layer 121ab and N ⁺ -type diffusion layer 1
Due to the 25aa overlap shape, a reduction in transconductance between the drain and source regions is avoided. Further, due to the shape of the drain end on the side of the gate electrode 123aa, the influence of the depletion layer generated by applying the voltage to the drain region on the depletion layer of the channel region generated by applying the voltage to the gate electrode 123aa becomes small, and the short circuit occurs. -It becomes easy to suppress the channel effect. Further, the position where the electric field strength is highest on the drain side is the gate electrode 123.
Since the position is sufficiently distant from immediately below aa, it becomes easy to avoid injection of hot carriers into the gate oxide film 122a.

The film thickness of the pad oxide film 102, the film thickness H of the silicon nitride film 104, the width L of the groove 105aa, the film thickness and oxidation temperature of the gate oxide film 122a, and the spacer 124.
a, width of ion implantation for forming N-type ion implantation region 121a, ion implantation conditions, N + type diffusion region 1
Ion implantation conditions and heat treatment conditions for forming 25aa and the like are not limited to the numerical values or conditions described in the first embodiment. Further, although the MOS transistor according to the first embodiment is an N-channel type, this embodiment has a P-channel type MOS transistor or CM.
It can also be applied to an OS transistor.

FIG. 5 is a sectional view of the manufacturing process of the semiconductor device.
2, the second embodiment of the present invention is the same as the first embodiment until the formation of the silicon nitride film 104 having a predetermined film thickness (for example, H≈0.42 μm).

Next, by the same method as that of the first embodiment, a predetermined width (for example, L) similar to that of the first groove of the first embodiment is obtained.
≈0.6 μm), and a groove 105b having a desired length is formed in a fixed direction. Then, arsenic ions are implanted under the same angle (for example, .theta..apprxeq.50.degree.) And conditions as in the first embodiment to form the N-type ion implantation region 121b [FIG. 5 (a)].

Next, a silicon oxide film (not shown) having a film thickness of about 0.06 μm (60 nm) is formed on the entire surface by LPCVD or PECVD, and this silicon oxide film (and the pad oxide film 102) is anisotropy. The spacers 114 are formed on the sidewalls of the grooves 105b by selectively etching back by etching. Subsequently, the gate oxide film 122b having a film thickness of about 10 nm is formed by thermal oxidation at about 750 ° C. By this thermal oxidation, the N-type ion implantation region 121b is formed.
Becomes an N ⁻ type diffusion layer 121ba [FIG. 5 (b)].

After that, the silicon nitride film 104 is selectively removed by etching to form a gate electrode 123b having a state in which the trench 105b is buried. High-concentration arsenic ion implantation and heat treatment are performed under the same conditions as in the first embodiment, and the N ^-- type diffusion layer 121ba is replaced with the N ^-- type diffusion layer 121.
bb to form the N ⁺ type diffusion layer 125b [FIG.
(C)].

This embodiment has the effects of the first embodiment. Further, in this embodiment, the boundary between the N ⁺ type diffusion layer 125b and the N ⁻ type diffusion layer 121bb is formed in the vicinity of the boundary between the spacer 114 and the gate oxide film 112b by selecting the film thickness for forming the spacer 114. And the parasitic capacitance between the gate electrode 123b and the source / drain regions can be reduced more easily than in the first embodiment, and the MOS transistor according to the first embodiment has higher speed. A MOS transistor can be obtained.

Further, as an application example of the second embodiment,
After forming the gate electrode 125b, it is possible to form an insulating film on the entire surface and etch back this insulating film to form a second spacer, and then form an N ⁺ -type diffusion layer.
In this case, the degree of freedom in setting the profile of the N-type impurity in the vicinity of the drain end on the gate electrode side is higher than that in the second embodiment.

In the second embodiment, it is possible to provide a second groove having a width different from that of the groove 105b as in the first embodiment. The present embodiment can also be applied to P-channel type MOS transistors, CMOS transistors and the like.

6, 7 and 8 which are plan views of the manufacturing process of the semiconductor device and XX of FIG. 6, FIG. 7 or FIG.
9 which is a cross-sectional view taken along the line, and FIG. 1 which is a cross-sectional schematic view for explaining conditions for forming the N-type ion implantation region.
With reference to 0 together, the third embodiment of the present invention is
A MOS transistor having a gate electrode bent at 90 ° and a manufacturing method are as follows.

First, as in the first embodiment, (10
0) plane orientation and 5.0 × 10 ¹⁶ as a P-type impurity
A pad oxide film 102 and a field oxide film 103 having a film thickness of about 10 nm are formed in the element formation region and the element isolation region on the surface of the P-type silicon substrate 101 containing boron of cm ⁻³ . Next, a first predetermined film thickness H ₀ (eg 0.42
(μm) silicon nitride film 104 is formed on the entire surface. Next, the silicon nitride film 1 is anisotropically etched by using a first photoresist film pattern (not shown) as a mask.
04 is selectively etched to form a groove 105c. This groove 105c is formed on the groove side wall 15 parallel to the first direction.
5aa, 155ba and the groove side wall 15 parallel to the second direction
5ab and 155bb. The second direction is orthogonal to the first direction. Groove side wall 155aa and groove side wall 155a
b is directly orthogonal to the groove side wall 155ba and the groove side wall 155
It is directly orthogonal to bb. Groove 1 in the portion in the first direction
05c (the width between the groove sidewalls 155aa and 155ba) and the width of the groove 105c in the second direction (the groove sidewall 1
55ba and the distance between the groove side wall 155bb) are both a predetermined width L ₀ (for example, 0.6 μm) [FIG. 6 (a), FIG. 9].
(A)].

After the first photoresist film pattern is removed, a second photoresist film (not shown) is formed on the entire surface. The second photoresist film needs to completely fill the groove 105c and has a flat upper surface. This second photoresist film is patterned to form a second photoresist film pattern 131. The second photoresist film pattern 131 covers only the portion of the groove 105c in the second direction, and is not formed in the portion of the groove 105c only in the first direction. In the portion where the first direction and the second direction of the groove 105c intersect, on the second direction side of the line segment connecting the intersection of the groove sidewall 155aa and the groove sidewall 155ab and the intersection of the groove sidewall 155ba and the groove sidewall 155bb, Further, the second photoresist film pattern 131 is formed in the portion having the width ΔL ₁ from the groove side wall 155ba to the groove side wall 155aa (the reason will be described in the description of the next step) [FIG. 6 (b), Figure 9
(B)].

Next, the photoresist film pattern 13 is formed.
1 by ΔH ₀ by anisotropic etching with O ₂ plasma.
Of the second predetermined film thickness (H ₀ −Δ
It is converted into a photoresist film pattern 131a having H ₀ ). The anisotropic etching is plasma etching in which O ₂ gas is microwave-excited, and if it is left as isotropic etching, the P-type silicon substrate 10
The RF bias is applied to the No. 1 unit. If a few% of N ₂ gas is added to the etching gas, the side surface of the photoresist film pattern is protected by the film of the reaction product, and the etch back is further excellent in anisotropy. The photoresist film pattern 131a and the silicon nitride film 1
04 as a mask and groove side walls 155aa, 155ba
From the angle of θ (for example, 50 °)
KeV, 8.0 × 10 ¹³ cm ⁻² arsenic is ion-implanted. Thereby, the groove side wall 155aa and the groove side wall 155
including the vicinity of the intersection of ab and the vicinity of the intersection of the groove sidewall 155ba and the groove sidewall 155bb,
On the surface of the P-type silicon substrate 101 immediately below 155ba, an N-type ion implantation region 121ca is formed. At this time, ions are directly implanted without being masked by the silicon nitride film 104 or the photoresist film pattern 131a in the regions each having a width of ΔL ₁ (≈0.1 μm) from the end portions of the groove sidewalls 155aa and 155ba. here,
Between H ₀ , ΔH ₀ , L ₀ , ΔL ₀ , ΔL ₁ and θ, tan θ = ΔL ₁ / ΔH ₀ = (L ₀ − (ΔL ₀ + Δ
L ₁ )) / (H ₀ −ΔH ₀ ) [FIG.
(A), FIG. 9 (c), FIG. 10].

After removing the photoresist film pattern 131a, the portion of the groove 105c mainly in the first direction is formed into the second predetermined film thickness (H ₀ -ΔH ₀ ) by the same method as the photoresist film pattern 131a. A photoresist film pattern 132b to be embedded is formed. Then, using the photoresist film pattern 132b as a mask, the above-mentioned θ (≈) is applied to the groove sidewalls 155ab and 155bb.
50 °), 70 keV, 8.0 × 10 ¹³ cm
^-2 arsenic is ion-implanted. Thereby, the groove side wall 15
5aa and the vicinity of the intersection of the groove sidewall 155ab and the vicinity of the intersection of the groove sidewall 155ba and the groove sidewall 155bb, the N-type ion implantation region 121 is formed on the surface of the P-type silicon substrate 101 immediately below the groove sidewalls 155ab and 155bb.
cb is formed [FIG.7 (b), FIG.9 (d)].

After removing the photoresist film pattern 132b, the pad oxide film 102 on the bottom surface of the groove 105c is removed by etching in the same manner as in the first embodiment, and the gate oxide film having a film thickness of about 10 nm is thermally oxidized. 12
2c is formed, a gate electrode 123c having a shape of burying the trench 105c is formed, and a spacer 124c made of a silicon oxide film and having a width of about 0.1 μm is formed. Further, arsenic ion implantation is performed under the conditions of 70 keV, 3.0 × 10 ¹⁵ cm ^-2 , and 900 ° C., 10 ° C. in a nitrogen atmosphere.
Minute heat treatment is performed. By this series of processing, N
^{A +} type diffusion layer 125c and an N ⁻ type diffusion layer 121c are formed [FIGS. 8 and 9 (e)].

The third embodiment has the effects of the first embodiment. Also in this embodiment, similarly to the first embodiment, a groove having a width different from that of the groove 105c is formed in the groove 1.
It is also possible to form it simultaneously with 05c. Also, the second embodiment described above can be applied to this embodiment.
Although the groove of this embodiment has two directions orthogonal to each other, this embodiment is also applied to a MOS transistor having a gate electrode having four directions intersecting these two directions at 45 °. Is possible. At this time, the formation of the N-type ion implantation region may be performed four times (although it was twice in this embodiment). In addition, this embodiment also uses a P-channel MO.
It can be applied to the production of S-transistors and CMOS transistors.

[0044]

As described above, in the method of manufacturing a semiconductor device according to the present invention, a silicon nitride film is formed on the entire surface before forming the gate electrode, and a groove is formed in the gate electrode forming region of the silicon nitride film. Ion implantation is performed to form a low-concentration diffusion layer of opposite conductivity type at a predetermined angle with respect to the side wall of the groove. Therefore, immediately below the gate electrode, the distance between the reverse-conductivity-type low-concentration diffusion layer on the source side and the reverse-conductivity-type low-concentration diffusion layer on the drain side becomes minimum at the interface between the one-conductivity-type silicon substrate and the gate insulating film. , The deeper it gets wider.

As a result, a decrease in transconductance between the drain region and the source region is avoided. Further, the influence of the depletion layer generated by applying the voltage to the drain region on the depletion layer of the channel region generated by applying the voltage to the gate electrode is reduced, and the short channel effect is easily suppressed. Furthermore, since the position where the electric field strength is highest on the drain side is a position sufficiently distant from directly under the gate electrode, injection of hot carriers into the gate insulating film can be easily avoided.

[Brief description of drawings]

FIG. 1 is a plan view of a manufacturing process according to a first embodiment of the present invention.

FIG. 2 is a plan view of the manufacturing process of the first embodiment.

FIG. 3 is a cross-sectional view of the manufacturing process of the first embodiment,
It is sectional drawing in XX of FIG. 1 or FIG.

FIG. 4 is a diagram for explaining the effect of the first embodiment, and is a schematic sectional view of a main step and a diagram showing an arsenic concentration distribution in the vicinity of a drain end.

FIG. 5 is a cross-sectional view of the manufacturing process of the second embodiment of the present invention.

FIG. 6 is a plan view of the manufacturing process according to the third embodiment of the present invention.

FIG. 7 is a plan view of the manufacturing process of the third embodiment.

FIG. 8 is a plan view of the manufacturing process of the third embodiment.

FIG. 9 is a cross-sectional view of the manufacturing process of the third embodiment.

FIG. 10 is a schematic sectional view for explaining condition setting of the third embodiment.

FIG. 11 is a cross-sectional view of a manufacturing process of a conventional MOS transistor having a gate overlap LDD structure.

FIG. 12 is a diagram for explaining the problem of the conventional MOS transistor having the gate overlap LDD structure, and is a diagram showing the concentration distribution of arsenic near the drain end of this transistor.

[Explanation of symbols]

101, 201 P-type silicon substrate 102 Pad oxide film 103, 203 Field oxide film 104 Silicon nitride film 105aa, 105ab, 105b, 105c Grooves 111a, 131, 131a, 132b Photoresist film pattern 114, 124a, 124c, 224 Spacer 121a, 121b, 121ca, 121cb, 221
a N-type ion implantation region 121aa, 121ab, 121ba, 121bb, 1
21c, 221b N ⁻ type diffusion layers 122a to 122c, 222 Gate oxide film 123aa, 123ab, 123b, 123c, 223
Gate electrodes 125a to 125c, 225 N ⁺ type diffusion layers 155aa, 155ab, 155ba, 155bb
Groove sidewall

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication H01L 29/78 301 L

Claims (6)

[Claims] 1. A field oxide film and a pad oxide film are formed in an element isolation region and an element formation region on a surface of a one conductivity type silicon substrate, and a field oxide film and a pad oxide film each having a predetermined film thickness covering the surface of the field oxide film and the pad oxide film are formed. A step of forming a silicon nitride film on the surface of the silicon substrate, and a selective anisotropic etching of the silicon nitride film using the photoresist film pattern as a mask to cross the element formation region through the pad oxide film. And forming a groove having a predetermined width and having a desired length in a certain direction in the silicon nitride film, and from a direction orthogonal to the certain direction and forming a predetermined angle with respect to a sidewall of the groove. A step of ion-implanting a low-concentration opposite conductivity type impurity into the surface of the silicon substrate, removing the pad oxide film on the bottom surface of the groove, and forming a gate oxide film by thermal oxidation And a step of forming a gate electrode having a form of filling the trench, the silicon nitride film is selectively removed, an insulating film is formed on the entire surface, and the insulating film is etched back to form the gate electrode. A step of forming a spacer made of the insulating film on the side surface of the substrate, and a step of ion-implanting a high concentration of a reverse conductivity type impurity into the element forming region using the field oxide film, the spacer and the gate electrode as a mask. And a method for manufacturing a semiconductor device. 2. A second groove having a width different from the predetermined width is formed together with the groove, and the second groove is covered with a second photoresist film pattern to have the low-concentration reverse conductivity type. 2. The method for manufacturing a semiconductor device according to claim 1, further comprising ion-implanting impurities into the surface of the silicon substrate and removing the second photoresist film pattern. 3. A field oxide film and a pad oxide film are formed in an element isolation region and an element formation region on a surface of a one conductivity type silicon substrate, and a field oxide film and a pad oxide film having a predetermined film thickness are formed to cover the surface of the field oxide film and the pad oxide film. A step of forming a silicon nitride film on the surface of the silicon substrate, and a selective anisotropic etching of the silicon nitride film using the photoresist film pattern as a mask to cross the element formation region through the pad oxide film. And forming a groove having a predetermined width and having a desired length in a certain direction in the silicon nitride film, and from a direction orthogonal to the certain direction and forming a predetermined angle with respect to a sidewall of the groove. A step of ion-implanting a low-concentration opposite conductivity type impurity into the surface of the silicon substrate, forming a silicon oxide film on the entire surface, and etching back the silicon oxide film Forming a spacer made of the silicon oxide film on the side wall of the silicon oxide film, forming a gate oxide film by thermal oxidation, forming a gate electrode having a form of filling the groove, and selectively forming the silicon nitride film. A method of manufacturing a semiconductor device, comprising: a step of removing; and a step of ion-implanting a high concentration of a reverse conductivity type impurity into the element forming region using the field oxide film, the spacer and the gate electrode as a mask. 4. The insulating film is formed on the entire surface after the silicon nitride film is selectively removed, and the insulating film is etched back to form a second spacer made of the insulating film on the side surface of the gate electrode. 4. The method according to claim 3, further comprising:
The manufacturing method of the semiconductor device described in the above. 5. A first predetermined film is formed by forming a field oxide film and a pad oxide film on an element isolation region and an element formation region on a surface of a one conductivity type silicon substrate, and covering the surface of the field oxide film and the pad oxide film. A step of forming a silicon nitride film having a film thickness on the surface of the silicon substrate, and a selective anisotropic etching for the silicon nitride film using the first photoresist film pattern made of the first photoresist film as a mask, A groove is formed in the silicon nitride film across the element formation region via the pad oxide film and having a predetermined width and being bent in the first direction and the second direction. And the step of forming a second photoresist film having a required film thickness on the entire surface,
A second photoresist film pattern having an opening is formed in at least the portion of the groove having the first direction, and the second photoresist film pattern is formed until the second predetermined film thickness is smaller than the first predetermined film thickness. A step of selectively etching back the second photoresist film pattern by anisotropic etching; and forming a predetermined angle with respect to a sidewall of the groove in a portion which is orthogonal to the first direction and has the first direction. Direction, a low concentration impurity of opposite conductivity type is ion-implanted into the surface of the silicon substrate to remove the second photoresist film pattern, and a third photoresist film having a desired film thickness is formed on the entire surface. ,
A third photoresist film pattern having an opening is formed in at least the portion of the groove having the second direction, and the third photoresist film pattern is formed to a second predetermined film thickness smaller than the first predetermined film thickness. 3 is a step of selectively etching back the photoresist film pattern by anisotropic etching; and a step of forming the predetermined angle with respect to a side wall of the groove which is orthogonal to the second direction and has the second direction. A step of ion-implanting a low-concentration impurity of opposite conductivity type into the surface of the silicon substrate from the direction of forming the third photoresist film pattern, and removing the pad oxide film on the bottom surface of the groove by thermal oxidation. To form a gate oxide film, a step of forming a gate electrode having a form of filling the trench, the silicon nitride film is selectively removed, an insulating film is formed on the entire surface, and the insulating film is etched. Backing up to form a spacer made of the insulating film on the side surface of the gate electrode, and ion-implanting a high-concentration impurity of the opposite conductivity type into the element formation region using the field oxide film, the spacer and the gate electrode as a mask. A method of manufacturing a semiconductor device, comprising: 6. The etching back for the second and third photoresist film patterns is performed by microwave-excited plasma etching in which an RF bias is applied to the silicon substrate and a gas containing at least oxygen gas is used as an etching gas. The method for manufacturing a semiconductor device according to claim 5, wherein