JPH0897275A - Semiconductor device - Google Patents

Abstract

PURPOSE: To obtain microscopic electrodes, which do never inflict a variation on the performance characteristics of an element, by a method wherein grooves provided in an insulating film formed on the surface of a semiconductor substrate are filled with a semiconductor film to form element regions and at the same time, element isolation regions are respectively formed between element operating regions adjacent to each other in a self-alignment manner. CONSTITUTION: In a NAND EEPROM, a plurality of control gates 2 and a plurality of active layers 6 are arranged in such a way as to intersect orthogonally each other and floating gates 4 are provided on the intersection parts of both of the gates 2 and the layers 6 in a form that the gates 4 are held between the gates 2 and the layers 6 via a tunnel oxide film 5 and an ONO film 3 to form a storage node at each intersection part. Element regions are formed by depositing a polycrystalline silicon film, for example, in grooves provided in an insulating film formed on the surfaces of semiconductor electrodes and floating gate electrodes are respectively formed on element isolation regions adjacent to each other in a self-alignment manner. Thereby, a cell structure, which is formed very microscopically and isolatedly, can be obtained and at the same time, a variation of the performance characteristics of an element can be also eliminated completely without generating a variation of the form of the element due to a misalignment or the like.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device,
In particular, it relates to a semiconductor device in which electrodes such as a charge storage layer and a gate electrode are formed in a self-aligned manner with respect to an element isolation region having a trench structure.

[0002]

2. Description of the Related Art In recent years, semiconductor devices have been highly integrated, and fine semiconductor memory devices have been actively researched.
Among various semiconductor memory devices, for example, a non-volatile memory element is expected as a substitute for a hard disk device,
Higher integration is desired. As shown in FIG. 12, this non-volatile memory element has a special structure including a floating gate 4 as a charge storage layer, which is not found in other semiconductor memory devices. The technique of forming the operating region and the floating gate 4 finely is one of the important factors.

Here, a trench is formed in the well 7 formed on or in the silicon substrate,
When a fine element isolation region is formed by filling this groove with an insulating film 13 such as CVD SiO2, a void is generated in the embedded insulating film 13 or the film quality of the insulating film is locally deteriorated. In this case, the buried flatness is lowered, or the floating gates 4 or select gate electrodes (not shown) for selecting a memory cell are short-circuited, which causes an abnormal operation of the device.

In order to avoid these problems, the element isolation region must be enlarged, which is a major factor in hindering the miniaturization of cells and, consequently, the high integration of elements. still,
In the figure, 5 is a tunnel oxide film, 3 is an ONO film, 2 is a control gate, and 1 is an interlayer insulating film.

[0005]

As described above, in the conventional non-volatile memory device, it is extremely difficult to separately form the device operation region by the method of forming the groove in the substrate and filling the substrate with the insulating material. . Further, since the buried insulating film 13 has poor flatness, a short circuit between the floating gates 4 may occur, for example. Further, impurities from the buried insulating film 13 may affect the tunnel oxide film 5 and the gate oxide film 3.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor device having finely separated electrodes which does not change the element operation characteristics.

[0007]

A means for solving the problems in the present invention is to perform self-alignment between an element region formed by filling a groove provided in an insulating film formed on the surface of a semiconductor substrate with a semiconductor film and an adjacent element operation region. And an element isolation region formed in a specific manner.

Further, preferably, the element region may be formed by filling a groove provided in at least two kinds of insulators which can be selectively etched with each other with a semiconductor film.

Preferably, the groove may be formed with a taper angle to form an element operating region finer than the design rule so that a high coupling constant can be realized.

[0010]

According to the present invention (claim 1 or 4), since the element operating region is formed in a self-aligned manner between the adjacent element isolation regions, an extremely finely separated electrode can be obtained, and It is possible to eliminate the problem of flatness, which has been a problem in the past when a groove provided on a semiconductor substrate is filled with an insulator. Further, it is possible to eliminate the fluctuation of the operating characteristics, which is a conventional problem, without causing the fluctuation of the element shape due to the misalignment at the time of photolithography.

[0011]

FIG. 1 shows a NAND type E according to an embodiment of the present invention.
A top view of an EPROM is shown. Further, FIGS. 2 and 3 show an AA ′ sectional view and a BB ′ sectional view of the NAND type EEPROM of FIG. 1, respectively.

This NAND type EEP as shown in FIGS.
In the ROM, a plurality of control gates 2 and a plurality of active layers 6 are arranged orthogonally, and a tunnel oxide film 5 is formed at the intersection of the two.
The floating gate 4 is provided so as to be sandwiched by the ONO film 3 and the ONO film 3, and each intersection forms a storage node.

The element region is formed by depositing, for example, polycrystalline silicon in a groove provided in an insulating film formed on the surface of a semiconductor substrate, and a floating gate electrode is formed in an adjacent element isolation region in a self-aligned manner. ing.

In this embodiment, since the element region and the floating gate electrode are formed in a self-aligned manner between the adjacent element isolation regions, an extremely finely divided cell structure can be obtained, which is a conventional problem. It is possible to completely eliminate the variation of the operating characteristics without causing the variation of the element shape due to the misalignment at the time of photo-etching.

In this embodiment, as shown in FIG. 3, by utilizing the side wall of the floating gate electrode, it is possible to provide a large capacitance with the control gate. The manufacturing process for obtaining the EEPROM having the structure shown in FIG. 3 will be described below. First, for example, a P-type well is formed on an N-type silicon substrate having a plane orientation (100) and a specific resistance of 5 to 50 Ω-cm.
C., LOCOS oxidation or Box oxidation to form a film thickness of about 5000 angstrom. At this time, peripheral element isolation is also performed at the same time (FIG. 4A). Thereafter, for example, a silicon nitride film 10 is deposited to a thickness of 2000 angstrom as a mask layer. (FIG.4 (b)). Since the film thickness of the mask layer 10 is related to the film thickness of the control gate, that is, the side wall length,
It should be determined for the desired programming voltage.

Further, the resist film 1 is formed by photolithography.
1 is selectively covered, and the silicon nitride film 10 is etched by RIE using this as a mask (FIG. 4C). Further, the field oxide film 8 is etched by RIE (FIG. 4).
(D)). At this time, it is important to etch the silicon substrate by RIE.

Then, a polysilicon film 6 doped with boron as a semiconductor film is deposited, for example, in the thickness of 3000 angstrom to fill the groove (FIG. 4 (e)). After that, the boron-doped polysilicon film 6 is etched back. At this time, it is important that the etching surface of the boron-doped polysilicon film 6 is below the interface between the field oxide film 8 and the silicon nitride film 10. After this, a thermal oxidation step or CVD
S _i O ₂ film tunnel oxide film 5 is formed on the boron-doped polysilicon film 6 by depositing (FIG. 5
(A)), and a polysilicon film 4 is further deposited (see FIG. 5).
(B)) For example, after phosphorus is diffused, etching back is performed by RIE (FIG. 5C). At this time, it is desirable that the etching surface of the polysilicon film 4 be substantially equal to the surface of the silicon nitride film 10. This is because the sidewall of the polysilicon film 4 also serves as chapatacitor, which improves the coupling constant.

Thereafter, the silicon nitride film 10 is formed on the CD, for example.
It is peeled off by etching back the entire surface with E, and then O
The NO film 3 is formed on the entire surface (FIG. 5D). Further, the ONO film 3 is selectively covered with a resist film by, for example, photolithography, and the ONO film 3 is removed only by the peripheral portion by, for example, RIE. After that, the buffer oxide film in the peripheral element portion is removed with, for example, ammonium fluoride, and then the resist film is peeled off to form a gate oxide film of the peripheral transistor. Next, after depositing the polysilicon film 2 and performing phosphorus diffusion, the polysilicon film 2 is selectively covered with a resist film by photolithography or the like, and, for example, by RIE or the like.
The gate electrode portion 2 of the peripheral transistor and the control electrode 2 of the cell portion are formed at the same time (FIG. 5E). From the above,
The above-described excellent effects of the embodiment of the present invention can be obtained. A second embodiment of the present invention will be described with reference to FIGS.

After forming the field oxide film 8 on the substrate 20, for example, a silicon nitride film 10 is deposited as a mask layer and selectively covered with a resist film by photolithography (FIG. 6).
(A)) Using the resist film as a mask, the mask layer, here the silicon nitride film 10 is etched by, for example, RIE (FIG. 6B). Further, after removing the resist film, the field oxide film 8 is etched by, for example, RIE using the silicon nitride film 10 as a mask as a mask to remove the silicon nitride film 10 (FIG. 6C). Here, it is important that the etching shape of the field oxide film 8 has a sufficient taper angle, for example, an angle of about 100 degrees to about 80 degrees, and in this embodiment, it is set to about 80 degrees.

After that, a boron-doped polysilicon film 6 is deposited, and after filling the groove (FIG. 6 (d)), the boron-doped polysilicon film 6 is etched back by, for example, RIE. At this time, the boron-doped polysilicon film 6
It is important that the above etching is sufficiently overetched. (FIG. 7 (a)). Here, the tunnel oxide film 5
Is formed by thermal oxidation or CVDS _i O ₂ film deposition (FIG. 7B), then a polysilicon film is deposited to form the floating gate 4 and phosphorus is diffused (FIG. 7C). After that, etch back is performed by, for example, RIE. At this time, it is important that the etching surface of the polysilicon film 4 is below the surface of the field oxide film 8. However, if overetching is excessively performed, the capacitance of the control gate capacitor becomes small and the coupling constant decreases. Therefore, it is important that the etching surface of the polysilicon film 4 is slightly below the surface of the field oxide film 8 (FIG. 7D). After that, the ONO film 3 is formed. After that, the process is the same as that of the first embodiment, and finally the gate electrode 2 of the peripheral transistor and the control electrode 2 of the cell portion are simultaneously formed (FIG. 8). According to the second embodiment formed in this way, the same effect as that of the first embodiment can be obtained.

Next, a third embodiment of the present invention will be described with reference to FIG. Here, in the manufacturing method according to the second embodiment, instead of forming the element region by depositing the boron-doped polysilicon film 6 and then etching back, in the third embodiment, selective growth is performed by epitaxial growth. A silicon epitaxial film 12 is selectively grown from the exposed silicon substrate to form an element region. At this time, the angle (taper angle) of the side wall of the trench may be vertical or around 80 degrees. Also in this example,
Similar to the second embodiment, it is desirable that the angle is about 80 to 100 degrees. As an example thereof, the third embodiment shows a process sectional view relating to the case where a taper angle is provided. After this,
For example, by thermal oxidation or CVDS _i O ₂ film deposited to form a tunnel oxide film 5 (FIG. 9 (a)), depositing a polysilicon film 4 then serving as a floating gate, and phosphorus diffusion, then etched back (FIG.9 (b)). At this time, the etching surface of the polysilicon film 4 is etched back until it is below the surface of the field oxide film 8 so that adjacent floating gates 4 are not short-circuited. Although etching back is used here, patterning may be performed with a resist as usual.

Next, an ONO film 3 is formed and a polysilicon film is further deposited to form a control gate 2. Furthermore, as the manufacturing method according to the fourth embodiment of the present invention, after etching the silicon nitride film by, for example, RIE,
The resist is removed, and a groove is formed in the field oxide film by, for example, RIE using the silicon nitride film as a mask. It is important that this groove also has a taper angle as in the second and third embodiments (for example, around 80 degrees).

After that, the trenches are filled with the boron-doped polysilicon film 6 and etched back. At this time, it is important that the etching surface of the polysilicon film 6 is sufficiently over-etched so that it is located under the trench. Further, the tunnel oxide film 5 is formed by thermal oxidation or CVD (FIG. 10A). After that, a polysilicon film 4 is deposited to fill the groove (FIG. 10B), and then phosphorus is diffused into the polysilicon film 4 and etched back. At this time, it is important that the etching surface of the polysilicon film 4 is slightly below the upper end portion of the silicon nitride film 10 (FIG. 10).
(C)).

Next, the silicon nitride film 10 is treated with, for example, C
It is removed by DE or the like (FIG. 11A), an ONO film is formed, and a control gate is formed (FIG. 11B). The same effects as those of the first embodiment can be obtained by the third and fourth embodiments thus formed. Further, the present invention is not limited to the above embodiment, but can be applied to a normal MOSFET having no floating gate.

[0025]

According to the present invention, the problem of flatness that occurs when an insulator is embedded in a groove formed in a semiconductor substrate can be completely solved, and the element shape can be changed due to misalignment during photolithography. It is possible to completely eliminate fluctuations in operating characteristics without causing

[Brief description of drawings]

FIG. 1 is a plan view of an EEPROM according to a first embodiment of the present invention.

FIG. 2 is a sectional view taken along the line AA ′ of the EEPROM according to the embodiment.

FIG. 3 is a sectional view taken along the line BB ′ of the EEPROM according to the embodiment.

FIG. 4 is a process sectional view showing a manufacturing process of the EEPROM according to the embodiment.

FIG. 5 is a process sectional view showing a sequel to FIG. 4;

FIG. 6 is a process sectional view showing a second embodiment of the present invention.

FIG. 7 is a process sectional view subsequent to FIG. 6;

FIG. 8 is a process sectional view subsequent to FIG. 7;

FIG. 9 is a process sectional view showing a third embodiment of the present invention.

FIG. 10 is a process sectional view showing a fourth embodiment of the present invention.

FIG. 11 is a process sectional view subsequent to FIG. 10;

FIG. 12 is a sectional view of an EEPROM according to a conventional example.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Interlayer insulating film 2 ... Control gate 3 ... ONO film 4 ... Floating gate 5 ... Tunnel oxide film 6 ... Boron doped polysilicon film 7 ... P-Well 8 ... Field oxide film 9 ... Buffer oxide film 10 ... Silicon nitride film 11 ... Resist film 12 ... Silicon epi film 13 ... Embedded CVDS _i O ₂ 14 ... Substrate

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Claims (5)

[Claims] 1. A plurality of element regions formed by filling a groove formed in an insulating film formed on a surface of a semiconductor substrate with a semiconductor film and an element isolation region separating adjacent element regions by the insulating film. A semiconductor device characterized by the above. 2. The semiconductor device according to claim 1, wherein the element isolation region is formed of at least two kinds of insulating films. 3. The semiconductor device according to claim 1, wherein the groove is formed with an angle of 100 degrees to 80 degrees on the side wall thereof. 4. A plurality of memory cells in which a charge storage layer and a control gate are laminated are arranged on a semiconductor substrate, and a groove provided in an insulating film formed on the surface of the semiconductor substrate is provided with a conductive layer. A semiconductor device comprising: an element region formed by embedding a film; and an element isolation region separating an adjacent element region with the insulating film. 5. The semiconductor device according to claim 4, wherein the charge storage layer has a control gate electrode formed on at least a side surface thereof with an insulating film interposed therebetween.