JPH0896596A - Semiconductor storage device, its testing method and its testing device - Google Patents

Abstract

PURPOSE: To improve efficiency of the testing and to simplify constitution of a testing device by discriminating the test operating mode with a signal from the testing device, supplying input data to plural memory blocks and outputting discriminated results. CONSTITUTION: A self-testing circuit 100 is provided in the semiconductor storage device of multibit-constitution having plural memory blocks M1 to Mn . When a voltage higher than that at the time of a normal use is applied from the testing device to an p external terminal DQ2, a mode discriminating part 11 transmits the discrimination signal S11 of the test operating mode to a control part 12= Thc control part 12 outputs a mode changeover signal S12 and then a data distributing part 13 supplies testing data DIN inputted from the testing device to the external terminal DQ1 to plural memory blocks M1 to Mn on parallel by receiving the signal S12. A data discriminating part 14 inspects readout data from the memory blocks M1 to Mn and outputs discriminated results DOUT from the external terminal DQ1 to the testing device via a data changeover part 15 as a serial data string.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, a test method therefor, and a test device therefor. It relates to the improvement of the test function. 2. Description of the Related Art In recent years, as information processing apparatuses have become more sophisticated and have more functions, the applications of semiconductor memories have expanded more and more, and along with the diversification and increase in capacity, there is a tendency for semiconductor memories having a multi-bit configuration.

Along with this, the number of input / output terminals of the memory has been increasing, and a method such as multiplexing of address input or commonization of input / output is adopted to suppress the increase of the number of input / output terminals. . Further, it is possible to suppress the increase in the external dimensions and the number of mounting wirings at the time of mounting, and reduce the number of drivers and comparators in the test apparatus. However, the change in the bit configuration of the memory has doubled like 4, 8, 16 ... 2 ⁿ , and naturally the number of input / output terminals of the memory has also doubled. In order to confirm the operation of the memory having such a multi-bit structure, the test device naturally requires the number of comparators corresponding to the bit structure.

Therefore, by devising the input / output data transmission / reception function and the self-test function during the memory test, it is possible to efficiently test a memory cell having a multi-bit structure and to reduce the test cost. A memory, method and apparatus is desired.

[0004]

2. Description of the Related Art FIGS. 8 and 9 are explanatory views according to a conventional example. FIG. 8 is a configuration diagram of a multi-bit memory according to a conventional example, and FIG. 9 is a connection diagram of a semiconductor memory and a test device at the time of the test. For example, an 8-bit semiconductor memory having a test switching function includes a mode determination unit 1, a control unit 2 and a selector 3, as shown in FIG.
8 input buffers 4, 8 output buffers 5, 8
It consists of one memory cell block M1 to M8.

The function of the semiconductor memory during normal operation is
The mode determination unit 1 becomes inoperative, and the control unit 2 supplies the selector 3, for example, with a mode signal Sm = “L” level. As a result, the selector 3 has the I / O gates of the memory cell blocks M1 to M8 and the external terminals DQ1 to DQ8.
The input buffer 4 and the output buffer 5 are connected to each other. As a result, 8-bit data is asserted according to the write or read operation.

As for the function of the semiconductor memory in the test operation, first, as shown in FIG. 9, the semiconductor memory 6 and the test apparatus 7 are connected, and the external terminal DQ2 is connected to the test apparatus as shown in FIG. A voltage VHH higher than the voltage during normal use is applied by the output driver 9 of 7. As a result, the mode determination unit 1 inside the memory as shown in FIG. 8 determines the test operation mode, and the determination signal is transferred to the control unit 2. In the controller 2, the mode signal Sm = based on the determination signal
The “H” level is supplied to the selector 3.

Here, the eight memory cell blocks M1 to M1
When M8 is tested half by half, for example, the selector 3
Connects the I / O gates of the memory cell blocks M1 to M4 in the first half to the input buffer 4 and the output buffer 5 of each of the four external terminals DQ3 to DQ6. As a result, 4-bit input / output data of the memory cell blocks M1 to M4 is asserted according to the write or read operation during the test. Specifically, the input data D is input by the four input / output drivers 8 of the test apparatus 7 as shown in FIG.
IN or output data DOUT is transmitted and received.

Similarly, the selector 3 includes the I / O gates of the latter half memory cell blocks M5 to M8 and four external terminals D.
The input buffer 4 and the output buffer 5 of Q3 to DQ6 are connected to each other. As a result, 4-bit input / output data of the memory cell blocks M5 to M8 is asserted according to the write or read operation during the test, and the read data from the eight memory cell blocks M1 to M8 is compared and judged in the test device. The memory is tested, for example, by comparison with expected value data.

[0009]

By the way, according to the conventional multi-bit semiconductor memory having the test switching function, the I / O gates of the memory cell blocks M1 to M8 are divided by half based on the test operation mode. Is provided to connect the four external terminals DQ3 to DQ6, respectively.

Therefore, the memory cell blocks M1 to M4 are
Alternatively, the writing or reading test can be performed by the test device 7 based on the 4-bit input / output data of M5 to M8. However, the read data DOU for the input data DIN
The process of determining whether T matches or does not match depends on the data comparison and determination unit provided inside the test apparatus. As a result, as the number of bits of the semiconductor memory 6 increases and the number of external terminals increases, the load on the data comparison / determination unit of the test apparatus 7 increases more and more.

According to the conventional method for testing a semiconductor memory having a multi-bit configuration, a high voltage is applied to a certain external terminal DQ2 to identify the test operation mode, and four external terminals DQ3 to DQ6 are used. Memory cell blocks M1 to
Input / output data DIN / DOUT for each half of M8 is transmitted / received to / from the test apparatus 7. Therefore, in order to confirm the operation of all the memory cells in the test apparatus 7, it is necessary to provide at least a 4-bit input / output driver 8 and a comparator. As a result, when the number of bits of the semiconductor memory 6 is increased and the number of external terminals is increased, if the number of drivers / comparators of the existing test device 7 is smaller than the number of bits of the semiconductor memory 6, the test is no longer performed. Can not be.

Even when the number of drivers / comparators of the test apparatus 7 is sufficient for the test of a single memory, when a high speed test is required to measure two or more semiconductor memories 6 simultaneously, Requires a large increase in the number of drivers / comparators of the test apparatus 7. As a result, the test apparatus becomes expensive and the test cost performance becomes poor.

The present invention has been made in view of the problems of the conventional example, and devises the input / output data transmission / reception function and the self-test function at the time of the memory test to efficiently make a memory cell having a multi-bit structure. An object of the present invention is to provide a semiconductor memory device, a test method therefor, and a test device capable of performing a test and reducing the test cost.

[0014]

1 and 2 show principle diagrams (Nos. 1 and 2) of a semiconductor memory device according to the present invention. As shown in FIG. 1, a first semiconductor memory device of the present invention is a semiconductor memory device having a multi-bit structure having a plurality of memory cell blocks, which indicates a normal operation mode or a test operation mode from input information of a first external terminal. When the determination is made and the test operation mode is determined, the input data from the second external terminal is supplied in parallel to the plurality of memory cell blocks,
A self-test circuit 100 for judging read data from the plurality of memory cell blocks and outputting the judgment result data of the serial column to the outside through the second external terminal.

In the first semiconductor memory device of the present invention,
As shown in FIG. 1, the self-test circuit 100 includes a mode determination unit 11 that detects input information from a first external terminal to determine a normal operation or test operation mode, and a determination from the mode determination unit 11. Mode switching signal S based on signal S11
12, and a data distribution unit for supplying input data DIN from a second external terminal to the plurality of memory cell blocks M1 to Mn in parallel in response to a mode switching signal S12 from the control unit 12. 13 and read data D1 to D from the plurality of memory cell blocks M1 to Mn
A data judging section 14 for judging n and outputting the judgment result data DOUT of the serial string, and the judgment result data DOUT from the data judging section 14 through the second external terminal in response to the mode switching signal S12. Output data switching unit 1
5 and.

As shown in FIG. 2, the second semiconductor memory device of the present invention is a semiconductor memory device having a multi-bit structure having a plurality of memory cell blocks, and a normal operation from the input information of the first external terminal or The test operation mode is determined, and when the test operation mode is determined, the input data from the second external terminal is supplied to the plurality of memory cell blocks in parallel or serially, and any one of the plurality of memory cell blocks is supplied. The self-test circuit 200 outputs the read data or the determination result data of the serial column that determines the read data from the plurality of memory cell blocks to the outside through the second external terminal.

In the second semiconductor memory device of the present invention,
As shown in FIG. 2, the self-test circuit 200 detects the input information from the first external terminal to determine a normal operation or test operation mode, a second external terminal and the first external terminal and the first external terminal. And a determination signal from the mode determination unit 21 and a decoding unit 22 that decodes input information from other than the external terminal and outputs a block selection signal S22 that selects one of the plurality of memory cell blocks M1 to Mn. S21
And a control section 23 for generating an input / output control signal S23 based on the block selection signal S22 from the decoding section 22, and input data DIN from a second external terminal in response to the input / output control signal S23 from the control section 23. And a data distribution unit 24 that supplies the plurality of memory cell blocks M1 to Mn in parallel or serially, and the plurality of memory cell blocks M1.
Read data Di from any of the memory cell blocks M1 to Mn.
Judgment result data DOUT of the serial string for judging 1 to Dn
Is output via the second external terminal in response to the input / output control signal S23.

A first test method for a semiconductor memory device according to the present invention is a test method for a semiconductor memory device having a plurality of memory cell blocks and having a self-test function, wherein the first external terminal of the semiconductor memory device is Input information for identifying a test operation mode is supplied, a test signal is supplied via a second external terminal of the semiconductor memory device that has shifted to the test operation mode, and a test result signal from the semiconductor memory device is supplied to the second external terminal.
It is characterized in that it is taken into the test device through the external terminal of.

A second test method for a semiconductor memory device according to the present invention is the same as the first test method, except that the test result signal from the semiconductor memory device is input to the test device by using a second external terminal. It is characterized in that selection data for selecting any one of the plurality of memory cell blocks is supplied to vacant external terminals other than the first external terminal and the second external terminal.

According to another aspect of the present invention, there is provided a semiconductor memory device testing apparatus which is a semiconductor memory device testing device having a self-test function, wherein input information for identifying a test operation mode at a first external terminal of each of the plurality of semiconductor memory devices. Supply each,
A test signal is supplied via each second external terminal of the semiconductor memory device that has shifted to the test operation mode, and each test result signal from the semiconductor memory device is supplied to the second external terminal.
In order to achieve the above-mentioned object, it is characterized in that each of the semiconductor memory devices is taken in through the external terminals of (1) and simultaneously tested for a plurality of semiconductor memory devices.

[0021]

[Operation] Next, the operation of the first semiconductor memory device of the present invention will be described with reference to FIG. For example, a self-test circuit
The normal operation or the test operation mode is determined from the input information of the first external terminal by 100, and when it is determined to be the “test operation mode”, the input data from the second external terminal is changed to the self-test circuit 100. To a plurality of memory cell blocks.

That is, in FIG. 1, the input information from the first external terminal is the mode determination unit 1 of the self-test circuit 100.
When it is detected by 1 and whether the normal operation mode or the test operation mode is determined, the control unit 12 generates the mode switching signal S12 based on the determination signal S11 from the mode determination unit 11. As a result, the data distribution unit 13 supplies the input data DIN from the second external terminal in parallel to the plurality of memory cell blocks M1 to Mn in response to the mode switching signal S12 from the control unit 12.

The read data from each memory cell block is judged by the self-test circuit 100, and the judgment result data DOUT at this time is output to the outside through the second external terminal. For example, a plurality of memory cell blocks M1 to M
The read data D1 to Dn from the data n
The determination result data DOUT of the serial string at this time is output to the data switching unit 15. The determination result data DOUT from the data determination unit 14 is the mode switching signal S
The data is output from the data switching unit 15 to the test device via the second external terminal in accordance with 12 (first test method).

Therefore, it is possible to receive the input data at the time of the memory test from the test apparatus by using the second external terminal and to send the judgment result data to the test apparatus by using the same external terminal. It will be possible. Also, unlike the conventional example, each memory cell block M for the input data DIN
Matching / mismatching of read data D1 to Dn from 1 to Mn can be self-determined inside the semiconductor memory device.
That is, the determination result data DOUT of the write or read test based on the n-bit input / output data is transferred to the test apparatus via the second external terminal and depends on the data comparison / determination unit inside the test apparatus as in the conventional example. Will not do.

As a result, even if the number of bits of the semiconductor memory device is increased and the number of external terminals is increased, it is possible to suppress an increase in the number of data comparison / determination units and the number of drivers / comparators in the test apparatus. Further, it is possible to efficiently test a memory cell block having a multi-bit structure and to reduce the test cost. Next, the operation of the second semiconductor memory device of the present invention will be described with reference to FIG. For example, the self-test circuit 200 determines the normal operation or the test operation mode from the input information of the first external terminal, and when it is determined to be the "test operation mode", the input data from the second external terminal is input. Are supplied from the self-test circuit 200 to a plurality of memory cell blocks in parallel or serially.

That is, as shown in FIG. 2, the input information from the first external terminal is detected by the mode determining section 21 of the self-test circuit 200, which is determined to be the "test operation mode". When the block selection signal S22 obtained by decoding the input information from other than the second external terminal and the first external terminal is output from the decoding unit 22 to the control unit 23, the determination signal S21 from the mode determination unit 21 and the decoding unit 22 The control section 23 generates an input / output control signal S23 based on the block selection signal S22.

As a result, in the data distribution unit 24, the input data DIN from the second external terminal is supplied to the plurality of memory cell blocks M1 in response to the input / output control signal S23 from the control unit 23.
To Mn in parallel or serially. Further, any read data from the plurality of memory cell blocks or the determination result data obtained by determining the read data from this memory cell block is output to the external test apparatus via the second external terminal.

At this time, a plurality of memory cell blocks M1
~ Mn read data Di directly, or the serial column judgment result data DOUT for judging the read data D1 to Dn from a plurality of memory cell blocks M1 to Mn, according to the input / output control signal S23. It is output from the data determination output unit 25 via the second external terminal (second
Test method).

Therefore, the input data at the time of the memory test is the second
It is possible to receive from the test apparatus using the external terminal of 1 and to send the judgment result data or read data directly to the test apparatus using the same external terminal. Further, unlike the first semiconductor memory device, the read data from each memory cell block can be transferred to the test device as it is, and there are two types of operation confirmation of all memory cells and operation confirmation of a specific memory cell block. It becomes possible to carry out the test.

As a result, even when the number of bits of the semiconductor memory device is increased and the number of external terminals is increased, it is possible to suppress an increase in the number of data comparison / determination units and the number of drivers / comparators in the test apparatus. Further, it is possible to efficiently test a memory cell block having a multi-bit structure and to reduce the test cost. The operation of the semiconductor memory device testing apparatus of the present invention will be described. For example, when the input information is respectively supplied to the first external terminals of each of the plurality of semiconductor memory devices, the test signals are respectively supplied through the second external terminals of each semiconductor memory device that has shifted to the test operation mode. Then, the respective test result signals from the respective semiconductor memory devices are taken into the respective test devices via the second external terminals.

Therefore, it is possible to confirm the operation of all the memory cells of one semiconductor memory device by the input / output driver and the comparator for 1 bit. As a result, even when the number of bits of the semiconductor memory device is increased and the number of external terminals is increased, the semiconductor memory device can be simultaneously tested by the number of existing drivers / comparators.

As a result, it becomes possible to sufficiently meet the demand for speeding up the test such that two or more semiconductor memory devices are simultaneously measured. Further, it is possible to simplify the test apparatus, reduce the cost, and improve the test cost performance.

[0033]

Embodiments of the present invention will now be described with reference to the drawings. 3 to 7 are views for explaining a semiconductor memory device, a test method therefor, and a test apparatus therefor according to an embodiment of the present invention. (1) Description of First Embodiment FIG. 3 is a configuration diagram of a multi-bit memory with a self-test function according to the first embodiment of the present invention, and FIG. 4 is a diagram showing a connection between the multi-bit memory and a test apparatus. It is a figure. FIG. 5 is an equivalent circuit diagram during the memory test, and FIG. 6 shows an equivalent circuit diagram during the normal operation.

For example, a semiconductor memory having an 8-bit structure with a self-test function has a self-test circuit 100, as shown in FIG.
The memory cell block includes eight memory cell blocks M1 to M8, seven input / output data switching units 16, eight input buffers 17 and eight output buffers 18. The self-test circuit 100 includes a mode determination unit 11, a control unit 12, a data distribution unit 13, a data determination unit 14, and a data switching unit 15 in FIG.

The mode determination unit 11 is a circuit that detects the input information from the external terminal DQ2 to determine the normal operation or test operation mode and outputs the determination signal S11 to the control unit 12. A voltage higher than the voltage during normal operation is used as the input information. The control unit 12 is a circuit that generates a mode switching signal S12 based on the determination signal S11 from the mode determination unit 11. The signal S12 is output to the data distribution unit 13, the data determination unit 14, the data switching unit 15, and the input / output data switching unit 16.

The data distribution unit 13 is a circuit for supplying the input data DIN from the external terminal DQ1 to the eight memory cell blocks M1 to M8 in parallel in response to the mode switching signal S12 from the control unit 12. For example, the data distribution unit 13
Is composed of two circuits and one selection switch element, the middle point of which is connected to the external terminal DQ1 via the input buffer 17, the point a is connected to the normal input of the I / O gate of the memory cell block MI, and the point b is Each is connected to the test input of the I / O gate.

The data judging section 14 is a circuit for judging the read data D1 to D8 from the eight memory cell blocks M1 to M8 and outputting the judgment result data DOUT of the serial column to the data switching section 15. The determination condition at this time is to find out whether the read data D1 to D8 match or do not match the input data DIN. The data switching unit 15 outputs the determination result data DOUT from the data determination unit 14 to the mode switching signal S12.
It is a circuit for outputting to the output buffer 18 in accordance with. For example, the data switching unit 15 is composed of two circuits and one selection switch element, and the midpoint thereof is connected to the external terminal D via the output buffer 18.
It is connected to Q1 and point a is I / I of the memory cell block MI.
It is connected to the normal output of the O gate, and point b is connected to the test output of the I / O gate.

The input / output data switching unit 16 is a circuit for selecting input / output according to the mode switching signal S12. The input / output data switching unit 16 is composed of a pair of two-circuit / one-selection switch element, one middle point is connected to the external terminal DQ2 via the input buffer 17, and point a is the memory cell block M.
2 is connected to the normal input of the I / O gate, and point b is its I
Each is connected to the test input of the / O gate. The other middle point is connected to the external terminal DQ2 via the output buffer 18, the a point is connected to the normal output of the I / O gate of the memory cell block M2, and the b point is the test output of the I / O gate. Connected.

Similarly, the other input / output data switching section 16 is
One of the middle points is connected to the external terminal DQ3 via the input buffer 17.
To DQ8, the point a is connected to the normal input of the I / O gate of each of the memory cell blocks M3 to M8, and the point b is connected to the test input of the I / O gate. The other middle point is connected to the external terminals DQ3 to DQ8 via the output buffer 18, the a point is connected to the normal output of the I / O gate of the memory cell blocks M3 to M8, and the b point is the I / O. Each is connected to the test output of the gate.

As a result, the input data switching unit 13, the data switching unit 15, and the input / output data switching unit 16 can be simultaneously connected to the point a or the point b according to the mode switching signal S12. The selection of point a indicates the normal operation mode, and the selection of point b indicates the test operation mode. Next, the first of the present invention
With respect to the test method of the multi-bit memory according to the embodiment, the operation at the time of the test of the self-test circuit 100 of the memory will be described. For example, four memory 101 with self-test function
When testing up to 104 at the same time, as shown in FIG. 4, first, the memories 101 to 104 and the test apparatus 105 are connected.

Here, the test apparatus 105 has an output driver 51 and an input / output driver 52 for one memory. The output driver 51 supplies a voltage (input information) VHH higher than the voltage during normal operation to the external terminals DQ of the memories 101 to 104.
2 is supplied. The input / output driver 52 is connected to the external terminal DQ1 of each of the memories 101 to 104 and sends and receives the input data DIN and the judgment result data DOUT.

When testing the multi-bit memory thus connected, the input information VHH for identifying the test operation mode is supplied to the respective external terminals DQ2 of the memories 101-104. For example, in one memory, as shown in FIG. 5, when the input information VHH from the external terminal DQ2 is detected by the mode determination unit 11 of the self-test circuit 100, it is determined whether the operation mode is the normal operation or the test operation mode. , Mode determination unit 1
Based on the determination signal S11 from 1, the control unit 12 generates the mode switching signal S12.

As a result, when the input data DIN is supplied through the external terminal DQ1 of each of the memories 101 to 104 which has shifted to the test operation mode, the data distribution unit 13 receives the external terminal in response to the mode switching signal S12 from the control unit 12. Input data DIN from DQ1 has eight memory cell blocks M1 to M8
Are supplied in parallel. Further, the read data D1 to D8 from the eight memory cell blocks M1 to M8 are judged by the data judging section 14, and the judgment result data DOUT of the serial column at this time are output to the data switching section 15.
The determination result data DOUT from the data determination unit 14 is output from the data switching unit 15 to the test apparatus 105 via the external terminal DQ1 according to the mode switching signal S12.

As a result, the judgment result data DOUT from each of the memories 101 to 104 is sent to the test apparatus 10 via the external terminal DQ1.
Incorporated in 5 (first test method). This gives 4
It is possible to simultaneously test the memories 101 to 104 with the self-test function. During the memory test, the input data switching unit 13, the data switching unit 15, and the input / output data switching unit 16 are simultaneously connected to the point b in response to the mode switching signal S12, and therefore are connected to the external terminals DQ2 to DQ8. The input buffer 17 and the output buffer 18 are deactivated.

When the input information VHH is removed from the external terminal DQ2, the input data switching section 13 and the data switching section 15 are removed.
Since the input / output data switching unit 16 is simultaneously connected to the point a, as shown in FIG. 6, the external terminals DQ1 to DQ8 are connected.
The input buffer 17 and the output buffer 18 connected to are connected to the memory cell blocks M1 to M8, respectively. Mode determination unit 11, control unit 12, and data determination unit 1
4 is in a non-operating state.

In this way, according to the multi-bit memory of the embodiment of the present invention, as shown in FIG. 3, when the test operation mode is determined, the input data DIN is input using one external terminal DQ1. To eight memory cell blocks M1 to M8
And a self-test circuit 100 for outputting the judgment result data DOUT from the memory cell blocks M1 to M8 to the test apparatus 105 via the same external terminal DQ1.

Therefore, the input data DIN during the memory test is
Can be received from the test apparatus 105 using the external terminal DQ1, and the determination result data DOUT can be transmitted to the test apparatus 105 using the same external terminal DQ1. Further, unlike the conventional example, the coincidence / non-coincidence of the read data D1 to D8 from the memory cell blocks M1 to M8 with respect to the input data DIN can be self-determined inside each of the memories 101 to 104. That is, the judgment result data DOUT of the write or read test based on the 8-bit input / output data DIN / D1 to D8 is transferred to the test device 105 via the external terminal DQ1 and the data comparison inside the test device as in the conventional example is performed. No longer depends on the judgment unit.

As a result, even when the number of bits of the semiconductor memory is increased and the number of external terminals is increased, the test device
It is possible to suppress an increase in the number of data comparison / determination units 105 and the number of drivers / comparators. In addition, efficiently test the memory cell blocks M1 to M8 having a multi-bit configuration,
In addition, it is possible to reduce the test cost. Further, according to the test apparatus according to the embodiment of the present invention, each of the memories 101 to 104 which has shifted to the test operation mode is simultaneously tested by the four output drivers 51 and the input / output drivers 52.

Therefore, it is possible to confirm the operation of all the memory cells of one memory by the 1-bit input / output driver 51 and the comparator. As a result, even when the number of bits of the memory is increased and the number of external terminals is increased, it is possible to simultaneously perform the memory test for the existing driver / comparator number. For example, it becomes possible to simultaneously test N n-bit memories by using N drivers / comparators equipped for n-bit memory single-unit testing.

As a result, it becomes possible to sufficiently meet the demand for a high-speed test in which two or more multi-bit memories are simultaneously tested. Further, it is possible to simplify the test apparatus 105, reduce its cost, and improve the test cost performance. (2) Description of Second Embodiment FIG. 7 shows a block diagram of a multi-bit memory with a self-test function according to a second embodiment of the present invention. Unlike the first embodiment, the second embodiment is provided with a self-test circuit 200 which selectively inputs / outputs input data DIN, judgment result data DOUT and read data Di.

That is, as shown in FIG. 7, the second multi-bit memory of the present invention comprises a self-test circuit 200, eight memory cell blocks M1 to M8, seven input / output data switching units 26, and eight input buffers. 27 and eight output buffers 28. The self-test circuit 200 includes the mode determination unit 2
1, a decoding unit 22, a control unit 23, a data distribution unit 24, and a data determination output unit 25.

The mode determination section 21 is a circuit which detects the input information from the external terminal DQ2 to determine the normal operation or test operation mode and outputs the determination signal S21 to the control section 23.
The decoding unit 22 decodes the input information from the external terminals DQ3 to DQ8 and outputs the block selection signal S22 to the control unit 23.
Is a circuit that outputs to. The input information is binary data that selects any one of the eight memory cell blocks M1 to M8.

The control section 23 is a circuit for generating an input / output control signal S23 based on the determination signal S21 from the mode determination section 21 and the block selection signal S22 from the decoding section 22. The signal S23 is output to the data distribution unit 24, the data determination output unit 25, and the input / output data switching unit 26, respectively. The data distribution unit 24 receives the input data DIN from the external terminal DQ1 according to the input / output control signal S23 from the control unit 23.
Are supplied to eight memory cell blocks M1 to M8 in parallel or serially. The data judgment output unit 25 outputs the read data Di, [i = 1 to 8] from any of the eight memory cell blocks M1 to M8 or the judgment result data DOUT of the serial column in accordance with the input / output control signal S23. It outputs to the output buffer 28 connected to the terminal DQ1.

The determination result data DOUT is obtained by determining the read data D1 to D8 from the eight memory cell blocks M1 to M8. The judgment condition at this time is the input data D
Find out whether the read data D1 to D8 match the IN. The normal input of the memory cell block M1 also serves as a test input, and the normal output thereof also serves as a test output. Others having the same names as those in the first embodiment have the same functions, and thus the description thereof will be omitted.

Next, referring to FIG. 7, the second embodiment of the present invention will be described.
The operation at the time of testing the multi-bit memory according to the embodiment will be described. For example, the mode determination unit 21 of the self-test circuit 200 detects the input information from the external terminal DQ2, determines that it is the "test operation mode", and further, the external terminal DQ2.
When the block selection signal S22 obtained by decoding the input information from 3 to DQ8 is output from the decoding unit 22 to the control unit 23, based on the determination signal S21 from the mode determination unit 21 and the block selection signal S22 from the decoding unit 22. Control unit 2
At 3, the input / output control signal S23 is generated.

As a result, the data distribution unit 24 receives the external terminal DQ1 in response to the input / output control signal S23 from the control unit 23.
The input data DIN from the memory cell block M1 has eight
Is supplied to M8 in parallel or serially. Also, 8
The read data Di, [i = 1 to 8] from any one of the memory cell blocks M1 to M8 is directly output, or the determination result data DOUT of the serial column is transmitted via the external terminal DQ1 in accordance with the input / output control signal S23. And is output from the data determination output unit 25 to an external test device (second test method).

In this way, according to the multi-bit memory of the second embodiment of the present invention, as shown in FIG. 7, the self-test circuit 200, the eight memory cell blocks M1 to M8,
7 input / output data switching units 26, 8 input buffers 2
Self test circuit 20 with 7 and 8 output buffers 28
0 is the mode determination unit 21, the decoding unit 22, the control unit 2
3. It has a data distribution unit 24 and a data judgment output unit 25.

Therefore, the input data DIN during the memory test is
Can be received from the test apparatus using the external terminal DQ1 and the determination result data DOUT or read data Di can be directly transmitted to the test apparatus using the same external terminal DQ1. Further, unlike the first embodiment, the read data Di from each of the memory cell blocks M1 to M8 can be directly transferred to the test apparatus, and the operation check of all the memory cells and the specific memory cell block M can be performed.
It is possible to execute two types of tests for confirming the operation of i.

As a result, even if the number of bits of the semiconductor memory is increased and the number of external terminals is increased, a plurality of memories with a self-test function are simultaneously tested, and
It is possible to suppress an increase in the number of data comparison / determination units and the number of drivers / comparators in the test apparatus. Further, similarly to the first embodiment, it is possible to efficiently test the memory cell block having a multi-bit structure and to reduce the test cost.

In each of the embodiments of the present invention, the case where a plurality of memory units with a self-test function are tested at the same time is explained. However, the case where a mounting board in which a plurality of memories with a self-test function are modularized is tested, The test method of the present invention can be applied to a burn-in test device for a memory reliability test, and similar effects can be obtained.

[0061]

As described above, according to the semiconductor memory device of the present invention, the test operation mode is determined, input data is supplied to a plurality of memory cell blocks using one external terminal, and this memory is used. It has a self-test circuit that outputs the determination result data obtained by self-determining the read data from the cell block via the same external terminal.

Therefore, the memory operation test can be performed by the self-test circuit using the minimum number of external terminals, and even if the number of external terminals is increased due to the increase in the number of bits of the semiconductor memory device, the test can be performed. It is possible to suppress an increase in the number of data comparison / determination units and the number of drivers / comparators in the device. According to another semiconductor memory device of the present invention, one external terminal is used to supply input data to a plurality of memory cell blocks in parallel or serially, and read data of a memory cell block or determination result data is output to the same external device. It has a self-test circuit that outputs to the outside through a terminal.

Therefore, the read data from each memory cell block can be directly transferred to the test apparatus,
It is possible to execute two types of tests, that is, the operation confirmation of all memory cells and the operation confirmation of a specific memory cell block. According to the test method and the test apparatus for a semiconductor memory device of the present invention, a test signal is supplied via one external terminal of each semiconductor memory device that has transitioned to the test operation mode, and each test from the semiconductor memory device is performed. The result signal is taken into each device through the same external terminal, and a plurality of semiconductor memory devices are tested at the same time.

Therefore, it is possible to confirm the operation of all the memory cells of one semiconductor memory device by the 1-bit input / output driver and the comparator. As a result, even when the number of bits of the semiconductor memory device is increased and the number of external terminals is increased, the semiconductor memory device can be simultaneously tested by the number of existing drivers / comparators.

As a result, it is possible to test two or more semiconductor memory devices simultaneously and at a high speed, and to simplify the test device and reduce its cost. Moreover, it greatly contributes to the reduction of the test cost.

[Brief description of drawings]

FIG. 1 is a principle diagram (1) of a semiconductor memory device according to the present invention.

FIG. 2 is a principle diagram (No. 2) of the semiconductor memory device according to the present invention.

FIG. 3 is a configuration diagram of a multi-bit memory with a self-test function according to the first embodiment of the present invention.

FIG. 4 is a connection diagram at the time of testing a multi-bit memory according to each embodiment of the present invention.

FIG. 5 is an equivalent circuit diagram during a memory test according to the first embodiment of the present invention.

FIG. 6 is an equivalent circuit diagram of the multi-bit memory according to the first embodiment of the present invention during normal operation.

FIG. 7 is a configuration diagram of a multi-bit memory with a self-test function according to a second embodiment of the present invention.

FIG. 8 is a configuration diagram of a multi-bit memory according to a conventional example.

FIG. 9 is a connection diagram at the time of a test of a multi-bit memory for explaining the problems related to the conventional example.

[Explanation of symbols]

 100, 200 ... Self-test circuit, 11, 21 ... Mode determination unit, 12, 23 ... Control unit, 13, 24 ... Data distribution unit, 14 ... Data determination unit, 15 ... Data switching unit, 16 ... Input / output data switching unit , 17, 27 ... Input buffer, 18, 28 ... Output buffer, 22 ... Decoder, 25 ... Data determination output section, DQ1 to DQ8 ... External terminals, M1 to Mn ... Memory cell block, DIN ... Input data, VHH ... Input information , DOUT ... Judgment result data, D1-D8 ... Read data, S11, S21 ... Judgment signal, S12 ... Mode selection signal, S22 ... Block selection signal, S23 ... Input / output control signal.

Claims (7)

[Claims] 1. A multi-bit semiconductor memory device having a plurality of memory cell blocks, wherein a normal operation or a test operation mode is determined from input information of a first external terminal, and the test operation mode is determined. ,
The determination result data obtained by determining the read data from the plurality of memory cell blocks by supplying the input data from the second external terminal to the plurality of memory cell blocks
A semiconductor memory device having a self-test circuit for outputting to the outside through an external terminal of. 2. The self-test circuit detects the input information from the first external terminal to determine a normal operation or test operation mode, and a mode determination section based on a determination signal from the mode determination section. A control unit that generates a switching signal; a data distribution unit that supplies input data from a second external terminal to the plurality of memory cell blocks in parallel in response to a mode switching signal from the control unit; A data determination unit that determines read data from the cell block and outputs determination result data of the serial column, and a determination result data from the data determination unit via the second external terminal according to the mode switching signal. The semiconductor memory device according to claim 1, further comprising a data switching unit for outputting. 3. A multi-bit semiconductor memory device having a plurality of memory cell blocks, wherein a normal operation or a test operation mode is determined from input information of a first external terminal, and when the test operation mode is determined. ,
Input data from the second external terminal is supplied to the plurality of memory cell blocks in parallel or serially to determine any read data from the plurality of memory cell blocks or read data from the plurality of memory cell blocks. A semiconductor memory device having a self-test circuit for outputting the determination result data of the serial column to the outside through the second external terminal. 4. The self-test circuit includes a mode determination unit that detects input information from the first external terminal and determines a normal operation or test operation mode, a second external terminal and the first external terminal. A decoding unit that decodes input information from other than the above and outputs a block selection signal that selects one of the plurality of memory cell blocks; and a determination signal from the mode determination unit and a block selection signal from the decoding unit. A control unit for generating an input / output control signal based on the control unit, and a data distribution for supplying input data from a second external terminal to the plurality of memory cell blocks in parallel or serially in response to the input / output control signal from the control unit Section, and serial data for determining read data from any of the plurality of memory cell blocks or read data from the plurality of memory cell blocks. The determination result data semiconductor memory device according to claim 3, wherein a and a data decision output unit for outputting the output control signal corresponding through said second external terminals a. 5. A method of testing a semiconductor memory device having a plurality of memory cell blocks and having a self-test function, wherein input information for identifying a test operation mode is supplied to a first external terminal of the semiconductor memory device, A test signal is supplied via a second external terminal of the semiconductor memory device that has shifted to the test operation mode, and a test result signal from the semiconductor memory device is fetched into the test device via the second external terminal. A method for testing a semiconductor memory device having a feature. 6. When the test result signal from the semiconductor memory device is input to the test device using the second external terminal,
6. The selection data for selecting any one of the plurality of memory cell blocks is supplied to vacant external terminals other than the first external terminal and the second external terminal. A method for testing a semiconductor memory device as described. 7. A test device for a semiconductor memory device having a self-test function, wherein input information for identifying a test operation mode is supplied to first external terminals of each of the plurality of semiconductor memory devices, and the test operation mode is supplied. Of each of the semiconductor memory devices that have been moved to
A test signal is supplied from each of the semiconductor memory devices via the second external terminal, and a test signal is supplied from each of the semiconductor memory devices via the second external terminal. Semiconductor memory device test equipment.