JPH0896022A - Chip layout method - Google Patents

Abstract

PURPOSE: To provide a chip layout method which can secure the maximum chip area without increasing the chip cost. CONSTITUTION: In a chip layout using an I/O cell 10 having an expandable wiring 14, the minimum size of a semiconductor chip is calculated when the wiring 14 is contracted. Then, the number of chips that can be formed in the minimum size is calculated for a semiconductor wafer of a prescribed inch. Meanwhile, the maximum chip size is calculated within a range where the number of logical chips has no change, and the wiring 14 is expanded by an extent equal to the half of difference between the calculated maximum and minimum sizes. Thereby, a new application area is produced between a pad 16 and the cell 10.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a chip layout method capable of effectively utilizing a chip area in manufacturing a semiconductor chip.

[0002]

2. Description of the Related Art In semiconductor manufacturing, in order to reduce the manufacturing cost per chip, the size of the chip has been reduced, and the demand for higher functionality of the chip has been accompanied by higher integration of the chip. . Therefore, in the design stage of a semiconductor chip, how to efficiently lay out each circuit in the chip is very important in order to make the most of a small chip area.

[0003]

However, in the past, due to the high integration of semiconductor chips, there is no space in the chip for wiring areas, dummy cells, etc., and the layout is required when revisions or the like are required. It is difficult to fix. Further, due to high integration, surge, latch-up, and drive capability may decrease. On the other hand, if the chip size is increased to reduce the integration density,
Since the number of chips that can be manufactured from one semiconductor wafer is reduced, the chip cost is increased.

Therefore, an object of the present invention is to provide a chip layout method capable of ensuring the maximum chip area without increasing the chip cost.

[0005]

According to a first aspect of the present invention, there is provided a chip layout method, wherein an I / O cell in which a connecting portion with a bonding pad extends is used to minimize the connecting portion. A semiconductor which can be formed on the semiconductor wafer by calculating the minimum size of the semiconductor chip, calculating the theoretical number of chips when forming the obtained minimum size semiconductor chip on a semiconductor wafer of a predetermined inch, and changing the calculated theoretical chip number. The maximum size of the chip is obtained, the difference between the obtained maximum size and the minimum size is calculated, and the above-mentioned object is achieved by arranging the bonding pad at a position where the connecting portion is extended by half the length of the calculated difference. To achieve. According to a second aspect of the present invention, in the chip layout method according to the first aspect, the connection portion of the I / O cell has one end connected to the metal having one end connected to the bonding pad side and one end connected to the I / O cell side. And the metal of the same material that has been laminated on the other end side to form a two-layer structure,
The above objects are achieved by the two metals sliding and stretching. According to the invention of claim 3, in the chip layout method, the minimum size of the semiconductor chip when the I / O cell of the minimum size is arranged among a plurality of I / O cells of different sizes prepared in advance is obtained, Calculate the theoretical chip number when forming the obtained minimum size semiconductor chip in a semiconductor wafer of a predetermined inch, and obtain the maximum size of the semiconductor chip that can be formed in the semiconductor wafer without changing the calculated theoretical chip number. The object is achieved by selecting and arranging the largest I / O cell that can be arranged in the semiconductor chip of the maximum size from the plurality of I / O cells.

[0006]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Each embodiment of the chip layout method of the present invention will be described in detail below with reference to FIGS.

FIG. 1 shows a structure of an I / O cell and a bonding pad used in the chip layout method according to the first embodiment. As shown in FIG. 1A, the I / O chip 10 has a wiring 14 that can extend, and the wiring 14 connects the pad 16 to the pad 16. The wiring 14 is composed of a metal 14a whose one end is connected to the pad 16 side and a metal 14b whose one end is connected to the I / O cell side. These metals 14a, 14
b is made of the same material and overlaps each other at the other end
It has a layer structure. As shown in FIG. 1B, the wiring 14 is expanded by the movement of the pad 16 as indicated by the arrow and sliding of the metal 14 a, 14 b, and the pad 1
6 and the I / O cell 10 are widened.
In this embodiment, all the I
I / O cell 10 shown in FIG. 1 as an I / O cell.
To use.

Next, a specific procedure of the layout method using the above I / O cell 10 will be described. In the chip layout method of the present embodiment, first, in order to minimize the chip area, the wiring 14 is contracted as shown in FIG. 1A, and the I / O cell 10 is set to the minimum length. And
The size of the semiconductor chip when the I / O cell 10 is minimized, that is, the minimum size is obtained. Next, the theoretical number of chips that can be formed on a 6-inch semiconductor wafer, for example, is calculated from the obtained minimum size of chips.
Generally, when chips are formed on a semiconductor wafer, a lot of useless space remains at the edge of the wafer. Therefore,
The theoretical number of chips may not change even if the size per chip is changed by a predetermined amount. For example, 10.02x
The theoretical number of chips is the same for a 6 inch wafer for a 10.02 mm square chip and a 10.10 × 10.10 mm square chip.

Therefore, in this embodiment, the size of the largest chip (maximum size) is found within the range in which the theoretical number of chips found from the size of the smallest size chip does not change. Then, the I / O cell 10 and the pad 16 are laid out according to the obtained maximum size semiconductor chip. That is, the difference from the chip size when the above-mentioned I / O cell 10 is minimized is taken, and I / O for half the value is taken.
The cell 10 is stretched. For example, in the above example, 10.1
Since 0mm-10.02mm = 0.08mm, the maximum is about 4
Stretch to 0 μm. The length of extension at this time is set so that the metal 14a and the metal 14b are not cut.
For example, if the width where the metal 14a and the metal 14b overlap with each other is set to about 40 μm or more in advance, it is possible to extend by 40 μm. However, the extension of the wiring 14 is
The range of manufactured semiconductor chips shall not exceed the package cavity size. In the maximum size semiconductor chip in which the I / O cell 10 is expanded as described above (see FIG. 1B), a usable area is formed between the pad 16 and the I / O cell 10.

FIG. 2 shows a part of a semiconductor chip when the I / O cell 10 is expanded. As shown in FIG. 2, in the present embodiment, the wiring 14 that is a connection portion with the pad 16 is expanded, and the pad 16 is moved to the outside with respect to the chip inside 18, the power supply line 19, and the GND line 20, Between the pad 16 and the I / O cell 10, a use area S for arranging a wiring area and a dummy cell is newly formed. As described above, in the present embodiment, the use area S for newly securing the wiring area and the dummy cell placement area is formed within the range where the theoretical number of chips does not change, that is, within the range where the chip cost does not change. I can do it. Therefore, the layout correction can be easily performed by using the use area S, and the correction work can be simplified and shortened.

Next, a second embodiment will be described. The same components as those in the first embodiment are designated by the same reference numerals, and detailed description thereof will be appropriately omitted. Figure 3
Shows an I / O cell used in the chip layout method of the present embodiment. In this embodiment, as shown in FIG. 3, three I / O cells 22 and 2 having different sizes are used.
Prepare 4 and 26 in advance. The I / O cell 22 is of an original size used in a normal chip layout, and the I / O cells 24 and 26 are the I / O cells 22.
On the other hand, the size is increased in two steps. Large I / O with surge, latch-up and drive capability
The cell is better. That is, the I / O cell 24 is the I / O
I / O cell 26 is superior to cell 22 over I / O cell 24.

Next, the above I / O cells 22, 24, 26
A specific procedure of the chip layout method using is explained. First, as shown in FIG. 4A, a chip layout is performed using the smallest size I / O cell 22. Then, from the minimum size of the semiconductor chip when the I / O cell 22 is used, for example, the theoretical number of chips that can be formed in a 6-inch semiconductor chip is calculated. Next, the maximum chip size that does not change the theoretical number of chips is calculated.
For example, for a 6 inch wafer, as described above,
10.02 × 10.02mm square chip and 10.10 × 1
The theoretical number of chips is the same for 0.10 mm square chips.

Therefore, in this embodiment, the layout is performed for the calculated maximum size semiconductor chip. That is, the largest I / O cell within the maximum chip size is selected from the I / O cells 24 and 26, and the I / O cell 22 is replaced in the largest semiconductor chip. In the above example, since 10.10 mm-10.02 mm = 0.08 mm, the size difference from the I / O cell 22 is 0.08 mm.
The I / O cell having the largest size is replaced with the I / O cell 22 within a range of half a mm (40 μm) or less. By this replacement, the I / O cells having higher surge, latch-up, and drive capability than the I / O cells 22 are arranged on the semiconductor chip. Note that FIG. 4B shows a chip layout when the largest I / O cell that can be accommodated in the largest semiconductor chip is the I / O cell 26. Further, in this embodiment, in order to simplify the replacement work of the I / O cells, the connection part 28 to the inside 18 of the chip is connected to each I / O cell 2.
It is common to 2, 24 and 26.

As described above, according to the chip layout method of this embodiment, the maximum size I / O cell is arranged within the range in which the theoretical number of chips is not changed, that is, the range in which the chip cost is not changed. You can do it. Therefore,
At the same chip cost, it is possible to manufacture a semiconductor chip having an I / O cell that is more excellent in surge, latch-up and drive capability. In addition, in the second embodiment, only three I / O cells were prepared in advance.
One or more I / O cells having different sizes may be prepared. In this case, by reducing the size difference between the I / O cells, the I / O having a more accurate size can be obtained.
It becomes possible to select a cell.

[0015]

According to the chip layout method of the present invention, the maximum chip area can be secured without increasing the chip cost.

[Brief description of drawings]

FIG. 1 is an explanatory diagram showing an I / O cell used in a chip layout method according to a first embodiment of the present invention.

FIG. 2 is an explanatory diagram showing a part of a semiconductor chip laid out by the same chip layout method.

FIG. 3 is an explanatory diagram showing an I / O cell used in a chip layout method according to a second embodiment of the present invention.

FIG. 4 is an explanatory diagram showing a part of a semiconductor chip laid out by the same chip layout method.

[Explanation of symbols]

 10, 22, 24, 26 I / O cell 14 Wiring 14a, 14b Metal 16 Pad 18 Inside chip 19 Power line 20 GND line S Utilization area

Claims (3)

[Claims] 1. A minimum size of a semiconductor chip when an I / O cell in which a connecting portion with a bonding pad extends is used to minimize the connecting portion, and a semiconductor chip having the obtained minimum size is obtained. Calculate the theoretical number of chips when forming on a semiconductor wafer of a predetermined inch, find the maximum size of semiconductor chips that can be formed on the semiconductor wafer without changing the calculated number of theoretical chips, and find the maximum size and the minimum size The chip layout method is characterized in that the bonding pad is arranged at a position where the connecting portion extends by a length half the calculated difference. 2. The I / O cell connecting portion is connected to the metal whose one end is connected to the bonding pad side and the I / O cell.
2. The chip layout method according to claim 1, wherein a metal of the same material, one end of which is connected to the O cell side, is overlapped on the other end to form a two-layer structure, and both metals slide to expand. 3. A plurality of Is of different sizes prepared in advance
Of the minimum size of the I / O cells among the / O cells, the minimum size of the semiconductor chip is calculated, and the theoretical number of chips when forming the calculated minimum size semiconductor chip on a semiconductor wafer of a predetermined inch is calculated. Then, the maximum size of the semiconductor chips that can be formed on the semiconductor wafer is determined without changing the calculated theoretical number of chips, and the maximum I / O cell that can be arranged in the determined maximum size semiconductor chip is set to the plurality of I / Os. A chip layout method characterized by selecting and arranging from cells.