JPH0895851A - Electronic equipment with expansible memory - Google Patents

Abstract

PURPOSE: To make the addresses of the expanded memory area of a mounted IC memory consecutive through a simple switching operation even if a blank address is generated halfway in the expanded memory area. CONSTITUTION: The CS1 signal input terminal 21 of an expansion memory board 15 is connected to an IC memory mount part 27a and the CS2 signal input terminal 22 is connected selectively to the IC memory mount part 27b and a signal output terminal 25 through a signal switching part 28a, and, the CS3 signal input terminal 23 is connected selectively to signal output terminals 25 and 26 through a signal switching part 28b and the CS4 signal input terminal 24 is connected selectively to the signal output terminal 26 through a signal switching part 28c. Further, the signal input terminal 35 of a 1st expansion slot 16 and the signal output terminal 41 of a 2nd expansion slot 17 are connected and the signal input terminal 36 of the 1st expansion slot 16 and the signal output terminal 42 of the 2nd expansion slot 17 are connected. Then CS1-SC4 signals from a CPU 11 are supplied to the 1st expansion slot 16.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory expandable electronic device such as a personal computer and a POS (point of sale information) terminal.

[0002]

2. Description of the Related Art In general, electronic devices with expandable memory are
It has an expansion slot for installing an expansion memory board. For example, an electronic device capable of expanding the memory to a maximum of 2 MB in 0.5 MB (megabit) units has two expansion slots, a first expansion slot and a second expansion slot. Then, as shown in FIG. 10A, an expansion memory board 3a having a storage capacity of 0.5 MB, in which an IC memory 2 of 0.5 MB is mounted on one of the pair of memory mounting portions 1a and 1b, as shown in FIG. When,
As shown in FIG. 10B, a pair of memory mounting portions 1a, 1
By selectively attaching the expansion memory board 3b having a storage capacity of 1 MB in which the IC memory 2 of 0.5 MB is mounted to both b, it is possible to expand the memory to a desired storage capacity.

In FIG. 10, reference numeral 4 indicates a connector portion with an expansion slot, and CS indicates a signal line for a chip select signal.

FIG. 11 shows a circuit diagram of a main part of this type of electronic equipment. That is, the CPU that constitutes the main control unit of the device body
The first and second chip select signals CS1 and CS2 are provided between the (central processing unit) 5 and the first expansion slot 6.
Signal line is provided between the CPU 5 and the second expansion slot 7 and the third and fourth chip select signals CS
Signal lines 3 and CS4 are wired. The CPU5
Although not shown, bus lines of an address bus and a data bus, signal lines of a read access signal and a write access signal, and the like are also wired between the and each expansion slot 6 and 7.

Incidentally, the first chip select signal CS1
Is a signal for selecting the IC memory 2 mounted in one memory mounting portion 1a of the expansion memory board 3 (3a or 3b) mounted in the first expansion slot 6, and the second chip select signal CS2 is the same. This is a signal for selecting the IC memory 2 mounted on the other memory mounting portion 1b of the expansion memory board 3. In addition, the third chip select signal CS3
Is a signal for selecting the IC memory 2 mounted in one memory mounting portion 1a of the expansion memory board 3 mounted in the second expansion slot 7, and a fourth chip select signal C
S4 is the other memory mounting portion 1b of the extended memory board 3
This is a signal for selecting the IC memory 2 mounted on the.

Here, an example of a memory map of the electronic device is shown in FIG. As shown in the figure, in the electronic device, from [000000] H address to [9FFFFF] H
ROM preloaded in electronic equipment up to the address
(Read-only memory) and RAM (random access memory) areas, and extended memory area of IC memory 2 corresponding to the first chip select signal CS1 from [A00000] H to [A7FFFF] H Then, from [A80000] H address to [AFFFFF]
Addresses up to H are used as the extended memory area of the IC memory 2 corresponding to the second chip select signal CS2, and [B0000
0] H to [B7FFFF] H are used as the extended memory area of the IC memory 2 corresponding to the third chip select signal CS3, and [B80000] H to [BF
FFFF] 4th chip select signal CS up to address H
4 corresponds to the expanded memory area of the IC memory 2.

In this case, the CPU 5 causes [A00000]
When the processing to access the extended memory area from address H to [A7FFFF] H occurs, the first chip select signal CS1 is sent, and the extended memory area from [A80000] H to [AFFFFF] H is accessed. When processing occurs, the second chip select signal C
S2 is sent out, and from [B00000] H address to [B7FF
When the processing to access the extended memory area up to the address FF] H occurs, the third chip select signal CS3 is transmitted, and the processing to access the extended memory area from the address [B80000] H to the address [BFFFFF] H occurs. The program is configured to output the fourth chip select signal CS4.

[0008]

By the way, in the case of the memory expandable electronic device having the above-mentioned structure, for example, when expanding the memory of 1.5 MB, the expansion memory board 3a of 0.5 MB and the expansion of 1 MB. Memory board 3b
And may be added to the first and second expansion slots 6 and 7, respectively.

However, 0.5M in the first expansion slot 6
When the B extension memory board 3a is attached and the 1MB extension memory board 3b is attached to the second extension slot 7, the IC memory 2 corresponding to the second chip select signal CS2
No. is not mounted, therefore, from [A80000] H address to [AFFFFF] H address among all the extended memory areas, it becomes an empty address.

In addition, for example, when two 0.5 MB expansion memory boards 3a are used to expand the memory of 1 MB, the second chip select signal CS is similarly used.
Since the IC memory 2 corresponding to 2 is not mounted,
Free addresses are available from [A80000] H to [AFFFFF] H.

As described above, when a vacant address is generated in the middle of the memory area, the process of skipping to the address where the IC memory 2 is mounted is executed every time the process of accessing the memory area of the vacant address occurs. Will be needed.

Therefore, in the conventional electronic device of this type, the CPU 5 can automatically perform the process of skipping to the address where the IC memory 2 is mounted every time the process of accessing the memory area of the empty address occurs. The program was designed to. For this reason, the program was complicated and the processing speed was reduced.

Therefore, according to the present invention, the IC memory is not mounted in at least one of all the memory mounting portions of the expansion memory boat mounted in the first expansion slot, and an empty address is provided in the middle of the entire expansion memory area. If the error occurs, the addresses of the expansion memory areas corresponding to the IC memories mounted on the expansion memory boards mounted in the first and second expansion slots can be made continuous by a simple switching operation of the chip select signal. It is an object of the present invention to provide a memory-expandable electronic device capable of simplifying a program and increasing a processing speed.

[0014]

DISCLOSURE OF THE INVENTION The present invention provides an expansion memory board having n (n ≧ 2) IC memory mounting parts for detachably mounting an IC memory and a connector part of an expansion slot, and an expansion memory. First and second expansion slots to which the connector part of the board is detachably mounted, and n ICs of an expansion memory board to be mounted in the first expansion slot
The first to nth chip select signals and the second chip select signals respectively corresponding to the IC memories mounted in the memory mounting section
Of the n + 1 to 2nth chip select signals respectively corresponding to the respective IC memories mounted in the n IC memory mounting portions of the expansion memory board mounted in the expansion slot of In a memory expandable electronic device having a central processing unit for accessing an IC memory corresponding to a chip select signal, the expansion memory board has a connector section with first to nth
First to n-th chip select signal input terminals to which the chip select signals are respectively input, and n + 1 to second
(n + 1) th to which n chip select signals are respectively input
To 2nth chip select signal input terminals and 1st to nth signal output terminals are provided, and the 1st to nth chip select signal input terminals and each IC memory mounting portion are connected in a one-to-one relationship. At the same time, the second to nth chip select signal input terminals and the first to n-1th signal output terminals can be connected by the first signal switching unit without changing the order of the signals, and the n + 1th to nth The 2n chip select signal input terminals and the first to nth signal output terminals are connected in a one-to-one relationship, and the n + 1th to 2n-th terminals are connected.
The first chip select signal input terminal and the second to nth signal output terminals can be connected by the second signal switching unit without changing the order of signals, and the first expansion slot is the first expansion slot of the expansion memory board. An output terminal for the first to nth chip select signals transmitted from the central processing means is provided facing the to nth chip select signal input terminals, and
The n + 1th to 2nth signals sent from the central processing means in opposition to the (n + 1) th to 2nth chip select signal input terminals.
A chip select signal output terminal and first to nth signal input terminals facing the first to nth signal output terminals, and the second expansion slot includes the first to nth expansion memory boards. First to nth signal output terminals are provided facing the nth chip select signal input terminal, and the first to nth signal input terminals in the first expansion slot are connected to the first to nth in the second expansion slot. n signal output terminals are connected one to one.

[0015]

According to the present invention having such a configuration, the IC of the expansion memory board mounted in the first expansion slot
By switching the first and second signal switching means in accordance with the memory mounting status, the expansion memory board mounted in the second expansion slot according to the IC memory mounting number of the expansion memory board mounted in the first expansion slot. IC
When the number obtained by adding the memory mounting numbers is A, it is possible to selectively access the A IC memories mounted on both expansion memory boards by the first to Ath chip select signals.

[0016]

Embodiments of the present invention will be described below with reference to the drawings. In the first embodiment, the two IC memory mounting parts 27a, 27 for detachably mounting the IC memory 29 are mounted.
b, an expansion memory board 15 having a connector part 20 of an expansion slot, first and second expansion slots 16 and 17 to which the connector part 20 of the expansion memory board 15 is detachably attached, and a first expansion Two IC memory mounting parts 2 of the expansion memory board mounted in the slot 16
First to second chip select signals C corresponding to the respective IC memories 29 mounted on the ICs 7a and 27b.
S1 and CS2, and two IC memory mounting portions 27a of the expansion memory board mounted in the second expansion slot 17
The third to fourth chip select signals CS3 respectively corresponding to the respective IC memories 29 mounted on 27b.
When the present invention is applied to a memory expandable electronic device having a central processing means for selectively sending out CS4 and accessing the IC memory 29 corresponding to the sent out chip select signals CS1 to CS4. I will describe.

FIG. 1 is a block diagram showing a schematic configuration of such an electronic device. This electronic device has an internal RO in which fixed data such as a CPU 11 forming a central processing unit and program data for controlling the CPU 11 is stored in advance.
M12, an internal RAM 13 in which various memory areas for storing variable data written by the data processing of the CPU 11 are formed, a peripheral device interface 14 to which a peripheral device 14a such as a keyboard, a display device and a printer is connected The first and second expansion slots 16 and 17 to which the connector portions of the expansion memory board 15 are detachably attached are mounted, respectively.

The CPU 11, the internal ROM 12,
The internal RAM 13, the peripheral device interface 14, and the first and second expansion slots 16 and 17 are connected by an address bus 18A, a data bus 18D, and various control signal lines 19, respectively.

2A and 2B are schematic circuit diagrams of the expansion memory board 15. FIG. 2A shows a 0.5 MB expansion memory board 15a, and FIG. 2B shows a 1 MB expansion memory board 1.
5b.

These extended memory boards 15a and 15b
First, in the connector section 20 with the expansion slot,
The input terminals 21, 22, 23 and 24 for the fourth to fourth chip select signals CS1 to CS4 and the first and second signal output terminals 25 and 26 are provided.

Then, the first chip select signal CS1
Input terminal 21 is connected to one IC memory mounting portion 27a. In addition, the input terminal 22 of the second chip select signal CS2 is connected to the other I via the first short pin p1.
It is connected to the C memory mounting portion 27b and is also connected to the first signal output terminal 25 via the second shorting pin p2. Here, the first short pin p1 and the second short pin p2 form a first signal switching unit 28a.

The input terminal 23 for the third chip select signal CS3 is connected to the first signal output terminal 25 via the third short pin p3, and the second terminal is connected via the fourth short pin p4. It is connected to the signal output terminal 26. Here, the third short pin p3 and the fourth short pin p4 form a second signal switching unit 28b.

Further, a fourth chip select signal CS4
The input terminal 24 of the second terminal through the fifth shorting pin p5.
Of the signal output terminal 26. Here, the fifth shorting pin p5 constitutes a third signal switching unit 28c.

The first signal switching unit 28a functions as a first signal switching unit, and the second signal switching unit 28b and the third signal switching unit 28c function as a second signal switching unit.

Then, as shown in FIG. 2A, by mounting the 0.5 MB IC memory 29 only on one of the memory mounting portions 27a, an expanded memory board 15a having a storage capacity of 0.5 MB is formed. As shown in (b), the expansion memory board 15b having a storage capacity of 1 MB is formed by mounting the 0.5 MB IC memory 29 on each of the memory mounting portions 27a and 27b.

FIG. 3 is a circuit diagram of an essential part. Between the CPU 11 and the first expansion slot 16, signal lines for the first to fourth chip select signals CS1 to CS4 are connected.

The first expansion slot 16 has first to fourth expansion memory boards 15 which are inserted into the connector 20 of the expansion memory board 15 in a detachable manner.
Output terminals 31, 32, 33 of the first to fourth chip select signals CS1 to CS4 sent from the CPU 11 in opposition to the chip select signal input terminals 21 to 24.
34 and the first and second signal output terminals 2
5 and 26 facing the first and second signal input terminals 35,
36 are provided.

On the other hand, the second expansion slot 17 also has the first to fourth expansion memory boards 15 in which the connector portion 20 of the expansion memory board 15 is detachably attached.
The first to fourth signal output terminals 41, 42, 43 and 44 are provided so as to face the chip select signal input terminals 21 to 24, and the first and second signal output terminals 25.26.
The first and second signal input terminals 45 and 46 are provided so as to face each other.

Then, the first signal input terminal 35 in the first expansion slot 16 and the first signal output terminal 41 in the second expansion slot 17 are connected by a signal line 51, and the first expansion slot 16 is connected. The second signal input terminal 36 in and the second signal output terminal 42 in the second expansion slot 17 are connected by a signal line 52.

The second expansion slot 17 is provided with first and second signal output terminals 41 and 42 facing the first and second chip select signal input terminals 21 and 22 of the expansion memory board 15. Anything is acceptable.

As shown in FIG. 12, the electronic equipment uses the areas [000000] H to [9FFFFF] H as the internal ROM 2 and internal RAM 3 areas.
Addresses from [A00000] H to [A7FFFF] H are used as the extended memory area of the IC memory 29 corresponding to the first chip select signal CS1, and [A80000] H
Addresses from [AFFFFF] H to the expanded memory area of the IC memory 29 corresponding to the second chip select signal CS2, from [B00000] H to [B7FF
FF] H up to the address H is used as an extended memory area of the IC memory 29 corresponding to the third chip select signal CS3, and [B
Addresses 80000] H to [BFFFFF] H are used as the extended memory area of the IC memory 29 corresponding to the fourth chip select signal CS4.

In the first embodiment thus constructed, first, in order to expand the memory by 0.5 MB,
The expansion memory board 15a having a storage capacity of 0.5 MB shown in FIG. 2A may be attached to the first expansion slot 16.
At this time, all the short pins p1 to p5 are opened.

By doing so, the IC memory 29 mounted on one of the memory mounting portions 27a of the expansion memory board 15a is selected by the first chip select signal CS1. Addresses from [A00000] H to [A7FFFF] H will be assigned.

Next, in order to expand the memory of 1 MB, the expansion memory board 15b having a storage capacity of 1 MB shown in FIG. 2B may be attached to the first expansion slot 16.
At this time, the short pins p1 to p5 close p1 and open p2 to p4.

By doing so, the IC memory 29 mounted on one of the memory mounting portions 27a of the expansion memory board 15b is selected by the first chip select signal CS1. Addresses from [A00000] H to [A7FFFF] H are assigned. In addition, the second chip select signal CS2
The other memory mounting portion 2 of the expansion memory board 15b
Since the IC memory 29 mounted on the 7b is selected, the IC memory 29 has an extended memory area [A8000
[0] H to [AFFFFF] H are assigned.

As a result, two ICs mounted on the expansion memory board 15b mounted in the first expansion slot 16
The address of the extended memory area corresponding to the memory 29 is [A0
From [0000] H to [AFFFFF] H,
Continuous.

Further, as shown in FIG. 4, two expansion memory boards 15a each having a storage capacity of 0.5 MB are attached to the first expansion slot 16 and the second expansion slot 17, respectively, to expand the memory of 1 MB. It can also be planned. At this time, each of the short pins p1 to p5 of the expansion memory board 15a attached to the first slot 16 is p
2 is closed and p1, p3, p4 and p5 are opened. Further, all the short pins p1 to p5 of the expansion memory board 15a attached to the second slot 17 are opened.

By doing so, the one memory mounting portion 27 of the expansion memory board 15a attached to the first expansion slot 16 by the first chip select signal CS1.
Since the IC memory 29 mounted in a is selected,
The C memory 29 has an extended memory area [A00000].
[A7FFFF] H address is assigned from address H. Further, the IC memory 29 mounted in one memory mounting portion 27a of the expansion memory board 15a mounted in the second expansion slot 17 by the second chip select signal CS2.
Is selected, the IC memory 29 is stored in the expanded memory area from [A80000] H to [AFFFFF] H.
The address is assigned.

As a result, the expansion memory board 15a mounted in the first expansion slot 16 and the second expansion slot 1
1 for each of the extended memory boards 15a attached to the
The addresses of the extended memory areas corresponding to the IC memories 29 mounted one by one are from [A00000] H to [AFFF
FF] It becomes address H and continues.

Next, in order to expand the memory of 1.5 MB, as shown in FIG. 5, an expansion memory board 15a having a storage capacity of 0.5 M is attached to the first slot 16, and an expansion memory board having a storage capacity of 1 M is installed. 15b may be attached to the second slot 17. At this time, each short pin p1 of the expansion memory board 15a attached to the first slot 16
~ P5 closes p2 and p4 and opens p1, p3 and p5. Further, the short pins p1 to p5 of the expansion memory board 15b attached to the second slot 17 are p
1 is closed and p2 to p5 are opened.

As a result, the one memory mounting portion 27 of the expansion memory board 15a attached to the first expansion slot 16 by the first chip select signal CS1.
Since the IC memory 29 mounted in a is selected,
The C memory 29 has an extended memory area [A00000].
[A7FFFF] H address is assigned from address H. Further, the IC memory 29 mounted in one memory mounting portion 27a of the expansion memory board 15b mounted in the second expansion slot 17 by the second chip select signal CS2.
Is selected, the IC memory 29 is stored in the expanded memory area from [A80000] H to [AFFFFF] H.
The address is assigned. Further, since the third chip select signal CS3 selects the IC memory 29 mounted in the other memory mounting portion 27b of the expansion memory board 15b mounted in the second expansion slot 17, the IC memory 29 is stored in the IC memory 29. Addresses from [B00000] H to [B7FFFF] H are allocated in the extended memory area.

As a result, one IC mounted on the expansion memory board 15a mounted in the first expansion slot 16
The memory 29 and the two IC memories 2 mounted on the expansion memory board 15b mounted in the second expansion slot 17
The addresses of the extended memory areas corresponding to three IC memories 29 of 9 are [A00000] H to [B7FFF
It becomes address F] H and continues.

Further, by mounting the expansion memory board 15b having a storage capacity of 1 MB in the first expansion slot 16 and by mounting the expansion memory board 15a having a storage capacity of 0.5 MB in the second expansion slot 17, the memory expansion of 1 MB can be achieved. It can also be planned. At this time, the short pins p1 to p5 of the expansion memory board 15b attached to the first slot 16 close p1 and p3, and p2, p4 and p5.
Open up. Further, all the short pins p1 to p5 of the expansion memory board 15a attached to the second slot 17 are opened.

By doing so, the one memory mounting portion 27 of the expansion memory board 15b attached to the first expansion slot 16 by the first chip select signal CS1.
Since the IC memory 29 mounted in a is selected,
The C memory 29 has an extended memory area [A00000].
[A7FFFF] H address is assigned from address H. Further, the IC memory 29 mounted in the other memory mounting portion 27b of the expansion memory board 15b mounted in the first expansion slot 16 by the second chip select signal CS2.
Is selected, the IC memory 29 is stored in the expanded memory area from [A80000] H to [AFFFFF] H.
The address is assigned. Furthermore, since the third chip select signal CS3 selects the IC memory 29 mounted in one memory mounting portion 27a of the expansion memory board 15a mounted in the second expansion slot 17, the IC memory 29 is Addresses from [B00000] H to [B7FFFF] H are allocated in the extended memory area.

As a result, the two ICs mounted on the expansion memory board 15b mounted in the first expansion slot 16
Memory 29 and one IC memory 2 mounted on the expansion memory board 15a mounted in the second expansion slot 17
The addresses of the extended memory areas corresponding to three IC memories 29 of 9 are [A00000] H to [B7FFF
It becomes address F] H and continues.

Next, in order to expand the memory of 2 MB, as shown in FIG. 6, two expansion memory boards 15 b each having a storage capacity of 1 M should be attached to the first slot 16 and the second slot 17, respectively. Good. At this time, the short pins p1 to p5 of the expansion memory board 15b attached to the first slot 16 close p1, p3 and p5, and p
Open 2, p4. In addition, each short pin p1 of the expansion memory board 15b attached to the second slot 17
~ P5 closes p1 and opens p2 to p5.

By doing so, one memory mounting portion 27 of the expansion memory board 15b attached to the first expansion slot 16 by the first chip select signal CS1.
Since the IC memory 29 mounted in a is selected,
The C memory 29 has an extended memory area [A00000].
[A7FFFF] H address is assigned from address H. Further, the IC memory 29 mounted in the other memory mounting portion 27b of the expansion memory board 15b mounted in the first expansion slot 16 by the second chip select signal CS2.
Is selected, the IC memory 29 is stored in the expanded memory area from [A80000] H to [AFFFFF] H.
The address is assigned. Furthermore, since the third chip select signal CS3 selects the IC memory 29 mounted in one memory mounting portion 27a of the expansion memory board 15b mounted in the second expansion slot 17, the IC memory 29 is stored in the IC memory 29. Addresses from [B00000] H to [B7FFFF] H are allocated in the extended memory area. Further, the IC memory 29 mounted in the other memory mounting portion 27b of the expansion memory board 15b mounted in the second expansion slot 17 by the fourth chip select signal CS4.
Is selected, the IC memory 29 is expanded to [BF80FF] H from [B80000] H in the extended memory area.
The address is assigned.

As a result, the expansion memory board 15b mounted in the first expansion slot 16 and the second expansion slot 1
2 for each of the extended memory boards 15b mounted on the
The addresses of the extended memory areas corresponding to the IC memories 29 mounted individually are from [A00000] H to [BFFF
FF] It becomes address H and continues.

As described above, according to the first embodiment, the first expansion slot 16 and the second expansion slot 16 are provided in order to expand the memory.
When the expansion memory board 15 is selectively attached to the expansion slot 17 of the above, even if an empty address occurs in the middle of the entire expansion memory area depending on the IC memory mounting state of the expansion memory board 15, Corresponding to the IC memory 29 mounted on the expansion memory board 15 mounted in the first and second expansion slots 16 and 17 by a simple operation of simply switching between closing and opening of the short pins p1 to p5 The addresses of the extended memory area can be made continuous.

Therefore, a program for skipping to the address where the IC memory 29 is mounted every time a process for accessing the memory area of the vacant address occurs is not required, so that the program is simplified and the processing speed is high. Can be realized.

Further, since the expansion memory boards 15a and 15b having different storage capacities can be used in common to the expansion slots 16 and 17, there is no mounting error and it is necessary to prepare the expansion memory board exclusively for each expansion slot. Without
Since the program is simplified, the cost can be reduced.

The present invention is not limited to the first embodiment. For example, in the first embodiment, the first to third signal switching units 28a to 28c are connected to the short pin p1.
.. p5, the present invention is not limited to this, and may be a switch or the like that can switch the connection destination of the signal line with a simple operation.

In the first embodiment, the storage capacity of the IC memory 29 mounted on the expansion memory board 15 is 0.
Although an electronic device capable of expanding the memory to a maximum of 2 MB in a unit of 5 MB is shown as 5 MB, for example, by mounting an IC memory of 1 MB on the expansion memory board 15, a memory of a maximum of 4 MB in a unit of 1 MB is shown. It is also possible to provide an electronic device that can be expanded.

By the way, in the first embodiment, two I
Although the case where the expansion memory board 15 having the C memory mounting portions 27a and 27b is used is shown, the present invention can be applied to the expansion memory board having three or more IC memory mounting portions.

Therefore, next, n (n ≧ 3) or more memory mounting portions M1 and M for detachably mounting the IC memory 29 are mounted.
2, M3, M4, ... Mn and an expansion memory board 60 having a connector portion 61 with an expansion slot,
The first and second expansion slots 71 and 72 to which the connector portion 61 of the expansion memory board 60 is detachably attached
And the first to n-th chip select signals CS1 to CSn corresponding to the respective IC memories 29 mounted in the n IC memory mounting portions M1 to Mn of the expansion memory board mounted in the first expansion slot 71. And n of the expansion memory board mounted in the second expansion slot 72.
The (n + 1) th to 2nd corresponding to the respective IC memories 29 mounted in the individual IC memory mounting portions M1 to Mn.
n chip select signals CSn + 1 to CS2n are selectively transmitted, and the transmitted chip select signals CS1 to CS2n
A second embodiment in which the present invention is applied to a memory expandable electronic device having a central processing means for accessing the IC memory 29 corresponding to 2n will be described.

The schematic structure of the electronic apparatus according to the second embodiment is, as shown in FIG. 7, replaced with first and second expansion slots 16 and 17, and first and second expansion slots 71 and 72. Since the second embodiment is the same as the first embodiment except that is mounted, the same parts as those in FIG.
The description is omitted.

FIG. 8 is a schematic circuit diagram of the expansion memory board 60. The expansion memory board 60 has a connector portion 61 with an expansion slot, which has input terminals e1 to en for the first to nth chip select signals CS1 to CSn and an nth terminal.
+1 to 2n chip select signals CSn + 1 to CS2n
Input terminals f1 to fn and first to nth signal output terminals g1 to gn are provided.

Then, the first chip select signal CS1
The input terminal e1 of is directly connected to the first memory mounting portion M1 on the expansion memory board 60.

The input terminal e2 of the second chip select signal CS2 is attached to the second memory on the expansion memory board 60 through the common terminal [c] -0 terminal [0] of the first signal switching section q1. It is connected to the section M2 and is also connected to the first signal output terminal g1 via the common terminal [c] -1 terminal [1] of the signal switching section q1.

The input terminal e3 of the third chip select signal CS3 is attached to the third memory on the expansion memory board 60 via the common terminal [c] -0 terminal [0] of the second signal switching section q2. Is connected to the first signal output terminal g1 via the common terminal [c] -1 terminal [1] of the signal switching unit q2, and is also connected to the common terminal [1] of the signal switching unit q2. c] -2 terminal [2] is connected to the second signal output terminal g2.

The input terminal e4 of the fourth chip select signal CS4 is attached to the fourth memory on the expansion memory board 60 via the common terminal [c] -0 terminal [0] of the third signal switching section q3. The first signal output terminals g1 to g3 connected to the section M4 and via the common terminal [c] -first terminal [1] to third terminal [3] of the signal switching section q3, respectively.
Is connected to the signal output terminal g3.

The input terminal en of the nth chip select signal CSn is the expansion memory board 60 via the common terminal [c] -0 terminal [0] of the mth (m = n-1) th signal switching section qm. The first signal output terminal is connected to the upper n-th memory mounting section Mn and also via the common terminal [c] -first terminal [1] to m-th terminal [m] of the signal switching section qm. It is connected to the g1 to m-th signal output terminals gm (not shown).

Although not shown, the signal switching sections q4 to qk-1 are connected in common from the input terminal e5 for the fifth chip select signal CS5 to the input terminal em for the mth chip select signal CSm. Terminal [c] -No. 0 terminal [0]
Through the memory mounting unit M5 on the expansion memory board 60
To Mm in a one-to-one connection, and the signal switching unit q
4 to qk-1 common terminal [c] -No. 1 terminal [1] to m-1
The first signal output terminal g1 to the (m-1) th signal output terminal gk-1 are connected through the number terminals [m-1].

Common terminal [c] of each signal switching section q1 to qm
And terminals 0 to m [0] to [m] are connected by inserting short pins. here,
The signal switching units q1 to qm are connected to the input terminals e2 to en for the second to nth chip select signals CS2 to CSn and the first to the first terminals, respectively.
To m-th signal output terminals g1 to gm can be connected without changing the order of signals, and function as a first signal switching unit.

On the other hand, the (n + 1) th chip select signal CS
The n + 1 input terminal f1 is connected to the first signal output terminal g via the common terminal [c] -0th terminal [0] of the nth signal switching unit r1.
1 and the second signal output terminal g2 to the nth signal output terminal via the common terminal [c] -first terminal [1] to m-th terminal [m] of the signal switching unit r1. gn
It is connected to the.

The input terminal f2 of the (n + 2) th chip select signal CSn + 2 is connected to the second signal output terminal g through the common terminal [c] -0 terminal [0] of the (n + 1) th signal switching section r2.
The second signal output terminal g3 to the nth signal output terminal are connected to the second signal output unit r2 via the common terminal [c] -the second terminal [2] to the mth terminal [m] of the signal switching unit r2. gn
It is connected to the.

The input terminal f3 of the (n + 3) th chip select signal CSn + 3 is connected to the third signal output terminal g through the common terminal [c] -0 terminal [0] of the (n + 2) th signal switching section r3.
3, and the fourth signal output terminal g4 to the nth signal output terminal via the common terminal [c] -third terminal [3] to the mth terminal [m] of the signal switching unit r3, respectively. gn
It is connected to the.

The input terminal f4 of the (n + 4) th chip select signal CSn + 4 is connected to the fourth signal output terminal g through the common terminal [c] -0 terminal [0] of the (n + 3) th signal switching section r4.
The fourth signal output terminal g5 (not shown) to the n-th terminal via the common terminal [c] -4th terminal [4] to the mth terminal [m] of the signal switching unit r4. Is connected to the signal output terminal gn.

The input terminal fn of the 2n-th chip select signal CS2n is directly connected to the n-th signal output terminal gn.

Although not shown, the signal switching unit r5 also operates from the n + 5th chip select signal CSn + 5 input terminal f5 to the 2n-1th chip select signal CS2n-1 input terminal fm. ~ Rk-1 common terminal [c]-
It is connected to the fifth signal output terminal g5 to the m-th signal output terminal gm via the 0th terminal [0] in a one-to-one correspondence, and
Connected to the sixth signal output terminal g6 to the nth signal output terminal gn through the common terminals [c] -5th terminal [5] to mth terminal [m] of the signal switching units r5 to rk-1, respectively. Has been done.

Common terminal [c] of each signal switching section r1 to rm
And terminals 0 to m [0] to [m] are connected by inserting short pins. here,
Each of the signal switching units r1 to rm has an input terminal f for the n + 1th to 2n-1th chip select signals CSn + 1 to CS2n-1.
2 to fm and the second to nth signal output terminals g2 to gn can be connected without changing the order of signals, and function as second signal switching means.

FIG. 9 is a circuit diagram of a main part. Between the CPU 11 and the first expansion slot 71, the first to n-th chip select signals CS1 to CSn and the (n + 1) th to 2nth chips are selected.
Of the chip select signals CSn + 1 to cs2n are connected.

The first expansion slot 71 is inserted into the insertion port of the connector section 61 of the expansion memory board 60 in a detachable manner, and the first to nth expansion memory boards 60 are inserted.
Output terminals h1 to hn for the first to n-th chip select signals CS1 to CSn are provided so as to face the chip select signal input terminals e1 to en, and n + 1 to 2n chip select signal input terminals f1 to fn are provided. To the n + 1 to 2n chip select signals CSn +.
Output terminals j1 to jn of 1 to CS2n are provided. Also,
Similarly, the extension memory board 60 is provided with first to nth signal input terminals k1 to kn facing the first to nth signal output terminals g1 to gn.

On the other hand, the second expansion slot 72 is inserted into the connector portion 61 of the expansion memory board 60 to which the connector portion 61 is detachably attached, and the first to nth expansion memory boards 60 are inserted.
The chip select signal input terminals e1 to en are provided with first to nth signal output terminals s1 to sn.

The signal input terminals k1 to kn in the first expansion slot 71 and the signal output terminals s1 to sn in the second expansion slot 72 are connected to the signal line 8 respectively.
1 to 8n connect one to one.

In the second embodiment constructed as described above, the signal switching parts q1 to qm of the expansion memory board 60 mounted in the second expansion memory slit 72 are respectively connected to the common terminals [c] and 0. Connect it to the No. terminal [0] with a short pin. In addition, the corresponding memory mounting portions M1 to Mn
The signal switching parts q1 to qm interposed in the signal lines to which the IC memory 29 is not attached do not necessarily have to connect between the common terminal [c] and the 0th terminal [0].

On the other hand, the signal switching parts q1 to q of the expansion memory board 60 mounted in the first expansion memory slit 71.
m and r1 to rm are the expansion memory boards 60, respectively.
The switching operation may be performed as follows depending on the condition of the IC memory 29 mounted on the.

For example, only the first memory mounting section M1 has I
When the expansion memory board 60 on which the C memory 29 is mounted is installed in the first expansion slot 71, the signal input terminal e
2 to en are respectively connected to the signal output terminals g1 to gk,
In addition, the signal switching units q1 to qm and r1 to rm are switched to connect the signal input terminal f1 to the signal output terminal gn.

By doing so, the first chip select signal CS1 accesses the IC memory 29 mounted in the first memory mounting section M1 of the expansion memory board 60 mounted in the first expansion slot 71. In addition, the second to n + 1th chip select signals CS2 to CSn + 1 are transmitted to the expansion memory board 6 mounted in the second expansion slot 72.
The IC memory 29 mounted in each of the first to nth memory mounting units M1 to Mn of 0 is accessed. Therefore, the addresses of the expansion memory areas corresponding to the IC memory 29 mounted on the expansion memory board 60 mounted in the first and second expansion slots 71 and 72 can be made continuous.

When the expansion memory board 60 in which the IC memory 29 is mounted on the first memory mounting section M1 and the second memory mounting section M2 is mounted on the first expansion slot 71, the signal input terminal e3 To en are respectively connected to the signal output terminals g1 to gk-1 and the signal input terminals f1 and f2 are respectively connected to the signal output terminals gm and gn, and the signal switching portions q1 to qm and r1 to rm are switched. .

As a result, the first chip select signal CS1 and the second chip select signal CS2 are
The IC memories 29 mounted in the first memory mounting section M1 and the second memory mounting section M2 of the expansion memory board 60 mounted in the first expansion slot 71 are accessed. In addition, the third to n + 2th chip select signals CS
2 to CSn + 2 are the first to n-th memory mounting portions M of the expansion memory board 60 mounted in the second expansion slot 72.
The IC memories 29 mounted in 1 to Mn are accessed. Therefore, the addresses of the expansion memory areas corresponding to the IC memories 29 mounted on the expansion memory boards 60 mounted in the first and second expansion slots 71 and 72 can be made continuous.

As described above, also in the second embodiment, when the expansion memory board 60 is selectively attached to the first expansion slot 71 and the second expansion slot 72 in order to expand the memory, the expansion is performed. Even if an empty address occurs in the middle of the entire extended memory area depending on the IC memory mounting state of the memory board 60, a simple switching operation of the signal switching units q1 to qn and r1 to rn provided on the extended memory board 60. By the first and second expansion slots 71, 7
IC mounted on the extended memory board 60 mounted on
The addresses of the extended memory area corresponding to the memory 29 can be made continuous. Therefore, the same effect as that of the first embodiment can be obtained.

[0083]

As described in detail above, according to the present invention, the IC memory is not mounted on at least one of all the memory mounting portions of the expansion memory boat mounted in the first expansion slot, When a vacant address is generated in the middle of the entire expansion memory area, the expansion corresponding to the IC memory mounted on the expansion memory board mounted in the first and second expansion slots is performed by a simple switching operation of the chip select signal. It is possible to provide an electronic device capable of expanding a memory in which addresses of memory areas can be made continuous and a program can be simplified and a processing speed can be increased.

[Brief description of drawings]

FIG. 1 is a schematic block configuration diagram of an electronic device according to a first embodiment of the invention.

FIG. 2 is a schematic circuit diagram of an extended memory board in the embodiment.

FIG. 3 is a main part circuit diagram of the embodiment.

FIG. 4 is a state diagram when 1 MB is expanded in the embodiment.

FIG. 5 is a state diagram when 1.5 MB is expanded in the embodiment.

FIG. 6 is a state diagram at the time of expanding 2 MB in the embodiment.

FIG. 7 is a schematic block configuration diagram of an electronic device according to a second embodiment of the present invention.

FIG. 8 is a schematic circuit diagram of an extended memory board in the embodiment.

FIG. 9 is a circuit diagram of a main part of the embodiment.

FIG. 10 is a schematic circuit diagram of an extended memory board in a conventional example.

FIG. 11 is a circuit diagram of a main part of a conventional example.

FIG. 12 is a diagram showing a memory map of a conventional electronic device.

[Explanation of symbols]

11 ... CPU (central processing unit) 15 ... Expansion memory board 16 ... First expansion slot 17 ... Second expansion slot 21-24 ... First to fourth chip select signal input terminals 25, 26 ... First and first 2nd signal output end 31-34 ... 1st-4th chip select signal output end 35, 36 ... 1st, 2nd signal input end 41-44 ... 1st-4th signal output end 51, 52 ... Signal lines 27a, 27b ... First and second memory mounting sections 28a-28c ... First to third signal switching section 29 ... IC memories p1 to p5 ... Short pins 60 ... Expansion memory board 71 ... First expansion slot 72 ... 2nd expansion slot e1-en ... 1st thru | or nth chip select signal input terminal f1-fn ... n + 1 thru | or 2n chip select signal input terminal g1-gn ... 1st thru | or nth signal output terminal h ... hn ... 1st to n-th chip select signal output terminals j1 to jn ... n + 1 to 2n chip select signal output terminals k1 to kn ... 1st to nth signal input terminals s1 to sn ... 1st to 1st n signal output terminal

Claims (2)

[Claims] 1. An extension memory board having n (n ≧ 2) IC memory mounting portions for detachably mounting an IC memory and a connector portion of an extension slot, and a connector portion of the extension memory board is detachable. First and second expansion slots attached to the first expansion slot, and first to second corresponding to the respective IC memories mounted on the n IC memory mounting portions of the expansion memory board attached to the first expansion slot. n chip select signals and n + 1 to 2n chip select signals respectively corresponding to the IC memories mounted in the n IC memory mounting portions of the expansion memory board mounted in the second expansion slot. And a central processing means for selectively transmitting and accessing the IC memory corresponding to the transmitted chip select signal. In the memory expandable electronic device according to claim 1, the expansion memory board is provided with the first connector on the connector part.
To the nth chip select signal input terminals to which the chip select signals are inputted respectively,
+1 to 2n chip select signals are respectively input, and n + 1 to 2n chip select signal input terminals and 1st to nth signal output terminals are provided, and the 1st to nth chip select signal inputs are provided. The terminals and the respective IC memory mounting parts are connected in a one-to-one relationship, and the second to nth chip select signal input terminals and the first
To the (n-1) th signal output terminals can be connected by the first signal switching means without changing the order of the signals, and the (n + 1) th to 2nth chip select signal input terminals and the first to the nth. The signal output terminals are connected in a one-to-one relationship, and the n + 1th to 2n-1th chip select signal input terminals and the second to nth signal output terminals are connected to each other by a second signal switching means. Connection is possible without changing the order, and the first expansion slot faces the first to nth chip select signal input terminals of the expansion memory board and is sent from the central processing means to the first to nth. Output terminals for the chip select signals are provided, and the (n + 1) th to 2nth output terminals are sent from the central processing means so as to face the (n + 1) th to 2nth chip select signal input terminals. An output terminal for a chip select signal is provided, and the first to nth
First to nth signal input terminals are provided so as to face the signal output terminals of the first to nth chip select signal input terminals of the extension memory board. To nth signal output terminals are provided, and the first to nth signal input terminals in the first expansion slot are connected to the first to nth in the second expansion slot.
A memory expandable electronic device, characterized in that it is connected to each of the signal output terminals of 1: 1. 2. An expansion memory board having a pair of IC memory mounting parts for detachably mounting an IC memory and a connector part of an expansion slot, and first and second connector parts of the expansion memory board to which the connector part is detachably mounted. Memory expansion having a second expansion slot and central processing means for selectively transmitting the first to fourth chip select signals and accessing the IC memory corresponding to the transmitted chip select signals In a possible electronic device, the expansion memory board is provided with first to fourth chip select signal input terminals and first and second signal output terminals in the connector portion, and the first chip select signal input is provided. The terminal is connected to one of the IC memory mounting parts, and the second chip select signal input terminal is selectively connected to the other IC memory by the first signal switching part. Connection part and the first signal output terminal, and the third chip select signal input terminal is selectively connected to the first signal output terminal and the second signal output terminal by a second signal switching part. And an input terminal for the fourth chip select signal is selectively connected to the second signal output terminal by a third signal switching unit, the first expansion slot is the first expansion slot of the expansion memory board. To output terminals for outputting the first to fourth chip select signals sent from the central processing means, facing the fourth to fourth chip select signal input terminals, and facing to the first and second signal output terminals. First and second signal input terminals are provided, and the second expansion slot faces the first and second chip select signal input terminals of the expansion memory board, and first and second signal output terminals. And the first Connecting the first signal input terminal in the second expansion slot and the first signal output terminal in the second expansion slot, and the second signal input terminal in the first expansion slot and the second expansion slot. And a second signal output terminal according to the first aspect of the present invention.