JPH0895751A - Fifo memory - Google Patents

Abstract

PURPOSE: To initiating an efficient interruption when the FIFO memory is used for the transmitting and receiving buffer of a serial interface the and to easily make a serial communication based upon word quantity protocol. CONSTITUTION: The word quantity flag control part 105 of the FIFO memory 204 consists of a write painter which stores the RAM address of write data, a read pointer 104 which stores the RAM address of read data, a subtracter 107 which calculates the number of data words stored in the memory 204 from the write pointer 103 and read pointer 104, a word quantity pointer 101 which can set an optional value within the range of the memory capacity, and a comparator which compares the number of the data word stored in the memory with the number of words set in the word quantity pointer 101 and asserts a word quantity flag output when the number of data words stored in the memory is larger than the number of words set in the word quantity pointer.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a first-in first-out (FIFO) memory, and more particularly to a FIFO.
The present invention relates to a method for issuing an efficient interrupt and easily performing serial communication using a word number control protocol when an O memory is used as a send / receive buffer of a serial interface.

[0002]

2. Description of the Related Art Conventionally, in a FIFO memory, depending on the number of data words stored therein, EMPTY (asserted when the number of words is 0), FULL (asserted when the number of words is full of memory capacity), and HALF FULL ( Various flags such as asserted when the number of words is more than half the memory capacity), ALMOST (asserted before the number of 16 words before EMPTY, FULL are satisfied) are output. However, since the value of the number of words is fixed for each flag, for example, when the FIFO memory is used as the send / receive buffer of the serial interface, issuing an efficient interrupt, and
It was difficult to perform serial communication using the word number control protocol.

[0003]

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention
When the FO memory is used for the send / receive buffer of the serial interface, it is stored in the memory in order to issue an efficient interrupt and to facilitate serial communication by the word number control protocol. To provide a FIFO memory in which the word count flag output is asserted when the number of data words present is equal to or larger than the number of words set in the word count pointer that can set an arbitrary value within the range of the memory capacity.

[0004]

In order to solve the above-mentioned problems, the present invention provides a word pointer control unit of a FIFO memory with a write pointer for storing a RAM address of write data and a read pointer for storing a RAM address of read data. , A subtractor that calculates the number of data words stored in the memory from the write pointer and the read pointer, a word number pointer that can set an arbitrary value within the range of the memory capacity,
Also, the number of words set in the word count pointer is compared with the number of data words stored in the memory, and if the number of data words stored in the memory is greater than or equal to the number of words set in the word count pointer, the word count flag is compared. Provide a comparator that asserts the output.

[0005]

By comparing the number of data words accumulated in the memory calculated from the write pointer and the read pointer with the number of words set in the word number pointer by the comparator, the number of data words accumulated in the memory becomes the word number pointer. If the number of words is equal to or more than the set number of words, an asserted word number flag output is obtained.

[0006]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to FIGS.

First, FIG. 1 shows a configuration example of a FIFO memory. The FIFO memory includes a word number pointer 101, a write pointer 103, a read pointer 104, a word number flag control unit 105, a word number flag output 112, an arbiter 114, and RA.
It is composed of an M117, a FIFO read / write data register 123 and the like. The word number pointer 112 can set an arbitrary value within the range of the memory capacity. The write pointer 103 stores the RAM address of write data, and the read pointer 104 stores the RAM address of read data. The word count flag control unit 105 includes a memory capacity word count 106, a subtractor 107, an adder 108, a pointer code detector 109,
It is composed of a multiplexer 110 and a comparator 111. Write pointer 103 and read pointer 1
04 constitutes the address pointer of the circular buffer. The pointer code detector 109 uses the write pointer 10
3 and the read pointer 104 are in the same circle of the circular address, or the write pointer 103 is in the circle one ahead of the read pointer 104. When the write pointer 103 and the read pointer 104 are in the same circle of the circular address, the number of data words accumulated in the memory is "write pointer 103"-
It is the "read pointer 104" and the write pointer 10
When 3 is one round ahead of the read pointer 104, the number of data words stored in the memory is "memory capacity word number 106" + "write pointer 103"-"read pointer 104". Thus, the number of data words stored in the memory is output from the multiplexer 110.
The word number pointer 101 and the number of data words stored in the memory, which is the output of the multiplexer 110, are input to the comparator 111. If the number of data words stored in the memory is greater than or equal to the word number pointer 101, the number of words Flag output 112 is asserted. As mentioned above,
It is possible to configure a FIFO memory in which the word count flag output is asserted when the number of data words stored in the memory is equal to or larger than the number of words set in the word count pointer.

FIG. 2 shows an example in which a FIFO memory is used as a transmission / reception buffer of a serial interface. Consider a case where the CPU 201 receives serial data of the word number control protocol from the data transmission / reception device 205. The data block structure of the word number control protocol is shown in FIG. In this case, the CPU 201 reads the first word and sets it to the word number pointer of the FIFO memory. The FIFO memory asserts the word number flag output after buffering N words. The CPU 201 detects the interrupt and reads the data from the FIFO memory. Thus, it is possible to easily perform serial communication by the word number control protocol.

[0009]

According to the present invention, when the FIFO memory is used as the send / receive buffer of the serial interface, it is possible to issue an efficient interrupt and easily perform serial communication by the word number control protocol. .

[Brief description of drawings]

FIG. 1 is a block diagram of a FIFO memory.

FIG. 2 is a block diagram of an example in which a FIFO memory is used as a transmission / reception buffer of a serial interface.

FIG. 3 is an explanatory diagram of a data block configuration of a word number control protocol.

[Explanation of symbols]

101 ... word number pointer, 102 ... word number pointer read /
Write data, 103 ... Write pointer, 104 ... Read pointer, 105 ... Word number flag control unit.

Claims (1)

[Claims] 1. A FIF having a word number pointer capable of setting an arbitrary value within a memory capacity range and a word number flag output.
In an O type memory device and its control circuit, a FIFO memory wherein a word count flag output is asserted when the number of data words stored in the memory is equal to or greater than the number of words set in the word count pointer. .