JPH089408A - Chrominance signal processor - Google Patents

Abstract

PURPOSE:To provide a chrominance signal processor for which the hardware amount of an interpolating filter is decreased by widening the band of a chrominance signal. CONSTITUTION:Selectors 111 and 112 switch multiplication coefficients to be inputted to multipliers 108 and 109 corresponding to an output 105 (0, 1 or 2) of a ternary counter 107 synchronized with a clock 104 having the double frequency of a system clock. When the output 105 of the counter is '0', a1 and b1 are selected, when it is '1' a and b are selected and when it is '2' a3 and b3 are selected. Then, those outputs are added by an adder 110 and RGB signals are dot-sequetially generated. When the attention is paid on the R component in this case, R0 and R1 exist in an output 106 of a matrix arithmetic circuit but R2 is thinned and does not exist.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a color signal processing device for processing a video signal from an image pickup device and outputting a color signal.

[0002]

2. Description of the Related Art In a color signal processing apparatus, in so-called three-color processing, signal components W _r and G arranged as shown in FIG.
_b , _Gr and _Wb are synchronized to obtain the following signal components:

[0003] _{Y L = W r + G b} = G r + W b C R = W r -G b C b = W b -G r here, 3 of red (R), green (G), and blue (B) For the primary colors, W _r = 2R + G + B W _b = R + G + 2B G _r = R + 2G G _b = 2G + B.

These signal components are

[0005]

[Equation 1]

RG which is matrix-operated and dot-sequentialized as
A B signal is generated.

In order to generate the dot-sequential RGB signal, a matrix operation circuit as shown in FIG. 7A has been conventionally used. In this circuit, the system clock M
Output 70 of ternary counter 707 synchronized with CLK704
The inputs of the selectors 711 and 712 are switched according to 5, and an R component is generated when the output 705 of the counter 707 is “0”, a G component is generated when the output 705 is “1”, and a B component is generated when the output 705 is “2”. . A time chart of the above operation is shown in FIG. Here, focusing on the R component, although R ₀ exists at the output 706 of the matrix operation circuit,
₁ and R ₂ are thinned out and do not exist. Thus R
Each component of the GB signal has only one pixel out of three pixels,
It is thinned to 1/3.

In the so-called four-color processing, the signal components W _r , G _b , G _r , W _b arranged as shown in FIG. 6 are synchronized,

[0009]

[Equation 2]

RG which is matrix-operated and dot-sequentialized as
B signal is generated.

In order to generate the dot-sequential RGB signal, a matrix operation circuit as shown in FIG. 8A has been conventionally used. In this circuit, the system clock M
Output 80 of ternary counter 808 synchronized with CLK805
The inputs of the selectors 814 to 817 are switched according to 6, and an R component is generated when the output 806 of the counter 808 is “0”, a G component is generated when the output 806 is “1”, and a B component is generated when the output 806 is “2”. . A time chart of the above operation is shown in FIG. Here, focusing on the R component, although R ₀ exists in the output 807 of the matrix operation circuit,
₁ and R ₂ are thinned out and do not exist. Thus R
Each component of the GB signal has only one pixel out of three pixels,
It is thinned to 1/3.

[0012]

In the above conventional example, RG is used.
Since each component of the B signal actually has only one pixel for every three pixels, it is necessary to generate the other two pixels by interpolation when the respective components of the RGB signal which are dot-sequential are synchronized. is there. Therefore, there are problems that the band of the color signal is not sufficient and that the configuration of the interpolation filter becomes complicated.

The present invention has been made in order to solve the problems of the above-mentioned conventional example, and the RG is performed in a dot-sequential manner by matrix operation.
When a B signal is generated, an oversampling method is used to artificially increase the number of pixels, thereby broadening the band of the color signal and reducing the hardware amount of the interpolation filter. The purpose is to provide.

[0014]

The present invention is constructed as follows.

(1) A matrix operation circuit that separates a digitized video signal into a luminance signal and a color signal, and dot-sequentially generates an RGB signal from the signals that are synchronized by a color demodulation circuit. A color signal processing device comprising a matrix calculation circuit having means for switching a coefficient of matrix calculation by a signal having a frequency twice the sampling frequency.

(2) The color signal processing device according to (1), further comprising an interpolation filter for interpolating the signals thinned out by the matrix operation circuit by the signals generated by the matrix operation circuit.

(3) The interpolation filter inputs either the processed signal or the unprocessed signal to the RGB signal generated in a dot-sequential manner by the matrix operation circuit, and inputs this signal to the sampling cycle of the RGB signal. And a second delay means for inputting the output of the first delay means and delaying and outputting the output by the sampling cycle of the RGB signals, and a second delay means for outputting the output. The third delay means for inputting the output of the delay means and delaying and outputting the output by the sampling period of the RGB signals, the input signal of the first delay means and the output signal of the third delay means, The color signal processing device according to (2), further comprising: means for generating a signal that interpolates a signal thinned out by the matrix operation circuit.

[0018]

According to the present invention, by virtue of the configuration as described in (1) above, only one of the three pixels is thinned out.

With the above-mentioned configuration (2), a color signal in which the thinned pixels are interpolated is generated.

Further, with the above configuration (3), color signals are generated by interpolating the thinned pixels using the signals before and after the thinned pixels.

[0021]

EXAMPLES The present invention will be described below based on examples.

(Embodiment 1) FIG. 1 is a block diagram of a color signal processing apparatus according to a first embodiment. The first embodiment is an embodiment in the case of so-called three-color processing. In this figure, the output signal of the image pickup element 201 is the correlation double sampling circuit 2
Correlation double sampling is performed in 02, and the automatic gain adjustment circuit 2
In 03, automatic gain adjustment is performed, and in the A / D converter 204, analog-digital conversion (A / D conversion) is performed to obtain a digital signal, and then in a Y / C separator 205, a luminance signal and a chrominance signal are separated (Y / C separation).

The separated luminance signal is carrier-removed and the optical filter characteristic is corrected by the low-pass filter 206, and the aperture is corrected by the aperture correction circuit 207. Then, the gamma correction circuit 208 performs gamma correction, the blanking addition circuit 209 adds blanking, and the D / A converter 210 performs digital-analog conversion (D / A conversion) to output an analog luminance signal.

On the other hand, in the color signal, the signal components W _r , G _b , G _r , and W _b arranged as shown in FIG. 6 are obtained by the color demodulation circuit 211 as the following synchronized signal components.

[0025] Each signal components _{Y L = W r + G b} = G r + W b C R = W r -G b C B = W b -G r These Y _L, C _R, C _B is low-pass The carrier is suppressed by the filter 212, and the matrix calculation circuit 21
RGB which is dot-sequentialized by matrix calculation in 3
A signal is generated.

FIG. 2A shows the internal circuit of the matrix operation circuit 213. In this circuit, the selectors 111 and 11
2 is a ternary counter 10 synchronized with a clock 2MCLK 104 having a frequency twice that of the system clock MCLK.
The multiplier 10 according to the output 105 (0, 1 or 2) of 7
The multiplication coefficient input to 8, 109 is switched. Counter when the output 105 is "0" is selected _{a 1, b 1, "1} " a 2, b 2 is selected when the, a _3, b ₃ is selected when "2" . Then, the signals are added by the adder 110, and the RGB signals are dot-sequentially generated at the output 106 of the matrix operation circuit. A time chart of the above operation is shown in FIG. Here, focusing on the R component, R ₀ , R at the output 106 of the matrix calculation circuit 213
₁ is present, but R ₂ is decimated and is absent.

As described above, since each pixel of the RGB signal is thinned out by one pixel out of three pixels, the white balance adjustment circuit 214 performs white balance adjustment and the gamma correction circuit 215 performs gamma correction, and then the interpolation filter. 21
6 must be interpolated.

FIG. 3A shows the internal circuit of the interpolation filter 216. In this circuit, the gamma correction circuit 215
The signal 301 that has been gamma-corrected by the system clock MC
Clock 2MCLK 313 having twice the frequency of LK
Are delayed by the delay units 314 to 316 synchronized with. Input 3
01 and the output 304 of the delay device 316 are the multiplier 31
After being multiplied by 0.5 in 8, 319, the sum is added by the adder 320. Output 302 of delay device 314, delay device 315
Output 303 and output 327 of the adder 320 are sent to the selectors 321 to 323. In the selectors 321 to 323, the ternary counter 317 synchronized with the clock 2MCLK 313 having a frequency twice that of the system clock MCLK.
The input is switched according to the output 311 (0, 1 or 2) of the delay units 324, 326, 305, 306,
The R, G, and B components are always output to 307, respectively. Then, the delay devices 324 to 326 generate the synchronized RGB signals 308 to 310 in synchronization with MCLK. A time chart of the above operation is shown in FIG. In this example, the R component R ₂ decimated in the matrix calculation circuit 213 is interpolated in the form of (R ₁ + R ₃ ) / 2.

The RGB signals subjected to the interpolation process and the synchronization by the interpolation filter 216 become the color difference signals RY and BY in the matrix calculation circuit 217. Further, the hue correction circuit 218 performs hue correction using a linear matrix. Next, the modulation circuit 219 performs modulation and burst addition, and the D / A converter 220 converts the analog signal into an analog signal, which becomes an output color signal.

(Second Embodiment) FIG. 4 is a block diagram of a color signal processing apparatus according to the second embodiment. The second embodiment is an embodiment in the case of so-called four-color processing. In this figure, the output signal of the image sensor 501 is the correlated double sampling circuit 5
Correlated double sampling is performed in 02, and the automatic gain adjustment circuit 5
In 03, automatic gain adjustment is performed, and in A / D converter 504, A / D
After being D-converted into a digital signal, it is Y / C separated by a Y / C separator 505.

The separated luminance signal is subjected to carrier removal and optical filter characteristic correction by a low pass filter 506, and the aperture is corrected by an aperture correction circuit 507. Then, the gamma correction circuit 508 performs gamma correction, the blanking addition circuit 509 performs blanking addition, and the D / A converter 510 performs D / A conversion to output an analog luminance signal.

On the other hand, in the color signal, the signal components W _r , G _b , G _r , and W _b arranged as shown in FIG. 6 are synchronized by the color demodulation circuit 511. Carriers of these W _r , G _b , G _r , and W _b are suppressed by the low-pass filter 512, and matrix operation is performed by the matrix operation circuit 513, so that the dot-sequential R is obtained.
A GB signal is generated.

FIG. 5A shows the internal circuit of the matrix operation circuit 513. In this circuit, selectors 414-41
7 is a ternary counter 40 synchronized with a clock 2MCLK 405 having a frequency twice that of the system clock MCLK.
8 according to the output 406 (0, 1 or 2) of the multiplier 40
The multiplication coefficient input to 9 to 412 is switched. When the output 406 of the counter is “0”, a ₁ , b ₁ , c ₁ , d
_{When 1} is selected and is “1”, a ₂ , b ₂ , c ₂ , d ₂
Is selected and when 406 is “2”, a ₃ , b ₃ , c
₃ , ₃ are selected. Then, the RGB signals are added in the adder 413 and dot-sequentially generated at the output 407 of the matrix operation circuit. A time chart of the above operation is shown in FIG. Here, focusing on the R component, R ₀ and R ₁ exist in the output 407 of the matrix operation circuit 513, but R ₂ is thinned out and does not exist.

As described above, since each pixel of the RGB signal is thinned out by one pixel out of three pixels, the white balance adjustment circuit 514 performs white balance adjustment and the gamma correction circuit 515 performs gamma correction, and then the interpolation filter. 51
6 must be interpolated. A circuit similar to that of the first embodiment is used for the interpolation filter.

The RGB signals subjected to the interpolation processing and the synchronization by the interpolation filter 516 become color difference signals RY and BY in the matrix calculation circuit 517. Further, the hue correction circuit 518 corrects the hue by the linear matrix. Next, the modulation circuit 519 performs modulation and burst addition, and the D / A converter 520 converts the analog signal into an analog signal, which becomes an output color signal.

[0036]

According to the present invention, the number of pixels can be increased in a pseudo manner by using the oversampling method when the RGB signals are generated in the dot-sequential manner by the matrix operation, and the thinning-out is performed. When interpolating another pixel, a pixel located very close to the thinned pixel may be used, so that the band of the color signal can be widened and the hardware amount of the interpolation filter can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram of a first embodiment.

FIG. 2 is a circuit configuration diagram and a time chart of the matrix operation circuit according to the first embodiment.

FIG. 3 is a circuit configuration diagram and time chart of the interpolation filter according to the first embodiment.

FIG. 4 is a block diagram of a second embodiment.

FIG. 5 is a circuit configuration diagram and time chart of a matrix operation circuit according to a second embodiment.

FIG. 6 is a layout diagram of signals W _r , G _b , G _r , W _b

FIG. 7 is a circuit configuration diagram and time chart of a matrix operation circuit of Conventional Example 1.

FIG. 8 is a circuit configuration diagram and time chart of a matrix operation circuit of Conventional Example 2.

[Explanation of symbols]

213, 513 matrix operation circuit 216, 516 interpolation filter 104, 313, 405 clock having double frequency of system clock 107, 317, 408 ternary counter 111-112, 414-417 selector 314-316 delay device 320 adder

Claims (3)

[Claims] 1. A matrix operation circuit for separating a digitized video signal into a luminance signal and a color signal, and for generating RGB signals in a dot-sequential manner from the signals synchronized by a color demodulation circuit,
A color signal processing apparatus comprising a matrix calculation circuit having means for switching a coefficient of matrix calculation by a signal having a frequency twice the sampling frequency of an input signal. 2. The color signal processing device according to claim 1, further comprising an interpolation filter for interpolating a signal thinned out by the matrix operation circuit by a signal generated by the matrix operation circuit. 3. The interpolation filter inputs either the processed signal or the unprocessed signal to the RGB signal generated in a dot-sequential manner by the matrix operation circuit, and inputs this signal to the R
A first delay means for delaying and outputting a GB signal sampling period and an output of the first delay means are inputted,
Second delay means for delaying and outputting this by the sampling cycle of the RGB signal and third output for outputting the output of the second delay means after delaying by the sampling cycle of the RGB signal. A delay means and a means for generating a signal for interpolating a signal decimated by a matrix operation circuit by an input signal of the first delay means and an output signal of the third delay means. Item 2. The color signal processing device according to item 2.