JPH0888809A - Non-signal detection circuit - Google Patents

Abstract

PURPOSE: To eliminate erroneous discrimination at the time of nonsignal while maintaining discrimination performance at the time of inputting signals and to change detection sensitivity. CONSTITUTION: The pulse width of input signals is detected based on the clocks of reference signals by a pulse width detection circuit 10 and supplied to a pulse number detection circuit 11 as detection pulses. Thereafter, a detection pulse number present in one cycle period of the reference signals is detected by the pulse number detection means 11 and a detected result is supplied to an up-down counter 12 as pulse signals. The up-down counter 12 switches a counting direction based on the detected result and performs a counting operation, obtained count data are compared with threshold value data 14 by a large/ small comparator 13 and a compared result is outputted. In this case, the value of the up-down counter 12 increases only when pulses correlated to the cycle of the reference signals are inputted and it decreases in the other cases. Thus, by detecting whether or not the value of the up-down counter 12 exceeds a prescribed threshold value, whether or not the input signals are video signals is discriminated without malfunctions.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic device such as a color television receiver capable of inputting a composite signal such as a video signal and a composite video signal, and is particularly used for determining whether or not a video signal is input. Signal detection circuit.

[0002]

2. Description of the Related Art In recent years, television receivers receive broadcasts and display images, as well as image information such as video cassette tape recorders (hereinafter referred to as VTRs), video personal computers, text broadcasts and satellite broadcasts. A function as a display device for displaying is required.

In order to satisfy such demands,
An AV type television receiver (Audio Visual) having a plurality of audio input terminals has been put into practical use. In an AV television receiver, a system generally composed of a VTR is frequently used by users,
In other words, it is essential to switch between the video signal of the input signal and the composite video signal received by using the receiving device provided in the main body, and the input signal is automatically discriminated and the projection mode based on the input signal is obtained. It is desirable to switch and project.

Therefore, in an AV television receiver, for example, when a system is configured by connecting to a VTR, when a reproduced video signal is supplied, a no-signal detection circuit for determining whether or not the video signal is input is provided. Some have been conventionally adopted. As a method of this no-signal detection circuit,
This is a method of counting the number of pulses of the horizontal and vertical synchronizing signals within a fixed time using a counter circuit, and determining whether the counter value is within a predetermined range. This determination result is switched to supply the input signal to the reproduction processing circuit corresponding to the input signal by being supplied to, for example, the switching circuit control means for controlling the switching of the input signal, and the reproduction processing based on the input signal. Is done.

FIG. 8 is a block diagram showing an example of such a conventional no-signal detecting circuit. In FIG.
A pulse width detection circuit 1 is provided in the no-signal detection circuit. The pulse width detection circuit 1 is supplied with an input signal and a reference clock, and the pulse width detection circuit 1 detects the pulse width of the input signal based on the reference clock and converts the detection results into two pulse signals. Output. For example, the pulse width detection circuit 1 outputs the first detection pulse and the second detection pulse when the pulse width of the input signal exceeds two predetermined threshold values (set to 2 μSec and 3 μSec in this example). Generate and correspond to the first and second up counters 2, 3
Each pulse is supplied to (hereinafter referred to as up counters 2 and 3).

The up counters 2 and 3 receive the first and second detection pulses output from the pulse width detection circuit 1 as clock pulses, and use the clocks as counts to output the count data. For example, when the clock pulse which is the first and second detection pulses to be input is input, the count data is increased. Furthermore,
A reference signal is input to the up counters 2 and 3, and the up counters 2 and 3 are reset by the reference signal. Up counter 2,
The respective counter data output from 3 is supplied to the first and second range detection circuits 4 and 5.

A reference signal is supplied to each of the first range detection circuits 4 and 5. The first range detection circuit 4 compares the reference signal with the count data from the up counter 2, detects a range based on two preset level values, and outputs the detection result.

For example, the two level values are set to the threshold value A.
And the threshold value B, and the threshold value A is set to a standard value of −10.
%, On the other hand, when the threshold value B is set to + 10% of the standard value, the first range detection circuit 4 exceeds the threshold value A and exceeds the threshold value immediately before the up counter 2 is reset. When the value B is not exceeded, "H" level (hereinafter,
H level) signal is output. After that, the H level signal is supplied to one input terminal of the NAND circuit 6.

The second range detection circuit 5 compares the reference signal with the count data from the up counter 3, detects a range based on one preset level value, and outputs the detection result.

For example, let the level value be a threshold value C,
If this threshold value C is set to + 20% of the standard value,
The second range detection circuit 4 outputs a signal of "H" level (hereinafter, H level) when the threshold C is not exceeded immediately before the up counter 3 is reset. After that, the H level signal is supplied to the other input terminal of the NAND circuit 6.

The NAND circuit 6 is a circuit configured by combining a well-known NOT circuit and an AND circuit. When the supplied 2 input signals are P and Q, the output is Is denied. In this way, the output of the NAND circuit 6 is output as a determination result of determining whether or not a video signal is input. Thereafter, the result of this determination is supplied to a switching control means (not shown), and switching based on the input signal (hereinafter, mode switching) is performed.

However, in the no-signal detection circuit having such a configuration, the presence or absence of the signal is determined by the total value of the number of pulses of the horizontal and vertical synchronization signals existing in a certain period. Even with random noise other than the frequency component of the horizontal synchronization signal, the signal presence condition may be satisfied, and there is a risk of misjudgment.

In addition, the received signal at the time of tuning operation and the VT
There may be a case where signals having different characteristics of the input signal such as the R reproduction signal are supplied, but in this case, it is necessary to set / change the detection range according to the input signal in order to detect the presence or absence of the input of the video signal. . However, in the conventional technology, it is impossible to change the detection sensitivity according to the difference in the sync separation performance for separating the horizontal and vertical sync signals from the video signal, that is, the detection sensitivity is set according to the difference in the characteristics of the input signal.・ No improvements have been made regarding changes.

[0014]

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention As mentioned above,
In the conventional no-signal detection circuit, since the presence or absence of the signal is determined by the total value of the number of pulses of the horizontal and vertical synchronization signals existing in a certain period, there is a possibility of making an erroneous determination due to an accidental establishment of conditions.
There is also a problem that the detection sensitivity cannot be changed according to the difference in the characteristics of the input signal.

Therefore, the present invention has been made in view of the above problems, and while maintaining the discrimination performance at the time of signal input, it is possible to eliminate the erroneous discrimination at the time of no signal and change the detection sensitivity. For the purpose of providing.

[0016]

A no-signal detection circuit according to the present invention is supplied with an input signal and a reference signal, detects the pulse width of the input signal based on the clock of the reference signal, and outputs the pulse as a detection pulse. A pulse number detection unit that is supplied with a width detection unit, a detection pulse from the pulse width detection unit, and a reference signal, detects the number of detection pulses in one cycle period of the reference signal, and outputs the detection result as a pulse signal. And a means for counting the pulse signal of the detection result by using the reference signal as a clock and outputting count data, and an up-down counter for counting up or down depending on the detection result to generate count data, Comparing means for comparing the count data from the up / down counter with a predetermined threshold value is provided. Based on the comparison result by the determination means that the signal is correlated to the cycle of the reference signal to determine whether it is entered, but provided with the.

[0017]

According to the present invention, the pulse width of the input signal is detected by the pulse width detecting means based on the clock of the reference signal, and is supplied to the pulse number detecting means as a detection pulse. afterwards,
The number-of-pulses detecting means detects the number of detected pulses existing in one cycle period of the reference signal, and supplies the detection result as a pulse signal to the up-down counter. The up / down counter performs a counting operation by switching the counting direction for counting based on the detection result, and the obtained count data is compared with the threshold value by the comparison means and outputs the comparison result. In this case, the value of the up / down counter increases only when a pulse having a correlation with the cycle of the reference signal is input, and decreases otherwise. Therefore, it is possible to determine whether or not the input signal is a video signal, that is, the presence or absence of the input signal, by detecting whether or not the value of the up-down counter exceeds a predetermined threshold value by the determination means. . Therefore, it is possible to determine the presence or absence of the input signal without causing a malfunction. Also, the up / down counter is +1 when counting up, and − when counting down.
Since it is possible to provide a difference in the amount of operation in one counting operation, such as setting to 2, it is possible to easily change the detection sensitivity.

[0018]

EXAMPLES Examples will be described with reference to the drawings. FIG. 1 is a block diagram showing a first embodiment of a no-signal detection circuit according to the present invention.

In FIG. 1, a pulse width detection circuit 10 is provided in the no-signal detection circuit. An input signal and a reference clock are supplied to the pulse width detection circuit 10,
The pulse width detection circuit 10 detects the pulse width of the input signal based on the reference clock, converts the detection result into a pulse signal, and outputs the pulse signal. For example, the pulse width detection circuit 10 uses two predetermined threshold values for the pulse width of the input signal (2 μS as in the conventional example).
ec and set to 3 μSec), a detection pulse is generated, and this detection pulse is supplied to the pulse number detection circuit 11. The pulse width detection circuit 11 has a function of removing noise with a narrow pulse width mixed in the input signal.

A reference signal is supplied to the pulse number detecting means 11, and the pulse number detecting circuit 11 detects the number of the above-mentioned detection pulses in one cycle period of the reference signal. Level signal, otherwise L
Output level signal. The output signal from the pulse number detection circuit 11 is supplied to the up / down counter 12.

A reference signal is also supplied to the up / down counter 12, and the up / down counter 12 uses this reference signal as a clock, and the pulse number detection circuit 1
When the output of 1 is at H level, it counts up, and when it is at L level, it counts down. And
The counted data that has been counted is supplied to the magnitude comparator 13.

For example, the up counter 12 stops counting when it is up-counted and its value is ALL1 and when it is down-counted and its value is ALL0. Also,
The up counter 12 is provided with an overflow / underflow preventing function that restarts counting when the counting direction is switched.

Threshold data 1 is stored in the magnitude comparison circuit 13.
4 is supplied, and the magnitude comparator 13 compares the count data from the up / down counter with the threshold data 14 and outputs the comparison result as a no-signal discrimination result.

FIG. 2 is a block diagram showing a specific example of the pulse number detection circuit shown in FIG.

In FIG. 2, the pulse number detection circuit 11 is provided with an up counter 20 which is a 2-bit counter for counting up the input signal. Up counter 2
As described above, the reference signal and the detection pulse detected by the pulse width detection circuit 10 are supplied to 0, and the reference signal is delayed by the delay circuit 21 as shown in FIG. Is supplied to. on the other hand,
The detection pulse is supplied to one input terminal of the AND circuit 22, and the output Q1 from the up counter 20 is inverted and supplied to the other input terminal of the AND circuit 22. The output of the AND circuit 22 is the up counter 20.
It is supplied to.

The up counter 20 supplies the output Q1 to the AND circuit 22 as shown in FIG.
B output Q0 up / down counter 12 (see FIG. 1)
Then, the number of pulses of the input signal is detected based on the reference signal and is supplied as a detection result.

For example, the up counter 20 is reset with a signal obtained by delaying the reference signal. The up counter 20 prohibits clock input when the count value reaches 2,
Stop counting operation. Therefore, the LSB output Q0 of the up-counter 20 becomes L level when a reference signal is input, becomes H level when the input signal reaches one pulse before the next reference signal arrives, and becomes 2 levels or more when the input signal reaches one pulse.
The operation of returning to the L level is performed again. This output is used to control the switching of the count direction of the up / down counter 12.

Next, the operation of the no-signal detection circuit shown in FIG. 1 will be described in detail with reference to FIG. FIG. 3 is a timing chart for explaining the operation shown in FIG.

Now, it is assumed that a signal is input to the no-signal detection circuit. Then, the input signal is the pulse width detection circuit 10
And the pulse width detection circuit 10 detects the pulse width of the input signal based on the reference clock. In this case, a detection pulse is generated based on a predetermined threshold value and supplied to the pulse number detection circuit 11. For example, in the case of the input signal in this embodiment, the detected detection pulse is as shown in FIG.

After that, the pulse number detection circuit 11 detects the number of the detection pulses supplied in one cycle period of the reference signal. At this time, the pulse number detection circuit 11 outputs an H level signal when this number is 1, and outputs an L level signal otherwise. That is, this is because the operation of the up counter 2 is performed as described in the specific example of the pulse number detection circuit 11 shown in FIG.
The count data counted by 0 (see FIG. 2) has the values shown in FIG. Therefore, as shown in FIG. 3, the LSB output Q0 of the up counter 20 is the up / down counter 12 shown in FIG.
Is supplied to.

After that, the up / down counter 12 uses the reference signal as a clock and performs up-counting when the output of the pulse number detection circuit 11 is at the H level and down-counting when the output is at the L level, so that FIG. Count data can be obtained as shown. After that, this count data is supplied to the magnitude comparator 13,
The magnitude is compared with the preset threshold value data 14.
Therefore, by selecting the period of the reference signal as a value close to the period of the horizontal synchronizing signal of the video signal, it is possible to detect whether or not the input signal has a frequency component of the horizontal synchronizing signal. Can be determined.

FIG. 4 shows a second example of the no-signal detection circuit according to the present invention.
It is a block diagram which shows an Example.

In the circuit configuration shown in FIG. 4, the same components as those shown in FIG. 1 are designated by the same reference numerals and the description thereof will be omitted.

As shown in FIG. 4, in the no-signal detection circuit of this embodiment, the up-down counter 12 (see FIG. 1) used in the first embodiment is provided with the first and second flip-flop circuits. To constitute the up-down counter 30, and further supply the reference clock signal to be supplied to the counter 30 to the first flip-flop circuit at the time of up-counting and to the second flip-flop circuit at the time of down-counting. In addition, a clock switch 31 as a switching means is added. In the present embodiment, for example, when the output signal from the pulse number detection circuit 11 shown in FIG. 4 is supplied to the up / down counter 30, the up / down counter 30 becomes +1 at the time of up-counting and becomes −2 at the time of down-counting. To output the count data. This count data is supplied to the magnitude comparator 13 as in the above embodiment, and the magnitude comparator 13 compares the count data with the threshold data and outputs it as a no-signal detection result. In this way, it is determined whether or not the input signal is a video signal.

Therefore, in this embodiment, the operation amount of the up / down counter 30 is improved as described above so that the position of the clock applied to the up / down counter 30 can be selected. With this configuration, the signal detection sensitivity can be easily changed.

FIG. 5 shows a third example of the no-signal detection circuit according to the present invention.
It is a block diagram which shows an Example.

In the circuit configuration shown in FIG. 5, the same components as those shown in FIG. 1 are designated by the same reference numerals and the description thereof will be omitted.

As shown in FIG. 5, the no-signal detection circuit of this embodiment is configured to supply the logical sum of the reference signal and the delay signal of the input signal as the reference clock supplied by the up / down counter 12. This is an example of making it possible to obtain the count operation amount according to the number of arrivals of the input signal within one cycle of the reference signal.

In FIG. 5, as in the first embodiment, the pulse width detection circuit 10 detects the pulse width of the input signal based on the reference clock and supplies the detected pulse to the pulse number detection circuit 11 and the delay circuit 40. . The delay circuit 40 delays the detection pulse for a predetermined period and supplies it to one input terminal of the OR circuit 41. In the first embodiment, the reference signal is directly supplied to the up / down counter 12, but in this embodiment, the reference signal is supplied to the other input terminal of the OR circuit 41, and
The R circuit 41 supplies the reference signal and the delayed signal obtained by delaying the input signal to the up-down counter 12 with the morale.

Therefore, according to such a configuration, when the pulse number detection circuit 11 detects that the number of detected pulses in one cycle of the reference signal is 0 as shown in FIG. , -1. Further, when 1 is detected, the count data becomes +2, and when the other numbers are n, the count data in the case of n (n ≧ 2) becomes 1-n. in this way,
It is possible to obtain the count operation amount according to the number of arrivals of the input signal within one cycle of the reference signal.

As a result, the presence or absence of the input of the video signal can be discriminated as in the above-mentioned embodiment, and the operation amount of the count can be changed, so that the detection according to the input signal can be effected. Have.

FIG. 7 shows a fourth example of the no-signal detection circuit according to the present invention.
It is a block diagram which shows an Example.

In the circuit configuration shown in FIG. 7, the same components as those shown in FIG. 1 are designated by the same reference numerals and the description thereof will be omitted.

As shown in FIG. 7, in the no-signal detection circuit of this embodiment, the threshold value data 14 of the first embodiment is provided with two threshold values C60 and D61. An RS flip-flop circuit 16 that compares the threshold value C60 and the threshold value D61 with the count data of the up / down counter 12 by two magnitude comparators 50 and 51 and outputs a no-signal detection result according to the comparison result. They are different in that they are set or reset. As a result, it is possible to obtain a determination result having a hysteresis characteristic.

For example, the threshold value C60 and the threshold value D61 are set to have a relationship of (threshold value C)> (threshold value D). The count data from the up / down counter 12 is the size comparators 50 and 51.
Is supplied to each. Then, one size comparator 50
Compares the supplied count data with the threshold value C, and supplies the comparison result to one input terminal of the RS flip-flop circuit 16. The other magnitude comparator 51 compares the supplied count data with the threshold value D61, and the comparison result is inverted by the NOT circuit 15 to obtain the R
The signal is supplied to the other input terminal of the S flip-flop circuit 16. In this case, the RS flip-flop circuit 16 is set when the count value of the up / down counter 12 becomes equal to or larger than the threshold value C, and when the count value becomes equal to or smaller than the threshold value D, RS The flip-flop 16 is set to be reset. This gives R
Since the S flip-flop circuit 16 can output the determination result having the hysteresis characteristic, it becomes possible to more effectively determine the presence or absence of the input of the video signal, and further change the setting of the detection sensitivity according to the input signal. can do.

The no-signal detection circuit according to the present invention is used not only in a television receiver having an input terminal into which a video signal can be input, but also in a tuner capable of receiving a television signal, for example. It may be used in an electronic device such as a VTR provided, and in this case, it is obvious that the presence / absence of a video signal input can be surely determined.

[0047]

As described above, according to the present invention,
By selecting the period of the reference signal as a value close to the period of the horizontal synchronizing signal of the video signal, it is possible to identify the input signal correlated with the horizontal synchronizing signal of the video signal.
False detection due to random noise can be prevented.
Further, since the detection sensitivity can be set or changed in accordance with the video signal discrimination processing, it can be effectively used for applications such as when receiving a television signal and during VTR reproduction, and at the same time, it can be used for input signals. This has the effect that the setting of the detection sensitivity can be changed according to the synchronization separation performance.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of a no-signal detection circuit according to the present invention.

FIG. 2 is a block diagram showing a specific example of the pulse number detection circuit shown in FIG.

FIG. 3 is a timing chart for explaining the operation of the no-signal detection circuit shown in FIG.

FIG. 4 is a block diagram showing a second embodiment of a no-signal detection circuit according to the present invention.

FIG. 5 is a block diagram showing a third embodiment of the no-signal detection circuit according to the present invention.

6 is an explanatory diagram for explaining the operation of the no-signal detection circuit shown in FIG.

FIG. 7 is a block diagram showing a fourth embodiment of the no-signal detection circuit according to the present invention.

FIG. 8 is a block diagram showing an example of a conventional no-signal detection circuit.

[Explanation of symbols]

10 ... Pulse width detection circuit, 11 ... Pulse number detection circuit, 1
2, 30 ... Up-down counter, 13, 50, 51 ...
Large / small comparator, 14, 60, 61 ... Threshold data, 20
... 2 bit up counter, 21, 40 ... delay circuit, 2
2 ... Gate circuit, 31 ... Switching circuit, 15 ... NOT circuit, 16 ... RS flip-flop circuit.

Claims (6)

[Claims] 1. A pulse width detection means, which is supplied with an input signal and a reference signal, detects the pulse width of the input signal based on the clock of the reference signal, and outputs as a detection pulse, and detection from the pulse width detection means. A pulse and a reference signal are supplied, pulse number detection means for detecting the detection pulse number in one cycle period of the reference signal, and outputting the detection result as a pulse signal, and the detection result pulse using the reference signal as a clock A means for counting signals and outputting count data, the up-down counter counting up or down depending on the detection result to generate count data, the count data from the up-down counter, and a predetermined counter The comparison means for comparing with the threshold value is provided, and the cycle of the reference signal is determined based on the comparison result by this comparison means. A no-signal detection circuit comprising: a determination unit that determines whether or not a correlated signal is input. 2. The up / down counter is configured such that a value of count data generated by counting up or down according to the detection result can be set from the outside, and adjustment of detection sensitivity of an input signal and The no-signal detection circuit according to claim 1, wherein the no-signal detection circuit is changeable. 3. The up / down counter is configured by providing two flip-flop circuits, and switching means for switching and supplying a reference signal to these two flip-flop circuits is provided, and the switching means is 2. The no-signal detection circuit according to claim 1, wherein switching control is performed according to a change in the pulse number of the input signal detected by the pulse number detection means. 4. The no-signal detection is performed by providing the comparing means for comparing the count data with the threshold value with binary threshold values of different magnitudes and providing a dead zone between these binary values. The no-signal detection circuit according to claim 1, wherein the determination result of 1 has a hysteresis characteristic. 5. The comparison means comprises a plurality of magnitude comparisons provided to compare the count data with two thresholds of different magnitudes, and an inverting circuit for inverting and outputting the comparison result of one magnitude comparator. 5. A flip-flop circuit which is reset by the output of the inverting circuit and which is set when the output of the other magnitude comparator is supplied and which outputs a no-signal determination result. No signal detection circuit. 6. The no-signal detection circuit according to claim 5, wherein the threshold value is configured to be set from the outside, and a no-signal detection determination condition can be changed.