GB2238443A

GB2238443A - Video synchronising signal detection

Info

Publication number: GB2238443A
Application number: GB9007068A
Authority: GB
Inventors: Cheol-Min Kim
Original assignee: Samsung Electronics Co Ltd
Current assignee: Samsung Electronics Co Ltd
Priority date: 1989-11-14
Filing date: 1990-03-29
Publication date: 1991-05-29
Anticipated expiration: 2010-03-29
Also published as: KR910010262U; GB2238443B; KR920008249Y1; JPH067629Y2; GB9007068D0; JPH0369969U

Abstract

A synchronising pulse detecting circuit for use in an image receiving device detects the pulse width and comprises: a pulse generating means for generating pulse rows 2; a gate device G1 for outputting the detecting pulse rows generated by the pulse generating means during a period of potential synchronizing signal; a first inspecting means 10 for counting 7, 8 the pulses passed by the gate G1 and generating an output pulse from monostable 15; and a second inspecting means 20, enabled by the monostable output to count 21, 22 the pulses passed by gate G1 in the next sync pulse period; an output stabilizing means 30 for outputting synchronising pulse detection signals of a stabilized logic state. Using the present invention, the muting of noise and a mono-chromatic screen can be provided during channel search when no synchronizing signals are detected. <IMAGE>

Description

SYNCHRONISM DETECTING CIRCUIT UTILIZING PULSE WIDTH The present invention relates to an image receiving device, and particularly to a synchronism detecting circuit by which video noises and audio noises are removed by discriminating the non-broadcasting channels from the broadcasting channels.

Generally, image receiving device includes television, video tape recorder (to be called hereinafter "VTR") and the like, and VTR is a device which is capable of recording television image signals on a magnetic tape, and regenerating the television image signals recorded on the magnetic tape.

Among the receiving channels of television and VTR, the non-broadcasting channels which belong to the non-signal bands show ugly screens and wild noise, and therefore, it is the recent trend that efforts are made to mute the sounds of the non-broadcasting channels and to furnish a blue color screen or other monochromatic screen.

Further, among the receiving channels of televisions and VTR, the non-broadcasting channels occupy a greater part of the total channels, and therefore, if there are many nonbroadcasting channels between two broadcasting channels, an inconvenience is experienced in shifting from one broadcasting channel to another broadcasting channel, as well as consuming much time in performing the shifting.

In order to overcome such a problem, certain kinds of televisions and VTRs are so constructed as to discriminate the non-broadcasting channels through utilization of the picture search function, the discriminated broadcasting channels are stored in the memory, and the non-broadcasting channels are let to be leaped across, thereby saving the channel shifting time.

If the non-broadcasting channels of televisions and VTRs are let to give muted sounds and mono-chromatic screen, and if the non-broadcasting channels are to be skipped, then the non-broadcasting channels have to be discriminated, and the discrimination of them is carried out in such manner that the existence of a synchronizing signal is detected by means of a synchronism detecting device, thereby recognizing the existence or absence of an image signal based on the detected result.

However, the conventional synchronismdetecting circuit is liable to commit erroneous recognitions such that even the noise signals in the form of pulse arranged in a manner similar to the vertical svnchronism and the horizontal synchronism are accepted as synchronizing signals1 thereby judging a non-broadcasting channel as a broadcasting channel. Therefore such televisions and VTRs are imperfect in muting the noise and in furnishing a mono-chromatic screen, as well as being incapable of skipping the nonbroadcasting channels during the image search.

Therefore, it is the object of the present invention to provide a synchronism detecting circuit utilizing a pulse width for use in an image receiving device, in which the synohronism is exactly detected by inspecting the pulse width, so that the video signals and the noise signals of non-broadcasting channels should be muted, and that the nonbroadcasting channels should be exactly skipped during the channel search.

In achieving the above object, the synchronism detecting circuit according to the present invention comprises: a pulse generating means for generating pulse rows; a gate device for outputting the detecting pulse rows generated by the pulse generating means during the synchronized period of the sycnhronizing signal upon receipt of the synchronized pulse period of the received synchronizing signal; a first inspecting means for recognising the synchronizing signals based on the number of the pulses of the gated pulse rows supplied from the gate device during the synchronized pulse period of the received synchronizing signal;; a second inspecting means for recognizing the synchronizing signals by inspecting the number of the pulses of the gated pulse rows outputted by the gate device during the period of the synchronized width of the synchronizing signal which is supplied in accordance with the output of the first inspecting means; and an output stabilizing means for outputting synchronism detecting signals of a stabilized logic state, which are stablized by the outputs of the second inspecting means.

The above object and other advantages of the present invention will become more apparent by describing in detail the preferred embodiment of the present invention with reference to the attached drawings in which: Figure 1 shows the synchronism detecting circuit utilizing pulse width according to the present invention; and Figure 2 shows the operating waveforms of the different parts of the circuit of Figure 1.

Figure 1 shows the preferred embodiment of the circuit of the present invention.

A logic multiplying device G1 includes an input terminal connected through a line 1 to a synchronizing separator means1 and another input terminal connected through a line 2 to a pulse generating means, thereby performing the function of a gate device.

A first inspecting means 10 comprises: a first counter 11 including a clock terminal CLK connected through a line 3 to the output terminal of the logic multiplying device G1, and also including a reset terminal RS connected through the line 1 to the synchronizing separator means; a second counter 12 including a clock terminal CLK connected to the output terminal of the first counter 11; a third counter 13 including a reset terminal RS connected through the line 1 to the synchronizing separator means, also including a clock terminal CLK connected through the line 2 to the pulse generating means, and also including an output terminal connected to the reset terminal of the second counter 12; a delaying device 14 for delaying the output of the output terminal of the second counter for a certain period of time; and a mono-stable multi-vibrator 15 for generating pulses of certain widths in accordance with the outputs of the delaying device, and for transmitting the generated pulses through a line 4.

A second inspecting means 20 comprises: a transistor Q1 including a collector connected through the line 3 to the output terminal of the logic multiplying device G1, and also including a base connected through the line 4 to the output terminal of the mono-stable multi vibrator 15; a fourth counter 21 including a clock terminal connected to the emitter of the transistor Q1, and also including a reset terminal RS connected through the line 1 to the synchronizing separator means; and a fifth counter 22 including a reset terminal RS connected through the line 4 to the output terminal of the mono-stable multi-vibrator 15, and also including a clock terminal connected to the output terminal of the fourth counter 21.

An output stabilizing means 30 comprises: a transistor Q2 consisting of a base connected through an inverting device I1 to the output terminal of the fifth counter 22, a collector connected to a reference power source GND, and an emitter connected through a resistance R1 to a supply power source Vcc; a transistor Q3 consisting of a base connected to the emitter of the transistor Q2, a collector connected to the reference voltage GND, and an emitter connected through a resistance R2 to the supply power source Vcc; and a condenser C1 connected between the reference power source GND and the base of the transistor Q3.

Figure 2 shows the operating -wave patterns of the different parts of the circuit of Figure 1.

That is, Figure 200 shows a synchronizing signal, Figure 201 a detecting pulse row, Figure 202 a wave pattern of the output of the logic multiplying device G1, Figure 203 a wave pattern of the output of the second counter 12, Figure 204 a wave pattern of the output of the delaying device 14, Figure 205 a wave pattern of the output of the mono-stable multi-vibrator, Figure 206 a wave pattern of the output of the transistor Q1, Figure 207 a wave pattern of the output of the fifth counter 22, and Figure 208 an operating wave pattern of the condenser C1.

The operations of the circuit of Figure 1 will now be described referring to the wave patterns of Figure 2.

The synchronizing separator means is an indispensable component in the usual televisions and VTRs, and the pulse generating means is required for activating a microcomputer of a television and VTR using a microcomputer, the pulse generating means being added for other purposes in televisions and VTRs which do not use a microcomputer. The detecting pulse rows which are outputted by the pulse generating means have an extremely short period like that of Figure 201, i.e., a period far smaller than the period of the synchronizing signal of Figure 200, and further, the synchronizing signal like that of Figure 2A can be used either as a horizontal synchronizing signal or as a vertical synchronizing signal.

The logic multiplying device G1 receives the detecting pulse rows from the pulse generating means and the synchronizing signals from the synchronizing separator means into its two input terminals through the lines 1, 2. Then the logic multiplying device G1 outputs through the line 3 to the clock terminal CLK of the first counter 11 and to the collector of the transistor Q1 the detecting pulse rows which are supplied during the period when the above mentioned synchronizing signal is in a high logic state.

Here, the wave pattern of the output signal of the logic multiplying device G1 becomes like that of Figure 202.

The first counter 11 will be in an initial state during the period of a low logic state of the synchronizing signal which is supplied through the line 1 to the reset terminal RS from the synchronizing separator means. Then the first counter 11 carries out repeated countings of a first numeral (e.g., 7) in accordance with the gated pulse rows supplied through the line 3 the clock terminal CLK from the logic multiplying device G1 during the period of the high logic state. Then the first counter 11 supplies a pulse to the clock terminal CLK of the second counter 12 each time the first numeral (e.g., 7) is counted.

The third counter 13 stays in an initial state during the period of a low logic state of the synchronizing signal which is supplied from the synchronizing separator means through the line 1 to the reset terminal RS. Then the third counter 13 counts a second numeral (e.g., 58) in accordance with the detecting pulse rows which are supplied from the pulse generating means through the line 2 to the clock terminal CLK. Then the third counter 13 supplies a pulse of a low logic state to the reset terminal RS of the second counter 12 each time the second numeral (e.g., 58) is counted.

The second counter 12 is initialized upon receipt of a pulse of a low logic state from the third counter 13 into the reset terminal RS, carries out an increment-counting by "1 each time a pulse is supplied from the first counter 11 into the clock terminal CLK, and then, when the incrementing reaches a third numeral (e.g., 8), supplies to the delaying device 14 a first synchronism detecting signal of a high logic state like that of Figure 203. The reason why the numerals 7,58,8 are taken as examples of the first to third numerals is that the pulse width of the synchronizing signal is preferred to be larger than 56 times the period of the detecting pulse and smaller than 58 times the period of the detecting pulse.

The delaying device 14 delays for a certain period of time the first synchronism detecting signal from the second counter 12 as shown in Figure 204 before supplying it to the mono-stable multi-vibrator 15.

The mono-stable multi-vibrator 15 generates a pulse of a high logic state having a width large enough to cover the next synchronizing pulse period each time the first synchronism detecting signal is supplied from the delaying device. The mono-stable multi-vibrator 15 delivers the above mentioned pulse through the line 4 to the base of the transistor Q1 and to the reset terminal RS of the fifth counter 22, the output wave pattern of the mono-stable multi-vibrator 15 being like that of Figure 205.

The transistor Q1 is turned on during the period when the output of the mono-stable multi-vibrator 15, which is supplied through the line 4 into the base, is in a high logic state. The output of the logic multiplying device G1 which receives its input through the line 3 into its collector is supplied through the emitter of the transistor Q1 to the clock terminal OLK of the fourth counter 21 by the transistor QI. Here, the wave pattern of the output of the transistor Q1 becomes like that of Figure 206.

The fourth counter 21 stays in an initial state during the period of a low logic state of the synchronizing signal which is supplied from the synchronizing separator means through the line 1 to the reset terminal RS. Then the fourth counter 21 counts up to a first numeral (e.g., 7) in accordance with the pulse rows which are supplied from the emitter of the transistor Q1 to the clock terminal CLK.

Then the fourth counter 21 supplies a pulse to the clock terminal OLK of the fifth counter 22 each time the first numeral (e.g., 7) is counted.

The fifth counter 22 stays in an initial state during the period when the output of the mono-stable multi-vibrator 15, which is supplied through the line 4 to the reset terminal RS, is in a low logic state. During the period of a high logic state, the fifth counter 22 carries out an increment-counting by '1" each time a pulse is supplied from the fourth counter 21 to the clock terminal CLK, until a second numeral (e.g., 8) is formed. Then, each time a second numeral (e.g., 8) is formed (counted), the fifth counter 22 supplies a high logic state pulse in the form of a second synchronism detecting signal to the base of the transistor Q2 through an inverting device n. Here, the wave pattern of the output of the fifth counter 22 is as shown in Figure 207. The reason why the first to third numerals of the fourth to fifth counters 21,22 are made same as those of the first to second counters 11,12 is that they are made so for the sake of the descriptional convenience, and therefore, they can be set in values different from those of the first and second counters 11,12 in order to provide a permissible range.

The transistor Q2 is turned on during each pulse period of the second synchronism detecting signals which are the outputs of the fifth counter 22, and which are inverted by the inverting device I1 and are supplied to the base of the transistor Q2, with the result that the transistor Q2 discharges the whole voltage charged into the condenser C1.

The condenser C1 discharges its own charged voltage through both the emitter and the collector of the transistor Q2 during the time when the transistor Q2 is turned on, and then1 slowly receives the charging voltage from the time when the transistor Q2 is turned off. Under this condition, the charging speed of the condenser C1 is determined by the multiplication of the resistance value of the resistor R1 and the capacitance value of the condenser C1, and therefore, the charging and discharging wave patterns of the condenser C1 become like the wave pattern of Figure 208.

The transistor Q3 is turned on by the transistor Q2, and the turned-on state of the transistor Q3 maintained until the charging voltage of the condenser C1 rises up to the turn-off voltage after reaching the reference voltage Vr of Figure 208. Thereupon, the transistor Q3 transmits a stabilized synchronism detecting signal of a low logic state through the line 5 which is connected to its emitter.

If the output of the transistor Q3 is to be kept in a stabilized logic state during the time when the synchronizing signals are continuously detected, the time constants of the resistance R1 and the condenser C1 have to be provided in larger numbers than the period of the synchronizing signal.

According to the present invention as described above, the detection of a synchronizing signal is recognized only in the case where the pulse width of the received synchronizing signal is corresponded with the reference pulse width of the synchronizing signal through two rounds, and therefore, the synchronizing signals can be detected in an exact manner.

Further, owing to the exact detection of the synchronizing signals, the existence or absence of image signals, i.e., broadcasting signals and non-broadcasting signals can be exactly discriminated, with the result that the muting of noise and the provision of a monochromatic screen can be carried out without fail, as well as surely skipping the non-broadcasting channels when shifting the channel.

Claims

CLAIMS:

1. A synchronism detecting circuit utilizing pulse width for use in an image receiving device provided with a synchronizing separator means, comprising: a pulse generating means for generating pulse rows; a gate device for outputting said detecting pulse rows generated by said pulse generating means during the synchronized period of a synchronizing signal upon receipt of said synchronizing signal; a first inspecting means for recognizing said synchronizing signals based on the number of the pulses of gated pulse rows supplied from said gate device during said synchronized pulse period of the received synchronizing signal;; a second inspecting means for recognizing said synchronizing signals by inspecting the number of the pulses of gated pulse rows outputted by said gate device during the period of said synchronized pulse width of said synchronizing signal which is supplied in accordance with the output of said first inpecting means; and an output stabilizing means for outputting synchronism detecting signals of a stabilized logic state, which are stabilized by the outputs of said second inspecting means.

2. The synchronism detecting circuit as claimed in claim 1, wherein said first inspecting means comprises: a first counting means for counting the number of the pulses of output pulse rows supplied from said gate device and generating a first synchronism detecting signal in the form of a pulse when a first predetermined value is counted; a waveform shaping means for shaping said first synchronism detecting signal into on operation controlling signal in the form of a pulse having a width large enough to cover the next synchronizing pulse period and supplying said operation controlling signal to said second inspecting means.

3. The synchronism detecting circuit as claimed in claim 2, wherein said waveform shaping means comprises; a delay mean for delaying said first synchronism detecting signal supplied from said first counting means by the starting point of the next synchronizing pulse; a mono-stable multi-vibrator for generating the operation controlling signal in the form of a pulse having width large enough to cover both a starting point and ending point of said synchronizing pulse by said output of delay means and supplying said operation controlling signal to said second inspecting.

4. The synchronism detecting circuit as claimed in claim 2, wherein said second inspecting means comprises; a gate means for sampling output pulse rows supplied from said gate device by said operation controlling signal that is supplied from said waveform shaping means; a second counting means for counting the number of the pulses of output pulse rows supplied from said gate means and generating a second synchronism detecting signal in the form of a pulse when a second predetermined value is counted, and supplying said second synchronism detecting signal to said output stablilizing means.

5. The synchronism detecting circuit as claimed in claim 4, wherein said second predetermined value set up in value defference from said first predetermined value.

6. Synchronism detecting circuit utilizing pulse width substantially as hereinbefore described with reference to Figure 1 of the accompanying drawing.