JPH0888661A - Psk demodulator - Google Patents

Abstract

PURPOSE: To realize low current consumption suitable for portable application by reducing spurious radiation due to a static operation in demodulation of a high sensitivity and high speed modulation signal in the demodulator used by a communication terminal equipment/public base station for interconnection testing. CONSTITUTION: An IF signal is amplified by a LOG amplifier 2. A PLL circuit 3 extracts a clock from an RSSI output of the LOG amplifier 2 to provide the output of a symbol clock. An orthogonal detector 5 applies orthogonal detection to a LOG limiter output from the LOG amplifier 2 to provide outputs of i(t), q(t). A 1st sample-and-hold circuit 6 and a 2nd sample-and-hold circuit 7 respectively delay the i(t), q(t) by one-bit to provide outputs of i(t-1), q(t-1). An analog multiplier 8 uses the signals to conduct 1-symbol delay detection.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PSK (Phase Shift Keying) demodulator used in a mobile communication device, and more particularly to a PSK demodulator with reduced spurious due to static operation in demodulation with high sensitivity and high speed modulation.

[0002]

[Prior art]

(Explanation of mobile communication) A simplified mobile phone system, which is also called a next-generation cordless phone, has been developed. This system is capable of making and receiving calls by accessing a public base station installed in a street or an underground mall by taking out one's own cordless telephone used at home or office.

It is necessary to carry out an interconnection test to make sure that the communication terminal (cordless telephone), the public base station, and the digital pseudo communication network function properly. In addition, it is necessary to select the optimum place to install the public base station. A simple portable testing machine for making the selection has been desired.

A communication terminal, such as a PHS (Per)
In the personal Handyphone System, frequency division is performed in a frequency band of 1.9 GHz (24 MHz).
Width), channel separation is 300 KHz, and the number of channels is 77 CHs. In addition, the channels of each frequency are time-divided into four slots for upstream and four slots for downstream.

(Conventional demodulator) π / 4 shift QPSK
(Quadrature Phase Shift K
Since there is a received wave phase fluctuation due to fading, differential detection is common in the eyeing). Based on FIG.
An example of a π / 4 shift QPSK baseband differential detector announced in “Yamamoto, Kunieda, Onishi, Makimoto: 1992 IEICE Spring National Convention Proposal B342” will be described.

The received IF signal is subjected to asynchronous quadrature detection through a BPF and a limiter. This detected signal is subjected to instantaneous phase detection and then phase-compared with one symbol before, and is passed as a phase difference signal to the bit synchronization section and the decoding section for data reproduction. The received IF signal is phase-compared with the in-phase and quadrature components by an asynchronous reference signal, and then counted as a signal proportional to the instantaneous phase after being counted for a certain period by a high-speed clock compared with the IF signal.

Here, the symbol frequency (fs) and the IF
A certain condition is required between the frequency (fi) and the counting frequency (fc) of the counter. Specifically, fs << f
The relationship i << fc is required. When fc <16 × fi, the error rate deteriorates. Therefore, fi = 6.25 ×
fs and fc = 16 × fi. That is, in the conventional technique, the counting frequency as a phase detector is 100 times the symbol frequency (fc = 16 × 6.25 = 100f).
s).

[0008]

However, in the case of PHS, since the data rate is 384 Kbps, fc =
It becomes 19.2 MHz. Therefore, the clock that drives the counter is high-speed, and the current consumption cannot be reduced, which is not suitable for portable use. The present invention has been made in view of such circumstances, and an object of the present invention is to provide a PSK demodulator that realizes low current consumption.

[0009]

In order to solve the above problems, in a PSK demodulator of the present invention, a LOG amplifier (logarithmic IF amplifier) for amplifying an IF signal (intermediate frequency signal) and an RSSI (logarithmic type IF amplifier) Received
Signal Strength Indicato
r) PLL (Phase) that extracts the clock from the output
Locked Loop) circuit,
A quadrature detector that quadrature-detects the output of the LOG limiter of the LOG amplifier, a sample hold circuit that delays the output of the quadrature detector by 1 symbol, a quadrature-detected baseband signal, and a delayed signal to calculate the IF signal to 1 symbol. It consists of an analog multiplier for differential detection.

[0010]

According to the PSK demodulator configured as described above,
No need for high-speed clock, so no spurious. Furthermore, since an analog multiplier is used as a phase detector,
Low current consumption. Further, even a high speed modulation signal can be demodulated.

The term "spurious" as used herein has the following meaning. Originally, the local oscillation signals necessary for demodulation should be only the carrier frequency (or center frequency of IF) f ₁ and the clock frequency f ₂ . However, in the conventional technique, the clocks N ₁ × f ₁ and N ₂ × f _{2 that} are integral multiples are required,
Further, when these intermodulation products, M ₁ and M ₂ are arbitrary integers, M ₁ × N ₁ × f ₁ + M ₂ × N ₂ × f ₂ = f _SP
May be a communication frequency in the 1.9G band, or another IF frequency. If this is the frequency f being used by the station
_When it matches with _R , it becomes an interfering wave and the function as a radio is impaired. Therefore, this f _SP is called a spurious. In the present invention, since N ₁ = 1 and N ₂ = 1 or 2, f _SP is less likely to come near f _R as compared with the conventional technique.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of a PSK demodulator.

The IF signal is logarithmically amplified by the LOG amplifier 2 after passing through the IF filter 1. As the LOG amplifier 2, for example, AD606 manufactured by Analog Devices, Inc. is used. The RSSI output of the LOG amplifier 2 is input to the PLL circuit 3 to extract the symbol clock. The local signal generator 4 generates a signal that matches the center frequency of the IF signal. The LOG limiter output of the LOG amplifier 2 is input to the quadrature detector 5 and quadrature detected by the signal of the local signal generator 4 to be i (t) and q (t). The first sample and hold circuit 6 samples and holds the i (t) at the symbol clock and delays i (t) by one symbol.
-1) is output. Similarly, the second sample and hold circuit 7 samples and holds q (t) at the symbol clock and outputs q (t-1) delayed by one symbol. Next, I (Inphase) and Q (Qu
An analog multiplier is used to obtain the difference i (t), q (t), i (t-1), and q (t-).
1) is calculated and the IF signal is differentially detected.

Specifically, in the first multiplier 8a, i
(T) is multiplied by i (t-1), and i (t) * i (t-
1) is obtained. In the second multiplier 8b, q (t) and q (t-
1) is multiplied to obtain q (t) × q (t-1). The third multiplier 8c multiplies q (t) and i (t-1) to obtain q
(T) × i (t−1) is obtained. In the fourth multiplier 8d, i
(T) is multiplied by q (t-1), and i (t) * q (t-
1) is obtained. Next, in the first adder 8e, I = + i (t)
Xi (t-1) + q (t) * q (t-1), Q = + q (t) * i (t-1) -i (t) * q in the second adder 8f.
Calculate (t-1).

The differential detection is a process for determining a code by obtaining a phase difference between detector input signals for one symbol.
Here, the symbol synchronization is set to 1 for the sake of explanation. PL
The L circuit 3 outputs a symbol clock synchronized with the clock of the input signal. The rising edge of the symbol clock coincides with the compound point (the point where the eyes of the eye pattern are completely open). Therefore, at this compound point, I,
The sign of Q can be determined. Therefore, the first comparator 9 for discriminating the positive / negative of I and the first D-type flip-flop 10 for holding the instantaneous value at the decoding point of the output (logical value) are required. Similarly, a second comparator 11 that determines whether the Q is positive or negative and a second D-type flip-flop 12 that holds the instantaneous value at the compound point of the output (logical value) are required.

The output X of the first D-type flip-flop 10 on the I side and the second D-type flip-flop 1 on the Q side.
The output Y of 2 has 2-bit information for each symbol period. In order to convert this into 1-bit information for each bit period, the multiplexer 13 performs parallel / serial conversion. Therefore, from the multiplexer 13, Y (t-1),
Information is output in the order of X (t−1), Y (t), and X (t), one bit for each half of the symbol period.

(Reason for Low Power Consumption of Analog Multiplier) The input of the analog multiplier 8 is the baseband component of the limiter output of the LOG amplifier 2, and its amplitude is constant in the state of receiving a signal. Therefore, the dynamic range of the analog multiplier 8 (the range of input amplitude operable as a multiplier) does not have to be wide. Therefore, the operating bias current of the analog multiplier 8 can be reduced.
That is, it is possible to use an analog multiplier with low power consumption as the analog multiplier 8.

[Other Embodiment of Analog Multiplier] I = + i
(T) × i (t−1) + q (t) × q (t−1), Q =
FIG. 2 shows another embodiment of the analog multiplier 8 that performs the operation of + q (t) * i (t-1) -i (t) * q (t-1). U = (i (t) + q (t)) × i (t-1), V =
(I (t-1) -q (t-1)) * q (t), W = (i
If (t−1) + q (t−1)) × i (t), then I =
U-V and Q = U-W. This increases the number of adders by 3 compared with the first embodiment of FIG. 1, but the number of multipliers is only 3. As a result, the power consumption is lower than that of the first embodiment.

[Application to Testing Machine] FIG. 3 is a block diagram of a testing machine using the present invention. For example, (2 ⁹ -1)
Transmit the PN code and measure the bit error at the receiver. A PN code is generated by the pattern generator 20, the code is modulated by the digital modulator 21, and the code is transmitted from the antenna 22. The characteristics of the digital modulator 21 are, for example, modulation method = π / 4 shift QPSK, roll-off rate: α = 0.
5 RCRO root Nyquist type, bit rate = 38
4 kbps and carrier frequency = 1.9 GHz.

The π / 4 shift QPSK continuous wave demodulator sets the frequency of the first local oscillator 23 to 1.810 GHz.
(Fc-90 MHz), and the second local oscillator 24
Was set to 79.3 MHz. The characteristics of the IF filter 1 in the PSK demodulator 25 are 10.7 MHz and root Nyquist. The PN code (RD) demodulated by the PSK demodulator 25 and the symbol clock (RT) are input to an error measuring device such as a data transmission unresolver,
Measure the error rate etc.

[0021]

As described above, according to the PSK demodulator of the present invention, the LOG amplifier 2 for amplifying the input signal (IF signal), the PLL circuit 3 for extracting the clock from the RSSI output of the LOG amplifier 2, A quadrature detector 5 that quadrature-detects the LOG limiter output of the LOG amplifier 2 and an analog multiplier 8 that delay-detects the quadrature-detected baseband signal by one symbol are provided. Therefore, no high-speed clock is required, and spurious does not occur. Further, since the analog multiplier 8 is used as the phase detector, the current consumption becomes low. Further, even a high speed modulation signal can be demodulated.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram of another embodiment of the analog multiplier of the present invention.

FIG. 3 is a block diagram of a test apparatus utilizing the present invention.

FIG. 4 is a block diagram of a conventional π / 4 shift QPSK baseband differential detector.

[Explanation of symbols]

2 ... LOG amplifier, 3 ... PLL circuit, 5 ... Quadrature detector,
6 ... 1st sample hold circuit, 7 ... 2nd sample hold circuit, 8 ... Analog multiplier.

Claims (1)

[Claims] 1. A LOG amplifier (2) for logarithmically amplifying an input signal, a PLL circuit (3) for extracting a symbol clock from the RSSI output of the LOG amplifier, and a limiter output of the LOG amplifier for quadrature detection i (t). ) And q (t) respectively, and a first sample-and-hold circuit for sampling and holding i (t) at the symbol clock and outputting i (t-1) delayed by one symbol. The circuit (6) and q (t) are sample-held by the symbol clock, and q (t- is delayed by one symbol.
A second sample and hold circuit (7) for outputting 1),
I (t), q (t), i (t-1), and q (t-
A PSK demodulator provided with an analog multiplier (8) that delay-detects an input signal by inputting 1) and performing an operation.