KR100226995B1 - DIGITAL DEMODULATING METHOD AND DEVICE OF ó /4 QPSK - Google Patents

Abstract

The present invention relates to a π / 4 QPSK digital demodulator for demodulating a π / 4 QPSK modulated signal applied to a digital mobile communication system.

The present invention provides a band pass filter for removing an unnecessary signal from an input QPSK modulated signal, a channel separator for mixing a modulated signal of the band pass filter and a previous modulated signal into a Q and I channel signal, and separating the channel. First and second low pass filter devices which extract only signals of quadrature and in-phase components from the Q and I channel signals separated from the device, and first and second samples that determine and restore data by sampling the Q and I channel signals. A data reconstruction device, a parallel / serial conversion device for converting the two pieces of restored data in series and outputting them, and three phase difference information based on previous data of the converted current serial data, and sequentially delaying and calculating It consists of an error correction device that corrects two errors by determining the threshold of the calculated value and without the error correction circuit using complex hemming code and BCH code. Simple hardware can correct errors in the data.

Description

π / 4QPSK digital demodulation method and apparatus

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital demodulation device. In particular, in a code division multiple access wireless mobile system, two signals without a separate error correction circuit are modulated among signals modulated by π / 4 quadrature phase shift keying (QPSK). Π / 4 QPSK digital demodulation method and apparatus for stably correcting and restoring error data.

In general, the demand for mobile communication services is increasing rapidly. In order to realize the above services to a large number of subscribers under limited frequency resources, a modulation scheme with a high spectrum efficiency is required. It is essential to study frequency efficiency utilization techniques such as spectrum efficiency utilization techniques and error correction code / decoding techniques.

In Europe, Group Special Mobile (GSM) groups are determined by digital cellular standards to serve all regions, and in the United States, TIA (Telecommunication Industry Association) is adopted as a standard for land mobile systems.

Current digital mobile modulation and demodulation methods include Gaussian-prefiltered Minimum Shift Keying (GMSK) in Europe and π / 4-shift QPSK in the United States and Japan.

In general, linear modulation transmits information with a narrower bandwidth than constant envelope modulation such as GMSK and TFM.

However, since the constant amplitude modulation method does not include information in the amplitude of the modulated signal, it is not necessary to apply strict fidelity to the signal waveform.

Therefore, a nonlinear amplifier with good power efficiency can be used.

On the other hand, the linear modulation method uses a linear amplifier because it must transmit information on the amplitude of the signal and have strict fidelity in the signal waveform.

In addition, the π / 4 shift QPSK has been adopted as a standard modulation scheme of the next generation digital cellular mobile communication system.

In the digital communication system, coherent detection is traditionally used to efficiently use power and bandwidth.

Although the synchronous system is theoretically good in power efficiency and performance in white Gaussian noise (AWGN), the performance decreases slightly due to a decrease in the synchronous capability in the presence of phase noise such as multipath fading or Doppler Shift. Done.

This situation is particularly serious in narrowband mobile communication systems.

Asynchronous systems such as differential detection are appropriate in narrowband mobile systems due to the need for carrier recovery.

Linear modulation such as QPSK has better bandwidth efficiency than constant amplitude modulation such as GMSK or TEM.

In order to use power efficiently in a digital communication system, a nonlinear amplifier is used. However, when a band-limited, non-constant linearly modulated carrier passes through a nonlinear amplifier to increase power efficiency, the spectrum spreads and crosstalk between in-phase and quadrature causes severe adjacent channel interference.

Such a system cannot utilize the spectrum efficiently and, as a result of the nonlinear amplifier, the bit error rate (BER) performance is slightly reduced.

In addition, a method of reducing amplitude variation of a modulated carrier, which is a disadvantage of linear modulation, uses OQPSK (Offset QPSK).

However, this modulation method requires synchronous detection, which results in low bit error rate characteristics in the mobile communication channel as described above.

Constant amplitude modulation, such as MSK, GMSK, and TFM, allows the use of nonlinear amplifiers without spreading the spectrum, as well as differential detection.

However, a disadvantage of this modulation is that it has a low spectral efficiency.

Accordingly, π / 4 shift QPSK is a linear modulation method that simultaneously satisfies power and bandwidth efficiency and can use a nonlinear amplifier.

Since the π / 4 shift QPSK is limited in phase shifts to ± π / 4 and ± 3π / 4, it does not deviate from ± π changes such as QPSK, resulting in reduced amplitude variations.

In addition, it can be used for asynchronous detection as well as synchronous detection, and bandwidth efficiency is quite good.

As such a modulation device, there is a device as shown in Fig. 1, which will be described as an example of a general? / 4 QPSK modulation device.

That is, the serial / parallel converter 101 separates the serial data input through the input terminal 100 into data of the orthogonal component and the data of the in-phase component and outputs them in parallel, and separates them from the serial / parallel converter 101. The differential encoding unit 102 obtains the phase shift amount by differentially encoding the data of the quadrature component and the in-phase component which are inputted, and based on the phase shift amount and the previous signal obtained by the differential encoding unit 102. A signal mapping section 103 for outputting a baseband signal of orthogonal and in-phase components with respect to time, and a baseband signal of an orthogonal component and a baseband signal of an in-phase component obtained by the signal mapping section 103, respectively, are output by low pass filtering. The first and second low pass filter units 104 and 105 and the signals filtered by the first and second low pass filter units 104 and 105 are input terminals 106 and 108, respectively. Modulated to the high frequency signal input through the output Synthesizer 10 for synthesizing the signals modulated by the first and second modulators 107 and 109 and the first and second modulators 107 and 109 and transmitting them through an antenna ANT. It consists of.

In the modulation device configured as described above, first, serial data input through the input terminal 100 are separated into in-phase data SI and quadrature data SQ through a serial / parallel conversion unit 101 to be differentially encoded. It is input to the unit 102.

The differential encoding unit 102 is differential to obtain nπ / 4 (n = ± 1, ± 3) phase shift in the phase of the input signal of the in-phase component (SI) and the quadrature component (SQ) and the previous signal. By coding, a phase shift amount Δθ k is obtained for each gray code.

The phase shift amount [Delta] [theta] k obtained by the differential encoding unit 102 is input to the signal imager 103.

The signal thinking unit 103 calculates the phase shift amount Δθ k obtained from the differential coding unit 102 and the immediately preceding signal to display an unfiltered NRZ baseband signal representing the in-phase component It and the quadrature component Qt. non-return-to zero).

The baseband signal It of the in-phase component and the orthogonal component baseband signal Qt output from the signal thinking unit 103 are filtered by the first and second low pass filter units 104 and 105, respectively, and are then filtered. And the second modulators 107 and 109.

The first modulator 107 mixes the baseband signal It of the in-phase component filtered by the first low pass filter 104 and cosω ₀ t which is a phase match signal input through the input terminal 106. The second modulator 107 is provided to the combining unit 110 and the quadrature phase inputted through the input terminal 108 and the baseband signal Qt of the quadrature component filtered by the second low pass filter 105. The signal -sinω ₀ t is mixed and provided to the synthesis unit 110.

The combiner 110 synthesizes two values modulated by the first and second modulators 107 and 109 and transmits the synthesized values through the antenna ANT.

As described above, in π / 4 shift QPSK, information is included in a phase difference between two consecutive channel signals and transmitted.

Therefore, the receiver must detect the phase difference between two consecutive signals in order to extract information.

The conventional apparatus for detecting the phase difference between the two consecutive signals includes the apparatus as shown in FIG. 2, and the apparatus shown in FIG. 2 will be described as an example of the conventional? / 4 QPSK demodulator.

That is, the demodulation device includes a reception filter 201 for removing unnecessary signals from the QPSK modulated signal input from the reception input terminal 200, a local oscillator 203 for generating a local carrier signal, and the local oscillator 203. A first phase shifter 204 for shifting the phase of the local carrier signal by? / 2, and a local carrier signal phase shifted by the first phase shifter 204 and the reception filter 201 A first mixing unit 202 mixing the modulation signals, a second mixing unit 205 mixing the local carrier signal input from the local oscillating unit 203 and the modulation signal of the receiving filter 201, and the first mixing unit 205 mixing the modulation signals; The third low pass filter 206 and the second mixed unit 205, which block the carrier component from the mixed signal in the first mixing unit 202 and extract only the baseband signal of the quadrature component (Q). Blocks the carrier component and extracts only the baseband signal of the in-phase component (I) 4 Low frequency filter unit 217, the frequency of the local carrier on the receiving side generated from the local oscillation unit 203 and the carrier frequency of the transmitting side received by the third and fourth low pass filter units 206 and 207. A carrier recovery unit having the third and fourth mixing units 210, 211 and the loop filter unit 209 for controlling the output of the local oscillator 203 according to the phase synchronization of the local oscillator 203, and the reception filter unit 201. Clock recovery section 208 for recovering the symbol rate clock of the transmitting side input from the transmission side, and a third mixing section 210 of the carrier recovery section by phase shifting the clock recovered by the clock recovery section 208 by? / 2. A second phase shifter 212, a third phase shifter 215 for phase shifting the clock recovered by the clock recovery unit 208 by [pi], and a recovery of the clock recovery unit 208. Second determination section 21 for detecting a phase difference between the clock and the baseband signal of the in-phase component I extracted from the fourth low pass filter 207. 4) and a first determination unit 213 for obtaining a phase difference between the phase shifted by the third phase shifter 215 and the baseband signal of the quadrature component Q extracted by the third low pass filter 206. ), A first adder 216 for adding the phases of the quadrature component and the in-phase component obtained by the first and second determination units 213 and 214, and the first adder 216. And a second adder 217 that adds and outputs a signal and a clock of the clock recovery unit 208.

In the π / 4 shift QPSK demodulation device configured as described above, when a QPSK modulated signal is first input from the reception input terminal 200, the reception filter 201 removes unnecessary signals from the input modulation signal, thereby eliminating unnecessary signals from the first and second mixing units. 202 and 205 and the clock recovery unit 208.

The first and second mixing units 202 and 205 multiply the output of the reception filter unit 201 by a local carrier synchronized with the transmitting side and output the multiplication.

In other words, the local carrier signal is oscillated by the local oscillator 203 and input to the second mixer 205, and phase shifted by π / 2 by the first phase shifter 204. ) Is entered.

The first mixing unit 202 extracts a quadrature component signal by mixing the local transfer and the signal phase shifted by the first phase shifter 204 and the modulation signal input from the reception filter 201.

The second mixing unit 205 extracts the in phase component signal by mixing the input modulation signal and the local carrier signal.

The extracted quadrature signal and the in-phase component signal are provided to the third and fourth low pass filter units 206 and 207, respectively.

The third and fourth low pass filter units 206 and 207 block carrier components of the first and second mixing units 202 and 205, and baseband and quadrature components, that is, the basebands of the Q and I channels. Only the signal is extracted and provided to the fourth mixing unit 211 and the first and second determination units 213 and 214, which will be described later.

On the other hand, since the clock recovery unit 208 has some error in the symbol rate clock used on the transmission side, the clock recovery unit 208 recovers the second and third phase shifters 212, 215, and second, which will be described later. The determination unit 214 is provided.

The second phase shifter 212 receives the clock restored by the clock recovery unit 208 and phase shifts it by? / 2 to provide it to the third mixer 210, and the third phase shifter 215 The clock of the clock recovery unit 208 is phase shifted by π and provided to the first determination unit 213.

Here, the fourth mixing unit 211 of the carrier recovery unit mixes the baseband signal of the Q channel and the baseband signal of the I channel extracted by the third and fourth low pass filter units 206 and 207 to form a third mixture. It is provided to the mixing unit 210.

The third mixing unit 210 of the carrier recovery unit recovers the carrier signal by mixing the output of the fourth mixing unit 211 and the output of the second phase shifter 212.

That is, in a phase-locked receiver, the frequency and phase of the local carrier used at the receiving side must be synchronized with the frequency and phase of the carrier used at the transmitting side. For this synchronization, a carrier recovery unit that recovers the frequency and phase of the carrier from the high frequency signal received at the receiver, that is, the third and fourth mixing units 210, 211 and the loop filter unit 209 This carrier recovery unit is implemented using a phase locked loop (PLL).

Meanwhile, the first determiner 213 obtains a phase difference from the phase shifted by the third phase shifter 215 and the baseband signal of the Q channel extracted by the third low pass filter 206 to obtain the first adder 216. The second determiner 214 detects the phase difference from the clock recovered by the clock recovery unit 208 and the baseband signal of the I-channel extracted by the fourth low pass filter 207 and then adds the first adder 216. To provide.

Accordingly, the first adder 216 adds the phases of the quadrature components and the in-phase components obtained from the first and second determination units 213 and 214, and the second adder 216 adds the first adder 216. The QPSK demodulated signal is output by adding the added signal and the clock of the clock recovery unit 208.

However, in the above-described conventional? / 4 QPSK demodulation device, a clock recovery unit for recovering how much error the symbol rate clock used on the transmitting side has is implemented. In addition, an error correction circuit using a separate hemming code and a BCH code is added to correct an error from the modulated signal.

As a result, not only the hardware for implementing the phase locked loop circuit and the error correction circuit is significantly complicated, but also the miniaturization of the product is difficult.

Accordingly, the present invention excludes the difficulty of miniaturization and manufacture of the product according to the phase-locked loop circuit and the separate error correction circuit in the above-described prior art, and in one aspect of the present invention, the differential on the π / 4 QPSK demodulation system It is an object of the present invention to provide a π / 4 QPSK digital demodulation method and apparatus that can detect two error data without using a conventional error correction circuit.

In addition, the present invention, by adopting a differential detection method that is strong against fading phenomenon, easy to configure the circuit, and stable on the π / 4 QPSK demodulation system, it is possible to correct error data by using the parity characteristic of the differential detection. There is a purpose.

It is an object of the present invention to simplify the circuit of a demodulation device by connecting an error correction circuit for correcting two errors at a rear end of a differential detector in a π / 4 QPSK demodulation system.

1 is a block diagram showing a typical [pi] / 4 QPSK modulator.

2 is a block diagram showing a conventional? / 4 QPSK demodulator.

3 is a block diagram of an exemplary embodiment of the present invention π / 4 QPSK demodulator.

4 is a diagram showing the error correction of FIG. 3 in more detail.

FIG. 5 is a configuration diagram showing in more detail the majority-resolution logic complex part of FIG.

6 is a graph showing an error correction state by applying the equation according to FIG.

Explanation of symbols for main parts of the drawings

301: band pass filter 302: channel separation unit

303: first low pass filter unit 304: second low pass filter unit

305: First data restoration unit 306: Second data restoration unit

307: parallel / serial converter 308: error correction

308a: first phase information detector 308b: second phase information detector

308c: third phase information detection unit 308d: first operation unit

308e: majority decision logic decoder

In the π / 4 QPSK digital demodulation method according to the present invention for achieving the above object, the signal received by modulating the digital data in the QPSK method, the I-channel signal and the Q-channel signal by a local carrier coexisted on the transmitting side A digital demodulation method of a QPSK receiving apparatus for demodulating and demodulating a signal, the method comprising: extracting phase information of an I-channel signal and a Q-channel by mixing the received modulation signal and a symbol-delayed reference signal; Restoring data by sampling phase information of the extracted I and Q channels; Converting the restored I-channel and Q-channel data into serial data; Restoring basic data based on the converted serial data and data previously delayed by a first predetermined symbol unit; Restoring data of a parity characteristic having correlation between the data based on the converted serial data and previously delayed data in units of second and third predetermined symbols; Sequentially delaying the restored basic information data and parity characteristic data in symbol units and determining a threshold of the delay value; And correcting an error of data through a predetermined modular operation on the error value of the determined threshold value.

In the π / 4 QPSK digital demodulation method according to the present invention, the data restoration process includes: restoring basic information data by comparing a phase difference between the converted serial data and one symbol delayed previous data; Restoring the data of the parity characteristic by comparing the phase difference between the converted serial data and previous data delayed by two symbols; And restoring the data of the parity characteristic by comparing the phase difference between the converted serial data and the six symbol delayed data.

Preferably, the delayed first predetermined symbol is one symbol.

Preferably, the delayed second and third predetermined symbols are 2 symbols and 6 symbols.

The π / 4 QPSK digital demodulation device according to the present invention for achieving the above objects, receives a signal obtained by modulating the digital data in the QPSK method, the I-channel signal and the Q-channel signal by a local carrier synchronized to the transmitting side A digital demodulation device of a QPSK receiver for demodulating and demodulating digitally a signal through each lowpass filter; A bandpass filter for removing unnecessary signals from the input QPSK modulated signal; A channel separator for mixing the modulated signal received by the bandpass filter and the previous one symbol delayed modulated signal into a Q channel and an I channel signal; First and second low pass filter devices which block carrier components from the Q-channel and I-channel signals separated by the channel separation apparatus, and extract only baseband signals of quadrature and in-phase components; First and second data restoring devices for sampling and determining the baseband signals of the Q and I channels respectively through the first and second low pass filter devices; A parallel / serial converter converting the restored two data into serial and outputting the serial data; And an error correction device that obtains three phase difference information based on the converted current serial data and previous data, sequentially delays and computes the result, and determines a threshold of the calculated value to correct two errors. .

In the π / 4 QPSK digital demodulation device according to the present invention, the channel separation device comprises: first symbol delay means for delaying and outputting a modulated signal inputted from the band pass filter by one symbol; First mixing means for extracting a signal of a Q channel by mixing the one symbol delayed signal and the modulation signal of the band pass filter; Phase shifting means for phase shifting the one delayed signal by [pi] / 2; And second mixing means for extracting the I-channel signal by mixing the phase shifted modulated signal and the band pass filter modulated signal.

In the π / 4 QPSK digital demodulation device according to the present invention, the first and second data restoring devices include a baseband signal of the Q channel and an I channel of the Q channel filtered by the first and second low pass filter devices. First and second sampling devices each sampling a signal; And first and second determination devices for determining respective data sampled by the first and second sampling devices.

In the? / 4 QPSK digital demodulation device according to the present invention, the error correction device comprises: first phase information for obtaining a phase difference based on data obtained by the parallel / serial converter and previous first predetermined symbol delayed data; Detection means; Second phase information detection means for obtaining a phase difference based on current data obtained by the parallel / serial conversion device and previous second predetermined symbol delayed data; A third phase information detection device for obtaining a phase difference based on current data obtained by the parallel / serial converter and previous third predetermined symbol delayed data; Delaying the phase information obtained by the second phase information detecting means by a predetermined symbol and calculating the delayed phase information and the current phase information obtained by the third phase information detecting means as predetermined module values to restore data of parity characteristics; 1 calculation means; Delaying the phase information obtained by the first phase information detecting means stepwise to calculate the delayed values and the operation value of the first calculating means to a predetermined module value to determine the threshold of the error to restore the error data It is preferable to include a logic decoding means.

In the π / 4 QPSK digital demodulation device according to the present invention, the majority decision logic decoding means includes: delay means for delaying the phase difference information obtained by the first phase information detection means by five symbols; The phase difference information delayed by three symbols, four symbols, and five symbols by the delay means and the current phase difference information obtained by the first phase information detecting means are calculated as predetermined module values, and the data of the first calculating means and predetermined module values are calculated. Second computing means for detecting an error by performing a calculation; Third calculating means for sequentially calculating the error value obtained by the second calculating means and the error value inputted by the predetermined module with a predetermined module and outputting two symbol delays; Fourth calculating means for calculating and delaying the previous error value delayed by two symbols in the third calculating means and the error value inputted back into a predetermined module value; Threshold determination means for judging the error values obtained by the third and fourth calculation means and the error values input by the second calculation means with threshold values and inputting them to the third and fourth calculation means; And decoded data output means for outputting the decoded data by calculating the error value obtained from the threshold value determining means and the phase difference information obtained from the delay means into predetermined module values.

Hereinafter, preferred embodiments of the π / 4QPSK digital demodulation device according to the present invention will be described in detail with reference to the accompanying drawings.

FIG. 3 is a block diagram illustrating an exemplary embodiment of the present invention π / 4 QPSK demodulation device, and FIG. 4 is a block diagram showing the error correction device of FIG. 3 in more detail. Q-channel and I-channel signals by mixing the band pass filter 301 for removing unnecessary signals from the input QPSK modulated signal, the modulated signal received by the band pass filter 301 and the previous one symbol delayed modulated signal. Channel separation unit 302 and the Q and I channel signals separated by the channel separation unit 302, and the carrier component to block the first and second to extract only the baseband signal of orthogonal and in-phase components Baseband signals of the Q channel and the I channel through the low pass filter units 303 and 304, and the first and second low pass filter units 303 and 304, respectively, are first and second sampling units 305a. Sampling through the first and second determination units 305b and 306b. First and second data restorers 305 and 306 for reconstructing the data by reconstructing the data, a parallel / serial converter 307 for converting and outputting the two pieces of restored data in series, and parallel / serial conversion. An error correction unit that obtains three phase difference information based on the current serial data and previous data converted by the unit 307, sequentially delays and calculates the error value, and determines two thresholds of the calculated error values. 308.

In the above description, the channel separator 302 includes a first symbol delayer 302a for delaying and outputting a modulated signal input from the bandpass filter 301 by one symbol, and the one symbol delayed signal and the bandpass. A first mixing unit 302c for mixing the modulated signals of the filter unit 301 to extract a Q channel signal, a phase shifting unit 302b for phase shifting the symbol delayed signal by? / 2, and the phase A second mixing unit 302d extracts an I-channel signal by mixing the modulation signal phase shifted by the transition unit 302b and the modulation signal of the band pass filter 301.

The error corrector 308 compares the data obtained by the parallel / serial converter 307 with the symbol delayed data through the second symbol delayer 30 in the first phase comparator 33 to obtain phase difference information. The second phase comparator 34 compares the current data obtained by the phase information detector 308a and the parallel / serial converter 307 with the data delayed by two symbols through the third symbol delayer 31 to compare the phase difference information. The third phase comparator 35 compares the current data obtained by the second phase information detector 308b and the parallel / serial converter 307 with the six-symbol delayed data through the fourth symbol delayer 32. The third phase information detector 308c for obtaining the phase difference information and the phase information obtained from the second phase information detector 308b are delayed by one symbol through the fifth symbol retarder 36, and the delayed phase difference information and the third phase information. Current phase obtained by detector 308c The first operation unit 308d for restoring the data of the parity characteristic by calculating the information to the eight module values in the first modular 37 and the phase information obtained by the first phase information detection unit 308a are delayed step by step. And a majority decision logic decoding unit 308e that sequentially calculates the values and the operation values of the first calculating unit 308d to predetermined 8 module values to determine the threshold of the error and to restore and output the error data.

The majority decision logic decoding unit 308e includes a delay unit 38 which delays and outputs the phase difference information obtained by the first phase information detection unit 308a by five symbols through the sixth to tenth symbol delayers 38a to 38e, The delay unit 38 calculates three-, four-, and five-symbol delayed phase difference information and the current phase difference information obtained by the first phase information detection unit 308e as 8 module values in the second modular 39a, and calculates the result. The second operation unit 39 which detects an error by calculating the data of the first operation unit 308d and the eighth module value by the third modular 39b, and the error value obtained by the second operation unit 39 and the error value fed back. Is sequentially calculated from the fourth to sixth modulars 40a, 40c, and 40d into eight module values, and a third symbol delay output is performed through the eleventh and twelfth symbol delayers 40b and 40e. To the seventh modular 41a inputted by being fed back to the operation unit 40 and the previous error value delayed by two symbols by the third operation unit 40. Computed by the eighth module value and outputted by delaying three symbols through the thirteenth to fifteenth symbol delayers 41b to 41d, and the third and fourth computational units 40 and 41. A threshold value determination unit 42 for determining the error value and the one-bit error value input from the second operation unit 39 with a threshold value, and inputting the error value to the third and fourth operation units 40 and 41; The eighth modular 43 outputs the decoded data to the output terminal 309 by calculating the error value determined by the threshold determination unit 42 and the phase difference information delayed by the delay unit 38 to eight module values.

The π / 4 QPSK digital demodulation method and apparatus of the present invention configured as described above operate as follows.

First, when a QPSK modulated signal is input from the reception input terminal 300, the band pass filter 301 removes an unnecessary signal from the input modulated signal and provides it to the channel separator 302.

The channel separator 302 mixes the received modulated signal and the previous one symbol delayed modulated signal, separates them into Q channel and I channel signals, and provides them to the first and second low pass filter units 303.

The channel separator 302 includes a first symbol delayer 302a, first and second mixers 302c, 302d, and a phase shifter 302d.

Accordingly, the received modulated signal is input to the first mixer 302c and delayed by one symbol through the first symbol delayer 302a of the channel separator 302, and π / 2 in the phase shifter 302b. Phase shifted by the amount provided to the second mixing section 302d.

The first mixer 302c mixes the current modulated signal received by the bandpass filter 301 and the modulated signal delayed by one symbol in the first symbol delayer 302a to extract the Q channel signal, and then performs the second mixer. The unit 302d mixes the modulated signal of the band pass filter 301 and the modulated signal phase shifted by π / 2 in the phase shifter 302b to extract the I channel signal.

The extracted quadrature component Q and the in-phase component I signal are provided to the first and second low pass filter units 303 and 304, respectively.

The first and second low pass filter units 303 and 304 block carrier components of the first and second mixing units 302c and 302d, and the basebands of quadrature and in-phase components, i.e., Q and I channels. Extract only the signal.

The extracted baseband signals of the Q channel and the I channel are sampled by the first and second sampling units 305a and 306a of the first and second data restoration units 305 and 306, respectively. Sampling data is determined by the second determination units 305b and 306b and input to the parallel / serial conversion unit 307.

The parallel / serial converter 307 converts the parallel data of the input Q channel and the I channel into serial and inputs them to the error correction unit 308.

The error correction unit 308 obtains three phase difference information based on the converted serial input current and previous data, sequentially delays and associates them, and determines the threshold of the calculated error value. Will be corrected.

That is, the error correction unit 308 is the first, second, third phase information detection unit 308a, 308b, 308c and the first operation unit 308d and the majority decision logic decoding unit as shown in FIG. 308e).

Accordingly, the serial data converted by the parallel / serial converter 307 is the second, third, and fourth symbol delayers of the first, second, and third phase information detectors 308a, 308b, and 308c. One, two, and six symbol delays are input to the first, second, and third phase comparators 33, 34, and 35, respectively, via (30), (31), and (32).

The first phase comparator 33 compares the current serial data with one symbol delayed data to obtain phase difference information, and the second phase comparator 34 compares the current serial data with two symbol delayed data to obtain phase difference information. The third phase comparator 35 compares the current serial data with the six symbol delayed data to obtain a phase difference.

The phase difference information obtained by the first phase difference detector 308a is provided to the majority vote logic decoder 308e to be described later.

The phase difference information obtained by the second phase information detector 308b is delayed by one symbol in the fifth symbol delay unit 36 of the first operator 308d, and the third phase information detector 308c in the first modular 35. After calculating the phase difference information and the 8 module values, the majority decision logic decoder 308e is provided.

The majority decision logic protection unit 308e delays the phase information obtained by the first phase information detection unit 308a step by step, sequentially calculates the delayed values and the operation value of the first operation unit 308d into 8 module values, and then generates an error threshold. The error data is restored and outputted.

That is, the majority decision logic decoding unit 308e includes a delay unit 38, second, third, and fourth operation units 39 to 41, a threshold value determining unit 42, and an eighth modular unit as shown in FIG. And a decoded data output unit as shown in (43).

Accordingly, the delay unit 38 delays the phase difference information detected by the first phase information detector 308a through the sixth to tenth symbol delayers 38a to 38e by five symbols to be described later. 43) and the three- and four-symbol delayed phase difference information is provided to the second modular (39a) of the second operation unit (39).

The second modular 39a of the second calculator 39 uses the current phase difference information obtained by the first phase information detector 308a and the phase difference information delayed by three symbols, four symbols, and five symbols from the delay unit 38 by eight module values. After calculating the error value to provide a third modular (39b).

The third modular 39b calculates the error value obtained by the second modular 39a and the error value obtained by the first calculating unit 308d into eight module values, and provides them to the third calculating unit 40 and the threshold value determining unit 42. do.

The error value inputted to the third operation unit 40 and the error value fed back by the threshold value determination unit 42 are subtracted from the fourth modular 40a to 8 module values and then through the eleventh symbol delayer 30b. One symbol delay is provided to the fifth and sixth modulars 40c and 40d.

The fifth modular 40c calculates an error value fed back from the threshold determination unit 42 and an error value through the eleventh symbol delayer 40b as an eight module value and converts the calculated error value into a twelfth symbol. The delay is delayed through the delay unit 40e and provided to the threshold value determining unit 42 and the fourth calculating unit 41.

The 13 th to 15 th symbol delay units 41b after the error value input from the fourth calculating unit 41 is calculated from the error value inputted from the threshold value determining unit 42 and the 8 module value in the seventh modular 41a. To 41d), and is provided to the threshold value determining unit 42.

Meanwhile, the sixth modular 40d of the third calculator 40 calculates an error value delayed by two symbols by the fourth calculator 41 and an error value delayed by the eleventh symbol delayer 40b as eight module values, and thus the threshold plate. Provided to the government 42.

The threshold value determining unit 42 determines that the output is n when three or four inputs from the second, third, and fourth calculating units 39, 40, and 41 are n at the same time, and the error data is described above. The eighth modular 43 is provided.

The eighth modular 43 subtracts the phase difference information delayed by the delay unit 38 and the error value determined by the threshold determination unit 42 into eight module values, so that the two pieces of error data are corrected as shown in FIG. 6. It is output through the output terminal 309.

On the other hand, as a comparative example, a conventional complex, i.e., a clock recovery unit for recovering how much error the symbol rate clock used on the transmission side has and a separate complex hemming code for correcting errors from the modulated signal Unlike the error correction circuit using the BCH code, it can be seen that the hardware can simply correct the two errors by connecting a demodulation circuit to the rear end of the differential detector.

As a result, according to the present invention, it can be seen that an effect equal to or higher than that of the conventional one can be obtained while simplifying the configuration of the π / 4 QPSK demodulator.

As described above, in the present embodiment, the differential detection method, which is resistant to fading, easy to construct, and stable on the π / 4 QPSK demodulation system, employs a parity characteristic of differential detection to improve error data correction. It can be done.

According to the π / 4 QPSK digital demodulation device of the present invention as described above, by adopting a differential detection method on the π / 4 QPSK demodulation system, it is possible not only to correct one error data without a conventional error correction circuit, but also a circuit of a demodulation device. There is an effect that can be simplified.

Claims (14)

A digital demodulation method of a QPSK receiver for receiving a signal modulated with digital data by a QPSK method and separating and demodulating the I channel signal and the Q channel signal by a local carrier synchronized with the transmitting side. Extracting phase information of the I channel signal and the Q channel by mixing one symbol delayed reference signal; Restoring data by sampling phase information of the extracted I and Q channels; Converting the restored I-channel and Q-channel data into serial data; Restoring basic data based on the converted serial data and data previously delayed by a first predetermined symbol unit; Restoring data of a parity characteristic having correlation between the data based on the converted serial data and data previously delayed in units of second and third predetermined symbols; Sequentially delaying the restored basic information data and data of parity characteristics in symbol units and determining a threshold of the delay value; And calculating the error of the data by calculating the error value of the determined threshold value with a predetermined module value. The method of claim 1, wherein the data restoration process comprises: restoring basic information data by comparing a phase difference between the converted serial data and previous data delayed by one symbol; Restoring the data of the parity characteristic by comparing a phase difference between the converted serial data and previous data delayed by two symbols; And restoring the data of the parity characteristic by comparing the phase difference between the converted serial data and the previous data delayed by six symbols. 4. The method according to claim 1, wherein the delayed first predetermined symbol is one symbol. The π / 4 QPSK digital demodulation method according to claim 1, wherein the delayed second and third predetermined symbols are 2 symbols and 6 symbols. 4. The π / 4 QPSK digital demodulation method according to claim 1, wherein the predetermined module value is eight. QPSK receiver that receives signals modulated with digital data by QPSK method, separates I-channel signals and Q-channel signals by local carriers synchronized to the transmitter, and converts and demodulates the signals through low-pass filters to digital. A digital demodulation device comprising: a bandpass filter for removing an unnecessary signal from an input QPSK modulated signal, a Q channel and an I channel signal by mixing a modulation signal received by the bandpass filter and a previous symbol delayed modulation signal A first and second low pass filter devices for separating carrier signals from the signals of the Q and I channels separated from the channel separator and extracting only the baseband signals of quadrature and in-phase components; And second data restoration for determining and restoring data by sampling the baseband signals of the Q channel and the I channel through the second low pass filter device, respectively. Value, a parallel / serial converter for converting the restored two data into serial and outputting the three phase difference information based on the converted current serial data and previous data, and sequentially delaying and calculating the calculated A π / 4 QPSK digital demodulator comprising an error correction device for correcting two errors by determining a threshold of values. 7. The apparatus of claim 6, wherein the channel separator comprises: a first symbol delay means for delaying the modulated signal inputted from the band pass filter by one symbol, and outputting the one symbol delayed signal and the modulated signal of the band pass filter; A first mixing means for extracting a signal of a Q channel by mixing a phase shifter, a phase shifting means for phase shifting the one symbol delayed signal by? / 2, and a modulation signal phase shifted by the phase shifting means and the band pass filtering device And? Second QPSK digital demodulator, comprising second mixing means for mixing the signals to extract the signals of the I channel. 7. The apparatus of claim 6, wherein the first and second data restoring apparatuses comprise: first and second sampling the baseband signal of the Q channel and the baseband signal of the I channel respectively filtered by the first and second low pass filter devices. 2. A π / 4 QPSK digital demodulation device comprising a sampling device and first and second determination devices for determining respective data sampled by the first and second sampling devices. 7. The apparatus of claim 6, wherein the error correcting apparatus comprises: first phase information detecting means for obtaining a phase difference based on data obtained by the parallel / serial converter and previous first predetermined symbol delayed data; Second phase information detection means for obtaining a phase difference based on the current data obtained at < RTI ID = 0.0 > and < / RTI > the previous second predetermined symbol delayed data, based on the current data obtained at the parallel / serial conversion device and the previous third predetermined symbol delayed data. A predetermined symbol delay of the phase information obtained from the third phase information detecting means and the second phase information detecting means and obtaining the delayed phase information and the current phase information obtained from the third phase information detecting means. A first calculation means for restoring the data of the parity characteristics by calculating with a value, and the phase information obtained by the first phase information detection means. Π / 4 characterized by including a plurality of logic decoding means for delaying stepwise and sequentially calculating the delayed values and the operation value of the first operation means to a predetermined module value to determine the threshold of the error and to restore the error data. QPSK Digital Demodulator. 10. The apparatus of claim 9, wherein the first phase information detecting means comprises: second symbol delay means for outputting the converted serial data by one symbol delay, and comparing the one symbol delayed data with the converted current serial data to obtain a phase difference. A π / 4 QPSK digital demodulation device comprising a first phase comparison means obtained. 10. The apparatus of claim 9, wherein the second phase information detecting means comprises: a third symbol delay means for outputting the converted serial data by two symbol delays, and the second phase information detecting means compares the two symbol delayed data with the current serial data to obtain a phase difference. Π / 4 QPSK digital demodulation device comprising two-phase comparison means. 10. The apparatus of claim 9, wherein the third phase information detecting means comprises: fourth symbol delay means for outputting the converted serial data by six symbol delays, and a sixth symbol delay means for obtaining a phase difference by comparing the six symbol delayed data with the current serial data. Π / 4 QPSK digital demodulation device comprising three-phase comparison means. 10. The apparatus of claim 9, wherein the first phase information calculating means comprises: fifth symbol delay means for delaying one symbol delay output of the phase difference information obtained by the second phase information detecting means, and one symbol delayed phase difference data and three phase information detecting means. A π / 4 QPSK digital demodulation device comprising a first modular operation of calculating the phase information obtained in step 8 into a module value. 10. The apparatus of claim 9, wherein the majority decision logic decoding means comprises: delay means for delaying and outputting the phase difference information obtained by the first phase information detecting means by five symbols; phase difference information delayed by three symbols, four symbols, and five symbol delays, respectively, in the delay means; And second calculation means for detecting an error by calculating the current phase difference information obtained by the first phase information detecting means into eight module values and calculating the result into data of the first calculating means and eight module values, in the second calculating means. A third operation means for sequentially calculating the obtained error value and the error value inputted back into 8 modules and outputting two symbols delay, and the previous error value delayed two symbols by the third operation means and the error value inputted by feedback A fourth calculation means for calculating a value and delaying the output, and the error value obtained from the third and fourth calculation means and the error value input from the second calculation means are determined based on a threshold value. Decoded data for outputting the decoded data by calculating the threshold value means for feedback input to the third and fourth calculation means, the error value obtained in the threshold value determination means, and the phase difference information obtained in the delay means as 8 module values. Π / 4 QPSK digital demodulation device comprising an output means.

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