JPH0888360A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE: To eliminate the decline of the reversing voltage and the variation of a field by a method wherein the wear of a field oxide film is avoided. CONSTITUTION: An insulating film 9 including a silicon nitride film is formed on the surface of the field oxide film 3 of the element isolation region of a semiconductor substrate 2. One or both of a first conductive layer 8 and a second conductive layer 18 on the semiconductor substrate 2 are used as the gate electrodes 8 and 18 of a MOS transistor. In the manufacturing method of a semiconductor device like this, ions are implanted into a channel in order to control the threshold of the MOS transistor by utilizing the insulating film 9 which includes at least a silicon nitride film as a buffer film. The silicon nitride film in the insulating film 9 blocks the movements of heavy metal impurities existing in an interlayer insulating film and suppresses the characteristic variation of the reverse voltage of the field oxide film.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a non-volatile memory and multiple power supplies, and more particularly to a semiconductor device having different gate oxide film thicknesses under gate electrodes formed in a plurality of regions and a method of manufacturing the same. It is about.

[0002]

2. Description of the Related Art FIG. 7 is a plan view of a conventional multi-power semiconductor device having a logic in which EPROMs are mounted together. As shown in the figure, the semiconductor substrate of the semiconductor device 1 is
A first region forming the cell region 10 and, for example, 12.5
A high voltage power supply (HV) region 20 such as V is provided with a second region and a logic region 30 operating with a power supply voltage of 5V is provided as a third region. 16 to 2
The manufacturing process of this semiconductor device will be described with reference to the manufacturing process sectional view shown in FIG. First, a field oxide film 3 having a thickness of 550 nm that separates each region is formed on the surface of a semiconductor substrate 2 such as a silicon semiconductor by the LOCOS method. To form this, a mask is applied to the element formation region on the surface of the semiconductor substrate 2 and heat treatment is performed to form an element isolation region. By forming the field oxide film 3, the semiconductor substrate 2 is separated into the cell region 10, the HV region 20 and the logic region 30 (FIG. 16A). Next, a dummy oxide film 4 having a thickness of about 15 nm is formed in the element region on the surface of the semiconductor substrate 2. Then, a cell region 10 is opened thereon and a photoresist 5 covering the HV region 20 and the logic region 30 is formed.

Using the photoresist 5 as a mask, boron ions are introduced into the cell region 10 at 60 KeV and 3 × 10 ¹² at.
Channel ion implantation 6 under the condition of oms / cm ²
(FIG. 16B). Next, the photoresist 5 is acid-treated and stripped to form a gate oxide film in the cell region 10. After that, the dummy oxide film 4 of the cell is removed by etching by dilute HF treatment. This rare HF treatment is NH ₄ F
And a dilute HF solution containing HF and H ₂ O.
By this processing, the thickness of the field oxide film 3 is reduced (FIG. 17A). Then, a gate oxide film 7 having a thickness of about 25 nm is formed in the element region on the semiconductor substrate 2 by thermal oxidation treatment (FIG. 17B). After forming the gate oxide film 7, a first-layer polysilicon film 8 (hereinafter referred to as a first polysilicon film) is deposited on the element region and the field oxide film by CVD (Chemical Vapor Deposition). Impurities such as phosphorus are thermally diffused into the first polysilicon film 8. An insulating film 9 is formed on the first polysilicon film 8. The insulating film 9 is Si containing a silicon nitride film.
It is composed of a three-layer film of O ₂ / Si ₃ N ₄ / SiO ₂ film (hereinafter referred to as ONO film) (FIG. 18A).

Next, a photoresist 51 is formed on the insulating film 9 and is patterned so that only the cell region 10 is covered, and the HV region 20 and the logic region 3 are formed.
The photoresist above 0 is removed. Using the patterned photoresist 51 as a mask, the insulating film 9 is selectively removed by etching, and further RIE (Reactive Ion Etc) is performed.
The HV region 20 and the logic region 30 of the first polysilicon film 8 are removed by anisotropic etching such as the Hing method. After that, the exposed gate oxide film 7 is diluted with HF.
Etching is removed by the treatment (FIG. 18B). Subsequently, the photoresist 51 on the cell region is removed by acid treatment or the like, and then the dummy gate oxide film 11 having a thickness of about 15 nm is formed on the HV region 20 and the logic region 30 by thermal oxidation or the like.
To form. At this time, an oxide film 13 formed by thermal oxidation is also formed on the sidewall of the first polysilicon film 8 on the cell region 10. Then, a photoresist 52 having a pattern exposing the HV region 20 is formed on the semiconductor substrate 2. Then, using the photoresist 52 as a mask, the HV region 2
Underneath the dummy gate oxide film 11 of 0 (for N channel of HV), 60 KeV of boron ions, 6 × 10 ¹² atoms
Channel ion implantation 12 is performed under the condition of / cm ² (FIG. 19A).

Similarly, the photoresist 5 on the semiconductor substrate 2
After removing 2 by acid treatment or the like, a photoresist 53 having a pattern exposing the logic region 30 is formed on the semiconductor substrate 2. Then, using the photoresist 53 as a mask, the dummy gate oxide film 1 in the logic region 30 is formed.
1 (under 5V N channel), first add 8 boron ions.
Deep implantation is performed under the conditions of 0 KeV and 1.5 × 10 ¹² atoms / cm ² , and then boron ions are implanted at 40 KeV and 2.5
Channel ion implantation 15 is performed by shallow implantation under the condition of × 10 ¹² atoms / cm ² (FIG. 19B). Next, the photoresist 53 is removed by acid treatment, and then the photoresist is formed so as to cover only the cell region 10.
Using this photoresist as a mask, the dummy gate oxide film 11 is removed by dilute HF treatment. After removing the photoresist by acid treatment, a gate oxide film 14 having a thickness of about 18 nm is formed in the HV region 20 and the logic region 30. Next, a photoresist 54 that covers the cell region 10 and the HV region 20 is formed on the semiconductor substrate 2, and the gate oxide film 14 in the logic region 30 is diluted with HF using the photoresist 54 as a mask.
It is removed by processing (FIG. 20 (a)).

Finally, the photoresist 54 is removed by acid treatment, and then the semiconductor substrate 2 is heat-treated to form a gate oxide film with a thickness of about 15 nm on the surfaces of the HV region 20 and the logic region 30. That is, in the HV area 20,
An oxide film is further stacked on the gate oxide film 14 to have a film thickness of 25.
The gate oxide film 16 of about nm is formed, and the logic region 3
0 has a thin thickness of 15 by thermal oxidation of the semiconductor substrate surface.
A gate oxide film 17 having a thickness of about nm is formed. By this method, gate oxide films having different thicknesses are formed. After that, a second-layer polysilicon film (second polysilicon film) serving as a gate electrode material is deposited on the entire surface of the semiconductor substrate 2 by the CVD method, and then this polysilicon film is formed in the same manner as the first polysilicon film. Diffuse impurities such as phosphorus (Fig. 20)
(B)). The first and second polysilicon films 8 and 18 shown in FIG. 20B are patterned to selectively form an impurity diffusion region in the surface region of the semiconductor substrate 2. The drain region 21, the gate oxide film 7 formed between them, and the floating gate 8 thereabove
And the interlayer insulating film 9 thereon and the control gate 18 thereon.
A memory cell composed of and is formed, and the HV region 20 is formed.
Is formed with a source / drain region 22, a gate oxide film 16 formed between the source / drain regions 22, and a gate electrode 18 formed on the gate oxide film 16, and a source / drain region 22 is formed in the logic region 30. / Drain region 23
And a gate oxide film 17 formed between them and a gate electrode 18 formed thereon
A transistor is formed (FIG. 21).

[0007]

Conventionally, in a semiconductor device having a MOS structure, characteristics of a MOS transistor, such as a change in element characteristics, are deteriorated due to the behavior of heavy metal impurities existing in an interlayer insulating film. In addition, in such a conventional semiconductor device, for example, one in which an EPROM is mounted together,
The gate electrodes in the V region and the logic region are both formed of the second polysilicon film. Moreover, since the gate oxide film thickness is different between the HV region and the logic region, in the conventional manufacturing method, the dummy gate oxide film of the cell, the gate oxide film of the cell,
An oxide film peeling process is performed by dilute HF processing for a total of three times on the dummy oxide film in the HV region. Further, by the time the gate oxide film in the logic region is formed, in addition to the above-described three times of dilute HF treatment, peeling of the gate oxide film in the HV region is performed a total of four times.
F processing is performed. As described above, in the conventional method of manufacturing a semiconductor device in which a memory and a logic are mixedly mounted, the field oxide film formed in the element isolation region is inevitably thinned by the repeated rare HF treatment performed in the oxide film stripping step ( Figure 2
0 (a)). Further, the film reduction causes a decrease or variation in the field inversion voltage, which causes a leak between fields.

Further, the receding of the field oxide film causes the fluctuation of the driving force of the transistor and the cause of the leakage of the transistor, which causes the reduction of the yield of the product. In the above-mentioned conventional example, the field oxide film is formed so as to have a film thickness of 550 nm, but the film thickness is reduced to about 300 nm to 400 nm by repeating such rare HF treatment. The present invention has been made under such circumstances, and provides a semiconductor device that blocks the behavior of heavy metal impurities existing in the interlayer insulating film and reduces the characteristic variation of the inversion voltage of the field oxide film. Semiconductor device and its manufacturing that can prevent decrease and variation of field inversion voltage by preventing film reduction of field oxide film even after acid treatment such as treatment, and prevent yield decrease with high reliability The purpose is to provide a way.

[0009]

The present invention is characterized in that an insulating film containing a silicon nitride (Ti ₃ N ₄ ) film is formed on the surface of a field oxide film in an element isolation region of a semiconductor substrate. In addition, in a method of manufacturing a semiconductor device in which one or both of a first conductive layer and a second conductive layer on a semiconductor substrate are used for a gate electrode of a MOS transistor formed on a semiconductor substrate, This first channel ion implantation for threshold control
It is characterized in that an insulating film having at least a silicon nitride film formed on the conductive layer of the second layer is used as a buffer film. That is, the semiconductor device of the present invention comprises a semiconductor substrate, a semiconductor substrate, an element region in a semiconductor substrate having a MOS transistor having a gate oxide film of a predetermined thickness, and a field oxide film separating the element region. The first feature is that it has an element isolation region therein and an insulating film including a silicon nitride film formed on the field oxide film that separates a predetermined element region to form the element isolation region. And

Further, a semiconductor substrate, a first element region in the semiconductor substrate in which a memory cell having a laminated two-layer gate electrode is formed, and a MOS transistor having a gate oxide film of a predetermined thickness are formed. A second element region in the semiconductor substrate, an element isolation region in the semiconductor substrate made of a field oxide film separating the element region, and a field oxide film constituting the element isolation region separating the element region. The memory cell includes an insulating film including at least a silicon nitride film, and the memory cell has a floating gate as a first conductive layer formed on the semiconductor substrate, and an interlayer insulating film on the floating gate. A second conductive layer formed on the semiconductor substrate and a control gate, and the MOS transistor has a gate electrode of the second conductive layer. It is a second feature of being. The insulating film formed on the field oxide film may be formed of an interlayer insulating film provided between the floating gate and the control gate.

A method of manufacturing a semiconductor device according to the present invention comprises the steps of forming a field oxide film on a semiconductor substrate and providing a first element region, a second element region and an element isolation region on the main surface of the semiconductor substrate. Forming a first gate oxide film on the element region of the main surface of the semiconductor substrate; and forming a first conductive layer on the main surface of the semiconductor substrate so as to cover the first gate oxide film. Steps and a second MO using the second conductive layer formed on the semiconductor substrate as a gate electrode.
Removing the first conductive layer and the first gate oxide film thereunder in the second element region where the S transistor is formed, and the first element region of the semiconductor substrate,
A step of forming an insulating film including a silicon nitride film on the second element region and the element isolation region, and using the insulating film as a buffer film in the second element region of the semiconductor substrate, Performing a channel ion implantation for controlling the threshold value of the second MOS transistor formed,
Removing the insulating film in the second element region while leaving the insulating film in the element isolation region; forming a second gate oxide film in the second element region; A step of forming a second conductive layer so as to cover the second gate oxide film, and a first MO formed in the first element region by selectively etching the first conductive layer.
And a step of forming a gate electrode of the S transistor and a step of selectively etching the second conductive layer to form a gate electrode of the second MOS transistor formed in the second element region. It is characterized by In the first element region region, the first conductive layer is a floating gate, and the second conductive layer provided on the floating gate via an interlayer insulating film is a control gate. A step of forming a memory cell having a gate structure may be provided.

[0012]

The silicon nitride film in the insulating film formed on the field oxide film blocks the behavior of heavy metal impurities existing in the interlayer insulating film, and reduces the variation in the inversion voltage characteristics of the field oxide film. Further, since the first conductive layer used for the gate electrode is used as the buffer film, the number of times of the rare HF process associated with the peeling of the dummy gate oxide film can be reduced, and the film loss of the field oxide film is reduced.

[0013]

Embodiments of the present invention will be described below with reference to the drawings. First, a first embodiment will be described with reference to FIGS. 2 to 6 are cross-sectional views of a manufacturing process of a semiconductor device including a high voltage (HV) part of a peripheral circuit including a cell region and a logic part. FIG. 1 shows an HV part including a cell region such as an EPROM. It is a schematic sectional drawing of the semiconductor device which consists of a logic part. As shown in FIG. 1, the semiconductor substrate 2 of this semiconductor device includes an HV portion 40 including a cell region such as an EPROM and having a high voltage power supply such as 12.5V.
And a second region that constitutes the logic section 30 that operates at 5V, for example. The field oxide film 3 is covered with an insulating film 9 including a silicon nitride film. The silicon nitride film in the insulating film covering the field oxide film blocks the behavior of heavy metal impurities existing in the interlayer insulating film, and reduces the characteristic variation of the inversion voltage of the field oxide film. Next, a manufacturing process of the semiconductor device shown in FIG. 1 will be described. A field oxide film 3 having a thickness of about 550 nm that separates each region is formed on the surface of a semiconductor substrate 2 such as a P-type silicon semiconductor by the LOCOS method. That is, an element formation region is masked on the surface of the semiconductor substrate 2 and heat treatment is performed to form an element isolation region. By forming the field oxide film 3, the cell / HV region 40 of the semiconductor substrate 2 is isolated (FIG. 2A).

Next, a dummy oxide film 4 having a thickness of about 15 nm is formed on the element region on the surface of the semiconductor substrate 2 by an oxidation treatment with dry HCl. And on top of that cell / HV
A photoresist 5 having a pattern that opens the region 40 and covers the logic region 30 is formed. Using this photoresist 5 as a mask, boron ions are added to the cell portion of the cell / HV region 40 at 60 KeV, 3 × 10 ¹² atoms / c.
Channel ion implantation 6 for controlling the threshold value of the MOS transistor is performed under the condition of m ² . Then, using a photoresist (not shown) with a new pattern, the cell /
Boron ions of 60 KeV in the HV part of the HV region 40,
Channel ion implantation 12 is similarly performed under the condition of 2.5 × 10 ¹² atoms / cm ² (FIG. 2B). Next, the photoresist 5 is acid-treated and stripped to form the gate oxide film of the cell / HV region 40. Then cell / HV
The dummy oxide film 4 in the region 40 and the logic region 30 is etched and removed by dilute HF treatment. This dilute HF treatment is performed using a dilute HF solution containing NH ₄ F, HF, and H ₂ O. By this treatment, the thickness of the field oxide film 3 is reduced (FIG. 3 (a)). After that, a gate oxide film 19 having a thickness of about 25 nm is formed in the element region on the semiconductor substrate 2 by the oxidation treatment with dry HCl (FIG. 3).
(B)).

After forming the gate oxide film 19, the thickness is about 4
Polysilicon film 8 which is the first conductive layer of 00 nm
(Hereinafter referred to as the first polysilicon film) is deposited on the device region and the field oxide film by the CVD method (FIG. 4).
(A)). Next, impurities such as phosphorus are thermally diffused into the first polysilicon film 8. Next, the photoresist 51 is formed and patterned, and the first polysilicon film 8 in the logic region 30 is removed by anisotropic etching such as RIE. Thereafter, the exposed gate oxide film 19 in the logic region 30 is removed by a dilute HF process (FIG. 4).
(B)). An insulating film 9 including a silicon nitride film is formed on the first polysilicon film 8 and the exposed field oxide film 3 and the semiconductor substrate 2 in the logic region.
The insulating film 9 is a SiO ₂ / Si ₃ N ₄ / SiO ₂ film (ON
(O film). And this ON
The thickness of the O film is about 18 nm / 15 nm / 6 nm (FIG. 5A). Next, a photoresist 52 is formed on the insulating film 9 and patterned to form a cell / H
The V region 40 and the field oxide film 3 covered with the insulating film are covered, and the photoresist on the logic region 30 is removed. Using the patterned photoresist 52 as a mask and the insulating film 9 as a buffer film in the logic region 30 (into a 5V N-channel transistor), first, boron ions are added at 120 KeV and 1.5 × 10 ¹² at.
deep ion implantation under the condition of oms / cm ² and then boron ions at 80 KeV and 2.5 × 10 ¹² atoms / cm ^2.
Channel ion implantation 15 is carried out by shallowly implanting under the condition (FIG. 5B).

Next, the insulating film 9 is selectively removed by etching so that the insulating film 9 on the field oxide film 3 remains, and the insulating film 9 in the logic region 30 is removed (FIG. 6).
(A)). Subsequently, the photoresist 52 is removed by acid treatment or the like, and then a gate oxide film 17 having a thickness of about 15 nm is formed in the logic region 30 by dry HCl oxidation or the like. After that, a second-layer polysilicon film (second polysilicon film) 18 serving as a gate electrode material is deposited on the entire surface of the semiconductor substrate 2 by the CVD method to a thickness of about 400 nm. Then, impurities such as phosphorus are diffused into this polysilicon film as in the first polysilicon film (FIG. 6B). Next, the insulating film 9, the first and second polysilicon films 8 formed on the cell / HV region 40 of the semiconductor substrate 2 and the field oxide film 3,
18 is appropriately patterned to form the gate electrodes of the MOS transistors in each region, and the subsequent steps are performed to form these MOS transistors. At this time, the insulating film 9 directly in contact with the field oxide film 3 is left as it is (FIG. 1).

An EPROM cell is formed in the cell portion of the first area / HV area 40, and a high voltage MO is formed in the HV area.
An S transistor is formed. Further, a transistor having a thin gate oxide film is formed in the logic region 30 of the second region. In the EPROM cell of the cell portion, N ⁺ source / drain regions 21 are formed in the surface region of the semiconductor substrate 2. A floating gate 8 formed of the first polysilicon film is formed with a gate oxide film 19 having a thickness of about 25 nm sandwiching this region. A control gate 18 made of a second polysilicon film is laminated on the floating gate 8 with an insulating film 9 made of an ONO film interposed therebetween. The MOS transistor in the HV section has N ⁺ source /
A drain region 22 is formed, and a gate electrode 8 formed of the first polysilicon film is formed with a gate oxide film 19 sandwiching this region. M of logic area 30
An N ⁺ source / drain region 23 is formed in the OS transistor, and a gate electrode 18 formed of a second polysilicon film is formed with a gate oxide film 17 sandwiching this region. The field oxide film 3 in the element isolation region is covered with an insulating film 9 left by etching. These transistors are covered and protected by an insulating film or a protective film (not shown).

In this embodiment, since the insulating film is used when the channel implantation of the logic region 30 is performed, the use of the dummy oxide film is reduced accordingly, and the characteristic change of the semiconductor device due to the dilute HF treatment is smaller than that of the above-mentioned conventional example. Get smaller. Further, the film loss of the field oxide film is small. Further, the silicon nitride film in the insulating film covering the field oxide film blocks the behavior of heavy metal impurities existing in the interlayer insulating film, and reduces the characteristic variation of the inversion voltage of the field oxide film. In this embodiment, the cell region and the HV region are further formed in one element region 40. That is, a plurality of regions having different functions but the same gate oxide film thickness
Since it can be integrated into one element region, high integration of the semiconductor device is advanced. In this element region 40, for example, a cell array of the memory cell region and a peripheral circuit of the HV region arranged apart from this region are formed. As described above, in the above-described embodiment, the first region (cell / H
Although the gate oxide film thickness of the V region) and the gate oxide film thickness of the second region are different, the present invention can make the gate oxide film thickness the same regardless of which region is formed. For example, the MOS / transistor in the cell / HV region and the MOS transistor in the logic region have a gate film thickness of about 25 nm.
Can be applied to the semiconductor device.

Next, a second embodiment will be described with reference to FIGS. FIG. 7 is a plan view of a logic semiconductor device in which an EPROM is embedded, and FIGS.
FIG. 13 is a cross-sectional view of the manufacturing process of the semiconductor device in which the first region of the PROM cell region, the second region of the HV region including the control circuit thereof, and the third region of the logic region are mounted together;
FIG. 3 is a schematic sectional view of the semiconductor device. FIG. 13 is a characteristic diagram of this semiconductor device. As shown in FIG. 7, the semiconductor device 1 is formed on a semiconductor substrate. The semiconductor substrate is, for example, a cell region 10 in which EPROM cells are formed, and an HV in which a high breakdown voltage MOS transistor (Vpp = 12.5V) is formed. It is composed of a region 20 and a logic region 30. Next, a method of manufacturing this semiconductor device will be described. For example, a field oxide film 3 having a thickness of about 550 nm for separating each element region is formed on the surface of a semiconductor substrate 2 made of a P-type silicon semiconductor or the like by the LOCOS method. The field oxide film is reduced by heat treatment or acid treatment in a later process. To form this, a mask is formed on the surface of the semiconductor substrate 2 excluding the element formation region, and then the element isolation region is provided.

By forming the field oxide film 3, the semiconductor substrate 2 has a cell region 10 in which an EPROM cell is formed and an HV in which a high breakdown voltage MOS transistor (Vpp = 12.5V) is formed as shown in FIG. The elements are separated into the region 20 and the logic region 30. Next, a dummy oxide film with a thickness of about 15 nm is formed in the element region on the surface of the semiconductor substrate 2. Then, the cell region 10 is opened thereon, and a photoresist that covers the HV region 20 and the logic region 30 is formed. Using this photoresist as a mask, boron ions are added to the cell region 10 at 60 KeV and 3
Channel ion implantation (channel implantation) is performed under the condition of × 10 ¹² atoms / cm ² . Next, the photoresist is etched and stripped to form a gate oxide film in the cell region 10. After that, the dummy oxide film of the cell is removed by etching by dilute HF treatment. This dilute HF treatment is performed using a dilute HF solution containing NH ₄ F, HF, and H ₂ O. This is the first acid treatment. By this treatment, the thickness of the field oxide film 3 is reduced. After that, a gate oxide film 7 having a thickness of about 25 nm is formed in the element region on the semiconductor substrate 2 by heat treatment such as dry HCl oxidation.

After forming the gate oxide film 7, the thickness 100
A first-layer polysilicon film 8 (first polysilicon film) having a thickness of nm is deposited on the element region and the field oxide film by CVD. Impurities such as phosphorus are thermally diffused into the first polysilicon film 8. The steps up to this point are the same as the conventional manufacturing steps, and therefore illustration is omitted (see FIGS. 16 and 17). Next, the photoresist 5 is applied to the first polysilicon film 8
It is formed on the upper surface and patterned to cover only the cell region 10. Then, using the photoresist 5 as a mask, the HV region 20 and the logic region 30 of the first polysilicon film 8 are removed by anisotropic etching such as RIE. Thereafter, the exposed gate oxide film 7 is removed by dilute HF treatment (FIG. 8).
(A)). This treatment is the second acid treatment. Next, the photoresist 5 on the cell region is removed by etching, and then on the first polysilicon film 8 in the cell region 10 and H
An insulating film 9 including at least a silicon nitride film is formed on the V region 20 and the logic region 30. Insulating film 9 is Si
It is composed of a three-layer film of O ₂ / Si ₃ N ₄ / SiO ₂ film (ONO film) (FIG. 8B).

Next, a photoresist 51 is formed on the insulating film 9 and patterned to form the cell region 1
0, the logic region 30 and the field oxide film 3 in the element isolation region are covered, and the photoresist on the HV region 20 is removed. By using the patterned photoresist 51 as a mask, boron ions are added to the channel of the transistor in the HV region 20 by using the insulating film 9 as a buffer film.
Channel ion implantation 12 is performed under the conditions of 0 KeV and 6 × 10 ¹² atoms / cm ² (FIG. 9A). After that, the exposed portion of the insulating film 9 is removed by etching using the photoresist 51 as a mask to expose the HV region 20.
After that, the photoresist 51 is removed by etching (FIG. 9).
(B)). Subsequently, the gate oxide film 14 having a thickness of about 18 nm is formed on the HV region 20 by heat treatment such as dry HCl oxidation.
To form. Then, a photoresist 52 having a pattern that covers the cell region 10, the HV region 20 and the field oxide film 3 and exposes the logic region 30 is formed on the semiconductor substrate 2. Then, using the photoresist 52 as a mask and the insulating film 9 in the logic region 30 as a buffer film, boron ions are first supplied at 120 KeV and 1.5 × 10 ¹² ato.
Channel ion implantation 15 is carried out by deeply implanting under the condition of ms / cm ² and then boron ion shallowly under the condition of 80 KeV and 2.5 × 10 ¹² atoms / cm ² .
0 (a)).

Next, the insulating film 9 in the logic region 30 is removed by using the photoresist 52 as it is as a mask. The insulating film 9 on the field oxide film 3 is left. Then, the photoresist 52 is removed by acid treatment (see FIG. 10).
(B)). Then, the gate oxide film 17 having a thickness of about 15 nm is formed in the logic region 30 by thermal oxidation. In the HV region 20, a gate oxide film 17 is further stacked on the gate oxide film 14 to form a gate oxide film 16 having a film thickness of about 25 nm. By this method, gate oxide films having different thicknesses are easily formed. At this time, the gate oxide film 17 having a thickness of 15 nm grows on the semiconductor substrate 2 in the logic region 30 as it is, but since the gate oxide film 14 is already formed on the semiconductor substrate 2 in the HV region 20, the gate oxide film 14 is already formed. Membrane 17
Will grow on it, and this gate oxide film 1
4 and 17 are integrated into a gate oxide film 16 having a thickness of about 25 nm. Then, the second polysilicon film 18 serving as the gate electrodes of the HV region 20 and the logic region 30 is CV
D or the like is deposited to a thickness of about 400 nm. Impurities such as phosphorus are thermally diffused and activated in the second polysilicon film 18 (FIG. 11). This second polysilicon film 18 is patterned and impurities are injected into the semiconductor substrate 2 to form the structure shown in FIG.
The semiconductor device shown in is formed.

In this embodiment, as shown in FIG. 12, the semiconductor substrate 2 is divided into a first region (cell region), a second region (HV region) and a third region (logic region), each of which is a field oxide film. The elements are separated by. The first and second polysilicon films 8 and 18 are appropriately patterned on the semiconductor substrate 2 to form the gate electrodes of the MOS transistors in each region, and the subsequent steps are performed to form these MOS transistors. Cell area 1 of the first area
An EPROM cell is formed at 0, and a high breakdown voltage MOS transistor is formed at the HV region 20 in the second region. A transistor having a thin gate oxide film is formed in the logic region 30 of the third region. Cell area 1
0 EPROM cells are N ^{+ in} the surface region of the semiconductor substrate 2.
Source / drain regions 21 are formed. A floating gate 8 formed of the first polysilicon film is formed with a gate oxide film 7 having a thickness of about 25 nm sandwiching this region. A control gate 18 formed of a second polysilicon film is laminated on the floating gate 8 with an ONO insulating film 9 interposed therebetween. This cell is covered and protected by an insulating film or a protective film (not shown).

In the high voltage MOS transistor of the HV region 20, the N ⁺ source / drain region 22 is formed in the surface region of the semiconductor substrate 2. A gate electrode 18 formed of the second polysilicon film is formed with a gate oxide film 16 having a thickness of about 25 nm sandwiching this region. In the MOS transistor of the logic region 30, the N ⁺ source / drain region 23 is formed in the surface region of the semiconductor substrate 2. A gate electrode 18 formed of the second polysilicon film is formed with a gate oxide film 17 having a thickness of about 15 nm sandwiching this region. In this embodiment, since the dummy oxide film in the HV region 20 and the logic region 30 is not necessary, the number of rare HF treatments can be reduced to 1 time in the HV region 20 and 2 times in the logic region 30 as compared with the conventional case. As a result, the characteristics of the semiconductor device can be maintained as follows.

FIG. 13 is a characteristic diagram showing the characteristics of the second embodiment and the conventional example. According to the present invention, as described in this embodiment, the reduction of the field oxide film is reduced, and as a result, as shown in this figure, for example, the high breakdown voltage (Vpp = Vpp = 20) formed in the HV region 20 (second region). The threshold voltage Vth of the field transistor of 12.5 V) can be sufficiently maintained at a predetermined value. The figure is a characteristic diagram showing the dependency of the threshold value of the field transistor on the number of acid treatments, the vertical axis shows the threshold voltage Vth (V) of the field transistor in the HV region, and the horizontal axis shows the dummy gate oxide film. The number of times (times) of the above-mentioned dilute HF treatment, which is an acid treatment required for peeling and removing the gate oxide film, is shown. The characteristic of this example is that the acid treatment is performed twice. As described above, in the MOS transistor in the HV region, the average value a of the threshold voltage Vth is about 14V, and the variation range of the threshold voltage exceeds the Vpp maximum guaranteed value (13.1V). On the other hand, in the conventional semiconductor device described above, the H
As for the threshold value Vth of the MOS transistor in the V region, the average value b is about 12V, and the range of the variation is smaller than the maximum guaranteed value. The shape (pattern) of a mask made of a photoresist used during the manufacturing process for manufacturing the semiconductor device of the present invention is different from the conventional one.

Next, the mask pattern will be described with reference to FIGS. 14 and 15. FIG. 14 is a cross-sectional view of a semiconductor substrate having a mask according to the present invention and a conventional one, and FIG. 15 is a plan view of a semiconductor substrate having a mask according to the present invention and a conventional mask. It is formed on one semiconductor substrate. As shown in FIG. 14A, conventionally, in the case of performing a process such as ion implantation, for example, when a predetermined element region formed in a P well or the like is opened and another element region is masked, element isolation is performed. The field oxide 3 in the region is not taken into account. Therefore, the photoresist 5 may or may not cover the field oxide film 3, and covers the element isolation region as necessary. However, according to the method of the present invention, since the insulating film 9 including the silicon nitride film is formed on the field oxide film of the semiconductor device, the element isolation region is usually covered with the photoresist 51. Therefore, when processing a predetermined element region formed in the P well or the like, the photoresist 51 is opened for each element region. It is very difficult to accurately align the photoresist with the element isolation region. For example, when the element isolation region C between the adjacent element regions A and B is covered with the photoresist 51, if the photoresist 51 is formed to have the same width as the width D of the element isolation region C, the photoresist 51 becomes the element region A. , B may be slipped and covered.

If ion implantation (channel implantation) or the like is performed in such a state, sufficient ions will not be implanted in the element region and the transistor characteristics will deteriorate. Therefore, when the element isolation region is covered with photoresist, it is formed with a width d (D> d) narrower than the width D of the element isolation region. In this way, the mask 51 does not cover the element region A or B even if the mask pattern is slightly deviated. Although the present invention has been described by using the memory cell in the embodiments, the present invention is not limited to the memory cell, and other elements can be used. In the above-described embodiment, the same polysilicon (second polysilicon film) as the first conductive layer (first polysilicon film) is used as the second conductive layer formed on the semiconductor substrate. But,
The present invention is not limited to this. For example, a first polysilicon film is used for a first gate of a memory cell having a two-layer gate structure of an EPROM, and a second gate formed on the first polysilicon film has a laminated film of a polysilicon film and a molybdenum silicide film formed thereon ( A polycide film) may be used.

According to the present invention, the silicon nitride film inserted between the first polysilicon film and the second polysilicon film when the channel ions are implanted in the transistor using the second polysilicon film as the gate electrode in this way. The use of the insulating film containing the as a buffer film can reduce the dummy oxide film formed for channel ion implantation and the step of peeling the dummy oxide film. Further, the reduction of the field oxide film due to the dilute HF treatment used for peeling the dummy oxide film can be prevented, and the decrease of the field inversion voltage and the variation of the inversion voltage can be prevented from the leak current between the fields. In addition, it can be expected that the electric characteristics of the field transistor are prevented from fluctuating or leaking due to the reduction of the field oxide film.

[0030]

As described above, the threshold ion-controlled channel ion implantation is performed on the gate electrode of the transistor, and the interlayer insulating film between the two-layer gate electrodes is used as the buffer film, so that the conventional buffer is realized. It is not necessary to use the dummy gate oxide film used as the film, and the acid treatment such as diluted HF for peeling the dummy gate oxide film can be reduced. As a result, the reduction of the film thickness of the field oxide film is reduced, so that it is possible to prevent the deterioration of the characteristics such as the decrease and the inversion voltage of the field of the transistor formed on the semiconductor substrate and the deterioration of the yield. Further, the insulating film having the silicon nitride film used as the buffer film is left on the field oxide film as needed, but this silicon nitride prevents the behavior of heavy metal impurities contained in the interlayer insulating film formed on the semiconductor substrate. Since it has a blocking effect, the element characteristics of the MOS transistor due to the behavior of the heavy metal can be prevented. In addition, silicon nitride can reduce the characteristic variation of the inversion voltage of the field oxide film.

[Brief description of drawings]

FIG. 1 is a sectional view of a manufacturing process of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view of the manufacturing process of the semiconductor device according to the first embodiment.

FIG. 3 is a cross-sectional view of the manufacturing process of the semiconductor device according to the first embodiment.

FIG. 4 is a cross-sectional view of the manufacturing process of the semiconductor device according to the first embodiment.

FIG. 5 is a cross-sectional view of the manufacturing process of the semiconductor device according to the first embodiment.

FIG. 6 is a sectional view of the semiconductor device according to the first embodiment.

FIG. 7 is a plan view of a semiconductor device according to a second example and a conventional example.

FIG. 8 is a cross-sectional view of the manufacturing process of the semiconductor device according to the second embodiment.

FIG. 9 is a cross-sectional view of the manufacturing process of the semiconductor device according to the second embodiment.

FIG. 10 is a sectional view of a manufacturing process of a semiconductor device according to a second embodiment.

FIG. 11 is a cross-sectional view of the manufacturing process of the semiconductor device according to the second embodiment.

FIG. 12 is a sectional view of a semiconductor device according to a second embodiment.

FIG. 13 is a characteristic diagram illustrating the dependence of the threshold voltage of the field transistor of the present invention on the number of acid treatments.

FIG. 14 is a cross-sectional view of a semiconductor substrate illustrating a mask pattern in a channel implanter of the present invention and a conventional semiconductor device.

15 is a plan view of the semiconductor substrate of FIG.

FIG. 16 is a sectional view of a conventional semiconductor device manufacturing process.

FIG. 17 is a sectional view of a conventional semiconductor device manufacturing process.

FIG. 18 is a sectional view of a conventional semiconductor device manufacturing process.

FIG. 19 is a sectional view of a conventional semiconductor device manufacturing process.

FIG. 20 is a sectional view of a conventional semiconductor device manufacturing process.

FIG. 21 is a sectional view of a conventional semiconductor device.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 semiconductor device 2 semiconductor substrate 3 field oxide film 4, 11 dummy oxide film 5, 51, 52, 53, 54 photoresist 6, 12, 15 channel ion implantation (channel implantation) 7, 14, 16, 17, 19 gate oxidation Film 8 First polysilicon film 9 Insulating film (SiO ₂ / Si ₃ N ₄ / SiO
₂ : ONO film) 10 cell region 13 polysilicon sidewall oxide film 18 second polysilicon film 20 HV region 30 logic region 40 cell / HV region

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication H01L 21/8247 29/788 29/792 H01L 27/10 434 29/78 371

Claims (5)

[Claims] 1. A semiconductor substrate comprising: a semiconductor substrate; a device region in which a MOS transistor having a gate oxide film having a predetermined thickness is formed; and a field oxide film separating the device region. A semiconductor device comprising: an element isolation region; and an insulating film including a silicon nitride film formed on the field oxide film that separates a predetermined element region to form the element isolation region. 2. A semiconductor substrate, a first element region in the semiconductor substrate in which a memory cell having a laminated two-layer gate electrode is formed, and a MOS transistor having a gate oxide film with a predetermined thickness is formed. A second element region in the semiconductor substrate, an element isolation region in the semiconductor substrate made of a field oxide film separating the element region, and the field forming the element isolation region separating the element region The memory cell includes an insulating film including at least a silicon nitride film formed on an oxide film, and the memory cell has a floating gate on a first conductive layer formed on the semiconductor substrate, and a floating gate on the floating gate. The MOS transistor has a second conductive layer formed on the semiconductor substrate via an interlayer insulating film and a control gate, and the MOS transistor is a gate of the second conductive layer. Wherein a has a electrode. 3. The insulating film formed on the field oxide film is formed of an interlayer insulating film provided between the floating gate and the control gate. The semiconductor device described. 4. A step of forming a field oxide film on a semiconductor substrate and providing a first element region, a second element region and an element isolation region on the main surface of the semiconductor substrate, and the element on the main surface of the semiconductor substrate. Forming a first gate oxide film in the region, forming a first conductive layer on the main surface of the semiconductor substrate so as to cover the first gate oxide film, and forming a first conductive layer on the semiconductor substrate The first conductive layer in the second element region in which the second MOS transistor having the formed second conductive layer as a gate electrode is formed and the first gate oxide film thereunder Removing the insulating layer, forming an insulating film including a silicon nitride film on the first element region, the second element region and the element isolation region of the semiconductor substrate, and forming the insulating layer on the second element region of the semiconductor substrate. Using the insulating film as a buffer film, The formed on the second element region second
Performing channel ion implantation for controlling the threshold value of the MOS transistor, removing the insulating film in the second element region while leaving the insulating film in the element isolation region, and the second element region Forming a second gate oxide film on the semiconductor substrate, forming a second conductive layer on the semiconductor substrate so as to cover the second gate oxide film, and selectively forming the first conductive layer on the semiconductor substrate. A step of etching to form a gate electrode of the first MOS transistor formed in the first element region; and a step of selectively etching the second conductive layer to form a second electrode formed in the second element region. And a step of forming a gate electrode of the MOS transistor. 5. In the first element region, the first conductive layer is used as a floating gate, and the second conductive layer provided on the floating gate with an interlayer insulating film interposed therebetween. 5. The method of manufacturing a semiconductor device according to claim 4, further comprising a step of forming a memory cell having a stacked gate structure that serves as a control gate.