JPH0888162A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH0888162A JPH0888162A JP6223283A JP22328394A JPH0888162A JP H0888162 A JPH0888162 A JP H0888162A JP 6223283 A JP6223283 A JP 6223283A JP 22328394 A JP22328394 A JP 22328394A JP H0888162 A JPH0888162 A JP H0888162A
- Authority
- JP
- Japan
- Prior art keywords
- film
- layer wiring
- layer
- wiring film
- thickness
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
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- Semiconductor Memories (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、０.5μｍ以下のライン
＆スペースを有する半導体装置、特にスタックトキャパ
シタを有するＤ−ＲＡＭのように、第１層目の金属配線
形成時のグローバル段差がキャパシタの高さに依存し、
且つ、第２層目の金属配線を有する半導体装置の製造方
法に関する。BACKGROUND OF THE INVENTION The present invention relates to a semiconductor device having a line & space of 0.5 .mu.m or less, especially a global step when forming a metal wiring of the first layer such as a D-RAM having a stacked capacitor. Depends on the height of the capacitor,
In addition, the present invention relates to a method for manufacturing a semiconductor device having a second layer metal wiring.
【０００２】近年、半導体装置の製造において、高集積
化、微細化により、多層配線の段差に起因する工程の困
難さが増大し、これを克服する技術が必要とされてき
た。In recent years, in the manufacture of semiconductor devices, due to high integration and miniaturization, the difficulty of the process due to the step of the multi-layer wiring has increased, and a technique for overcoming this has been required.
【０００３】[0003]
【従来の技術】図５〜７は従来例の説明図である。図に
おいて、11は半導体ウェーハ、12は下地電極膜、 12aは
蓄積電極、 12bは対向電極、13は下地絶縁膜、14は第１
層配線膜、15はレジストパターン、16はワード線、17は
ビット線である。2. Description of the Related Art FIGS. 5 to 7 are explanatory views of a conventional example. In the figure, 11 is a semiconductor wafer, 12 is a base electrode film, 12a is a storage electrode, 12b is a counter electrode, 13 is a base insulating film, and 14 is a first electrode.
A layer wiring film, 15 is a resist pattern, 16 is a word line, and 17 is a bit line.
【０００４】従来の半導体装置においては、特に、図５
（ｂ）に示すようなスタックトキャパシタを有するＤ−
ＲＡＭにおいて、第１層配線膜14形成時の下地電極12、
或いは下地絶縁膜13の下地層の段差Ｄの高さは、ほぼス
タックドキャパシタのセルのフィンの高さは０．６〜
１．０μｍ程度となり、このことは、第１層配線膜14の
形成時のフォトレジストの露光の焦点深度（Depth of F
ocus) により決定され、実際の量産工程で限界となる焦
点深度余裕度（マージン）の限界までに制限される。In the conventional semiconductor device, in particular, FIG.
D- having a stacked capacitor as shown in (b)
In the RAM, the base electrode 12 when the first-layer wiring film 14 is formed,
Alternatively, the height of the step D of the base layer of the base insulating film 13 is about 0.6 to about 0.6 for the fin height of the cell of the stacked capacitor.
This is about 1.0 μm, which means that the depth of focus of the exposure of the photoresist when forming the first layer wiring film 14 (Depth of F
ocus) and is limited to the limit of the depth of focus margin (margin) which is the limit in the actual mass production process.
【０００５】更に、図５（ａ）に示すようなシリンダキ
ャパシタの場合にはキャパシタのシリンダの高さが図５
（ｂ）に示したフィンキャパシタの２倍程度の高さも
１．２〜２．０μｍもあり、従って下地層の段差Ｄもほ
ぼ１．２〜２．０μｍの高さとなる。Further, in the case of a cylinder capacitor as shown in FIG. 5 (a), the height of the cylinder of the capacitor is as shown in FIG.
The height of the fin capacitor is about twice as high as that of the fin capacitor shown in (b) and 1.2 to 2.0 μm. Therefore, the step D of the underlayer is about 1.2 to 2.0 μm.
【０００６】すなわち、従来の露光焦点深度は第１層配
線膜が１．０μｍ以上のライン＆スペースの配線パター
ンからなる場合においては、従来の焦点深度は２．５μ
ｍ程度であり、焦点深度の余裕度を上下に０．５μｍ程
度を考慮して、キャパシタセルのフィンの高さは１．５
μｍ以下の段差が許容されており、実際のセルの高さも
各種のキャパシタで、１．０μｍ以上が可能である。That is, the conventional exposure depth of focus is 2.5 μm when the first layer wiring film has a wiring pattern of line and space of 1.0 μm or more.
The height of the fin of the capacitor cell is 1.5 m, considering the margin of depth of focus of about 0.5 μm above and below.
A step height of less than μm is allowed, and the actual cell height can be 1.0 μm or more for various capacitors.
【０００７】また、第一層配線膜14の膜厚に関しても、
その配線抵抗の要求値により決められ、かなり厚い膜厚
でも使用可能であった。Regarding the film thickness of the first-layer wiring film 14,
It was determined by the required value of the wiring resistance, and it was possible to use even a considerably thick film thickness.
【０００８】[0008]
【発明が解決しようとする課題】ところが、ライン＆ス
ペースが０.5μｍ以下となり、また、第１層配線膜とし
て高融点金属膜を用いるケースにおいては、その下地層
の段差の高さはフォトレジスト形成時のみならず、第１
層配線膜のエッチング能力にも大きな影響を与えること
がわかってきた。However, in the case where the line & space is 0.5 μm or less and the refractory metal film is used as the first layer wiring film, the height of the step of the underlying layer is the photoresist. Not only at the time of formation, but also the first
It has been found that the etching ability of the layer wiring film is also greatly affected.
【０００９】また、高融点金属によって形成された第１
層配線膜の膜厚が０.5μｍを越えると、第１層配線膜間
の電流リークが生じること、及びその上に形成された第
２層配線膜のリーク電流の増大や歩留りの低下等の影響
を与えることも判ってきた。すなわち、図６の左に示す
ような下地電極膜の高さが０．５μｍ以下の場合に対し
て、図６の右に示すような１.0μｍ以上の下地電極膜の
高さを有する時には、段差の部分においてその上にパタ
ーニングされた第１層配線膜のエッチング残渣を生じ、
第１層配線膜間のショートを引き起こす原因となる。Also, the first element formed of a refractory metal
When the film thickness of the layer wiring film exceeds 0.5 μm, current leakage between the first layer wiring films occurs, and the leakage current of the second layer wiring film formed thereon increases and the yield decreases. It has become clear that it will have an impact. That is, when the height of the base electrode film is 0.5 μm or less as shown on the left of FIG. 6, when the height of the base electrode film is 1.0 μm or more as shown on the right of FIG. In the step portion, an etching residue of the patterned first layer wiring film is generated on the step portion,
This causes a short circuit between the first layer wiring films.
【００１０】また、図７（ａ）に示すような、ライン＆
スペースが１μｍの場合に従来用いてきた１.7μｍ程度
のフォトレジスト膜の膜厚では、０.5μｍ以下のライン
＆スペース形成時ではレジストパターン15の抜き幅のア
スペクト比が図７（ｂ）に示すように、３を越え、レジ
ストパターン15が倒れるといった現象も起こっている。Further, as shown in FIG. 7A, the line &
With a photoresist film thickness of about 1.7 μm, which has been conventionally used when the space is 1 μm, the aspect ratio of the blank width of the resist pattern 15 is shown in FIG. 7 (b) when a line & space of 0.5 μm or less is formed. As shown, there is also a phenomenon that the resist pattern 15 falls over 3 and falls.
【００１１】すなわち、フォトリソグラフィ工程にてフ
ォトレジスト膜を塗布するが、ここで、そのフォトレジ
スト膜の膜厚による第１層配線膜14の形成時には図７に
示すような問題点が生じていた。すなわち、この時、
１．５μｍ以上の膜厚のフォトレジストではレジストパ
ターン倒れが発生し、第１層配線膜間のショートが発生
する。That is, the photoresist film is applied in the photolithography process. However, when the first layer wiring film 14 is formed due to the thickness of the photoresist film, a problem as shown in FIG. 7 occurs. . That is, at this time,
In a photoresist having a film thickness of 1.5 μm or more, the resist pattern collapses, causing a short circuit between the first-layer wiring films.
【００１２】更に、０.5μｍ以上の第１層配線膜14につ
いては、従来用いてきたＣＶＤによる層間絶縁膜や、薄
いＳＯＧ膜においては、第１層配線膜14の端部の絶縁膜
形状に起因するフォトレジスト膜の膜厚の増大が、第１
層配線膜14と同様に、アスペクトの増大によるレジスト
パターン倒れを引き起こす。Further, for the first layer wiring film 14 having a thickness of 0.5 μm or more, the interlayer insulating film formed by CVD which has been used conventionally, and for the thin SOG film, the shape of the insulating film at the end of the first layer wiring film 14 is used. The increase in the thickness of the photoresist film caused by
Like the layer wiring film 14, the resist pattern collapses due to an increase in aspect.
【００１３】本発明は、上記の問題点に鑑み、０．５μ
ｍ以下のライン＆スペースを有する半導体装置の第１層
配線膜の形成時の下地層の段差等に起因する障害を克服
する各種膜厚の限界値を設定し、高品質のデバイスを得
ることを目的として提供される。In view of the above problems, the present invention provides 0.5 μm.
In order to obtain a high quality device by setting limit values of various film thicknesses to overcome obstacles caused by a step of the underlying layer when forming the first layer wiring film of a semiconductor device having a line & space of m or less. It is provided for the purpose.
【００１４】[0014]
【課題を解決するための手段】図１は本発明の原理説明
図である。図において、１は半導体ウェーハ、２は下地
電極膜、３は下地絶縁膜、４は第１層配線膜、５は第１
層配線膜形成用フォトレジスト膜である。FIG. 1 is a diagram for explaining the principle of the present invention. In the figure, 1 is a semiconductor wafer, 2 is a base electrode film, 3 is a base insulating film, 4 is a first layer wiring film, 5 is a first
It is a photoresist film for forming a layer wiring film.
【００１５】前述したように、半導体デバイスの多層配
線において、キャパシタセル等の下地電極や下地絶縁膜
等の下地層の段差Ｄの高さは、微細パターンの第１層配
線膜４を形成するための第１層配線膜形成用レジスト膜
５の露光の焦点深度Ｂにより決定され、実際の量産工程
で限界となる焦点深度のマージンＣの限界まで、その高
さが制限されることとなる。As described above, in the multi-layer wiring of the semiconductor device, the height of the step D of the base electrode such as the capacitor cell or the base layer such as the base insulating film forms the first-layer wiring film 4 having a fine pattern. The height is limited to the limit of the margin C of the depth of focus, which is determined by the depth of focus B of the exposure of the first layer wiring film forming resist film 5 and becomes a limit in the actual mass production process.
【００１６】すなわち、図１に示すように、露光装置の
焦点深度Ａそのものは露光技術とフォトレジスト膜のパ
ターンの線巾により決まるものであるが、或る点におい
てパターン寸法が、細くなったり太くなったり変形した
りせず、一定の適正範囲に内に形成出来る焦点深度であ
る露光焦点深度Ｂは下地層の段差Ｄと量産余裕度（ばら
つきの許容範囲）Ｃとの和であり、例えば０．４±０．
０４μｍ巾のレジストパターンが形成出来る焦点深度の
量が２．０μｍであれば、量産時のばらつきである量産
余裕度Ｃを上側Ｃ1 と下側Ｃ2 に０．５μｍづつ、合わ
せて１．０μｍとすれば、下地層の段差Ｄは焦点深度Ａ
から量産余裕度Ｃを差し引いた露光焦点深度Ｂの１．０
μｍより低く例えば０．９μｍ以下にする必要がある。That is, as shown in FIG. 1, the focal depth A of the exposure apparatus itself is determined by the exposure technique and the line width of the pattern of the photoresist film, but at a certain point, the pattern dimension becomes thin or thick. The exposure depth of focus B, which is the depth of focus that can be formed within a certain appropriate range without being deformed or deformed, is the sum of the step D of the underlayer and the mass production margin (allowable range of variation) C, for example, 0. .4 ± 0.
If the depth of focus capable of forming a resist pattern having a width of 04 μm is 2.0 μm, the mass production margin C, which is a variation at the time of mass production, is 0.5 μm on the upper side C 1 and the lower side C 2 and is 1.0 μm in total. Then, the step D of the underlayer is the depth of focus A
1.0 of exposure depth of focus B minus mass production margin C
It must be lower than μm, for example, 0.9 μm or less.
【００１７】このように、本発明は、第１層配線膜形成
時の下地層の段差が何μｍであれば、第１層配線膜形成
が可能であるか、また、第１層配線の膜厚が何μｍであ
れば第１層配線膜及び第２層配線膜のリーク問題が解決
できるかを実験的に明らかにし、その限界値を明らかに
することで、第１層配線膜の下地のグローバル段差の許
容値、第１層配線膜のトータル膜厚、また第１層配線膜
形成のためのフォトレジスト膜厚の限界値を示す。ま
た、第２層配線膜のリーク電流を減らす方法について
は、滑らかな下地層の形成のための厚いＳＯＧ膜を使用
する。As described above, according to the present invention, if the step difference of the underlying layer at the time of forming the first layer wiring film is several μm, the first layer wiring film can be formed, and the film of the first layer wiring is formed. By experimentally clarifying how many μm the thickness can solve the leak problem of the first-layer wiring film and the second-layer wiring film, and clarifying the limit value thereof, The allowable values of the global level difference, the total film thickness of the first layer wiring film, and the limit values of the photoresist film thickness for forming the first layer wiring film are shown. As a method of reducing the leak current of the second-layer wiring film, a thick SOG film for forming a smooth underlayer is used.
【００１８】すなわち、本発明の目的は、図１に示すよ
うに、０．５μｍ以下のライン＆スペースの配線パター
ンを有する半導体装置において、第１層配線膜が形成さ
れる下地層の段差Ｄを、第１層配線膜形成用フォトレジ
スト膜の露光焦点深度Ｂ以下にすることにより達成され
る。That is, as shown in FIG. 1, an object of the present invention is to provide a semiconductor device having a line & space wiring pattern of 0.5 μm or less with a step D of a base layer on which a first layer wiring film is formed. , The exposure depth of focus B of the photoresist film for forming the first-layer wiring film or less.
【００１９】[0019]
【作用】上記のように、本発明では０.5μｍ以下のライ
ン＆スペースを有するスタックトキャパシタ形のＤ−Ｒ
ＡＭにおいて、その第１層配線膜の形成時の下地層の段
差を１.0μｍ以下に限定することで、第１層配線膜のフ
ォトレジスト膜の形成や、エッチング性能を向上し、そ
の第１層配線膜そのもののトータル膜厚を０.5μｍとす
ることで、第１層配線膜、及び第２層配線膜間のリーク
電流を下げることが可能となる。As described above, in the present invention, the stacked capacitor type D-R having a line & space of 0.5 μm or less is used.
In the AM, by limiting the step difference of the underlayer at the time of forming the first-layer wiring film to 1.0 μm or less, the photoresist film of the first-layer wiring film and the etching performance are improved. By setting the total film thickness of the layer wiring film itself to 0.5 μm, it becomes possible to reduce the leak current between the first layer wiring film and the second layer wiring film.
【００２０】また、第１層配線膜形成時のフォトレジス
ト膜の膜厚を１.5μｍ以下にすることで、レジストパタ
ーンのアスペクト比を軽減し、レジストパターン倒れを
防止する。但し、この技術はエッチング時のレジストア
ッシングレートに大きく影響するため、第１層配線膜の
トータル膜厚制限と併せて用いることが必要となる。Further, by setting the film thickness of the photoresist film at the time of forming the first layer wiring film to 1.5 μm or less, the aspect ratio of the resist pattern is reduced and the collapse of the resist pattern is prevented. However, since this technique greatly affects the resist ashing rate during etching, it is necessary to use it together with the limitation of the total film thickness of the first layer wiring film.
【００２１】更に、第１層配線膜として、１μｍ以上の
膜厚を用いざるを得ない場合においては、問題点となる
第２層配線膜のリーク電流が、第２層配線膜端部のレジ
スト膜厚の変動に起因するものであるから、ＣＶＤ層間
絶縁膜上に厚いＳＯＧ膜を塗布することで、滑らかなフ
ォトレジスト膜の下地を形成し、フォトレジストの膜厚
の変動を極力抑えるという手段を用いることで、リーク
電流の問題を回避することが可能となる。Further, when the film thickness of 1 μm or more must be used as the first layer wiring film, the leak current of the second layer wiring film, which is a problem, is caused by the resist at the end portion of the second layer wiring film. Since it is caused by the fluctuation of the film thickness, a means for forming a smooth underlayer of the photoresist film by applying a thick SOG film on the CVD interlayer insulating film and suppressing the fluctuation of the photoresist film thickness as much as possible. By using, it becomes possible to avoid the problem of leakage current.
【００２２】[0022]
【実施例】図２〜図４は本発明の実施例の説明図であ
る。図において、３は下地絶縁膜、４は第１層配線膜、
６は層間絶縁膜、７は第２層配線膜、８はカバー絶縁
膜、９はＳＯＧ膜である。2 to 4 are explanatory views of an embodiment of the present invention. In the figure, 3 is a base insulating film, 4 is a first layer wiring film,
6 is an interlayer insulating film, 7 is a second layer wiring film, 8 is a cover insulating film, and 9 is an SOG film.
【００２３】一般に半導体デバイスの電極配線パターン
において、高密度、高集積の場合、信号線は極端に密集
して配線する必要があるため、製造技術のレベルぎりぎ
で配線巾及び配線間隔をとるので、配線巾及び配線間隔
が同じ寸法のものを繰り返すパターンが多い。Generally, in the case of high density and high integration in the electrode wiring pattern of a semiconductor device, the signal lines need to be extremely densely wired, so that the wiring width and the wiring interval are set at the limit of the manufacturing technology. In many cases, patterns with the same wiring width and wiring interval are repeated.
【００２４】本発明では、０．５μｍ巾の配線パターン
と０．５μｍ巾の配線間隔を交互に繰り返したパターン
の場合を０．５μｍのライン＆スペースと定義する。本
発明ではライン＆スペースが０．５μｍ以下の配線パタ
ーンに限定して、下地層の段差を露光焦点深度以下とし
ているが、根拠としては、実際にフォトレジストの塗布
膜厚は２μｍ以下の場合が多く、実験的にフォトレジス
トの露光装置の焦点深度（ＤＯＦ）が図２に示すよう
に、焦点深度が２μｍ以下に狭まるのはライン＆スペー
スが０．５μｍ以下の場合となるためである。In the present invention, the case where a wiring pattern having a width of 0.5 μm and a wiring interval having a width of 0.5 μm are alternately repeated is defined as a line and space of 0.5 μm. In the present invention, the line and space is limited to the wiring pattern of 0.5 μm or less, and the step of the underlayer is set to the exposure depth of focus or less. The rationale is that the coating film thickness of the photoresist is actually 2 μm or less. In many cases, the depth of focus (DOF) of the photoresist exposure apparatus is experimentally narrowed to 2 μm or less because the line and space is 0.5 μm or less.
【００２５】本発明の第１の実施例として６４ＭのＤ−
ＲＡＭの多層配線形成プロセスの例を示す。従来例で述
べた図５（ａ）に示すようなシリンダ構造や単純スタッ
ク構造においては２．０μｍ以上の下地段差を有する
が、図５（ｂ）に示すようなフィン構造を有するスタッ
クトキャパシタにおいては第１層配線膜４形成時の下地
層の段差として、約１μｍの下地層の段差を有していた
が、本発明のキャパシタにおいてはフィンの段差を０．
５μｍ以下に抑え、第１層配線膜も０．５μｍ以下とす
ることが必要となる。As a first embodiment of the present invention, a 64M D-
An example of a multi-layer wiring formation process for a RAM will be shown. The stacked capacitor having a fin structure as shown in FIG. 5B has a ground step of 2.0 μm or more in the cylinder structure and the simple stack structure as shown in FIG. 5A described in the conventional example. Has a step of the underlayer of about 1 μm as the step of the underlayer when forming the first layer wiring film 4, but in the capacitor of the present invention, the step of the fin is 0.
It is necessary to suppress the thickness to 5 μm or less and to make the first-layer wiring film also 0.5 μm or less.
【００２６】図３（ａ）の従来例に対比して示す図３
（ｂ）の本発明の実施例では、下地層の段差の状況は図
１や図５で説明したので省略し、下地絶縁膜３上に第１
層配線膜４を形成するところから説明する。FIG. 3 shown in comparison with the conventional example of FIG.
In the embodiment of the present invention in (b), the condition of the step of the underlying layer has been described with reference to FIGS.
The process of forming the layer wiring film 4 will be described.
【００２７】微細パターンのため、第１層配線膜４とし
てポリSi膜やAl膜に代わって、高融点金属配線を用い
る。例えば、スパッタ法によりＴｉ膜を 100〜300 Å、
その後グルーレイヤー（バリア膜）として連続してＴｉ
Ｎ膜を 400〜600 Åの厚さにスパッタ法により形成す
る。Due to the fine pattern, a refractory metal wiring is used as the first layer wiring film 4 instead of the poly-Si film or the Al film. For example, a Ti film of 100 to 300 Å by the sputtering method,
After that, Ti is continuously used as a glue layer (barrier film).
An N film is formed with a thickness of 400 to 600 Å by the sputtering method.
【００２８】続いて、ＣＶＤ法により下地絶縁膜３上の
全面にＷ膜を 3,000〜 4,000Åの厚さに被覆形成する。
またＷ膜のパターニングのために、反射防止膜としてア
モルファスカーボン（α−Ｃ）膜を 500〜600 Åの厚さ
にスパッタ法にて被覆し、フォトリソグラフィ工程に進
める。この時の第１層配線膜４のグローバルの厚さは
０．５μｍ以下となる。Then, a W film is formed on the entire surface of the base insulating film 3 by the CVD method so as to have a thickness of 3,000 to 4,000 Å.
For patterning the W film, an amorphous carbon (α-C) film as an antireflection film is coated to a thickness of 500 to 600 Å by the sputtering method, and the photolithography process is performed. At this time, the global thickness of the first-layer wiring film 4 is 0.5 μm or less.
【００２９】フォトリソグラフィ工程にて第１層配線膜
膜形成用のフォトレジスト膜を塗布するが、ここで、そ
のフォトレジスト膜の膜厚による第１層配線膜４の形成
時には従来例でのべたような図３に示す問題点が生じて
いた。すなわち、この時、１．５μｍ以上のフォトレジ
スト膜ではレジストパターン倒れが発生し、第１層配線
膜４間のショートが発生する。A photoresist film for forming the first-layer wiring film film is applied in the photolithography process. Here, when forming the first-layer wiring film 4 according to the thickness of the photoresist film, the conventional method is used. The problem shown in FIG. 3 has occurred. That is, at this time, the resist pattern collapses in the photoresist film having a thickness of 1.5 μm or more, and a short circuit occurs between the first-layer wiring films 4.
【００３０】この問題は１.5μｍ以下の厚さのフォトレ
ジスト膜を用いる本発明で解消することが可能となる。
この場合、ブランケットＷ膜厚が、4,500 Åを越えると
グルーレイヤーを含めた第１層配線膜４のグローバル膜
厚が０．5 μｍを越えてしまい、対レジスト選択比の問
題からフォトレジスト膜を充分残したままエッチングを
完了することが困難となり、実際の出来上り配線形状が
悪化する。This problem can be solved by the present invention using a photoresist film having a thickness of 1.5 μm or less.
In this case, when the blanket W film thickness exceeds 4,500 Å, the global film thickness of the first-layer wiring film 4 including the glue layer exceeds 0.5 μm, and the photoresist film is not used due to the problem of resist selectivity. It becomes difficult to complete the etching while leaving enough, and the actual finished wiring shape deteriorates.
【００３１】次に、１.0μｍ以上の下地層の段差を有す
る時も従来例の図５で示したように、段差部においてエ
ッチング残渣を生じ、第１層配線膜の間ショートとなっ
てしまう。また、同時に、０.5μｍ程度の段差では問題
ないことも分り、図３（ｃ）に示すような本発明の第２
の実施例のように、ここで０．５μｍの下地層の段差で
抑えられるフィン形キャパシタ以外の、下地層の段差が
１．０μｍにもなるシリンダキャパシタ等を採用する場
合においても、下地層の段差は１.0μｍ以下に抑えるこ
とが必要である。Next, even when there is a step difference of 1.0 μm or more in the underlying layer, as shown in FIG. 5 of the conventional example, an etching residue is generated in the step portion, resulting in a short circuit between the first layer wiring films. . At the same time, it was also found that there is no problem with a step difference of about 0.5 μm, and the second aspect of the present invention as shown in FIG.
In the case where a cylinder type capacitor having a step difference of 1.0 μm in the base layer is adopted other than the fin type capacitor in which the step difference of the base layer of 0.5 μm is suppressed as in the embodiment of FIG. It is necessary to suppress the step to 1.0 μm or less.
【００３２】第１層配線膜形成後、層間絶縁膜６を形成
する。層間絶縁膜６としては、例えば、ＰＥ−ＣＶＤ法
によるＳｉＯＮ膜を 1,000〜2,000 Åの厚さに、続いて
常圧Ｏ3 −ＴＥＯＳ法によるＮＳＧ膜を 6,000〜8,000
Åの厚さに形成する。After forming the first layer wiring film, the interlayer insulating film 6 is formed. As the interlayer insulating film 6, for example, a SiON film formed by PE-CVD method with a thickness of 1,000 to 2,000 Å, and then an NSG film formed by atmospheric pressure O 3 -TEOS method from 6,000 to 8,000.
Form to a thickness of Å.
【００３３】次に、ビアホール窓の開口、及びビアホー
ルのエッチング後に、第２層配線膜７を成膜する。ここ
では、バリアメタル膜としてＴｉＮ膜を 1,000Åの厚さ
に、次にAl膜を１.0μｍの厚さに、反射防止膜としての
ＴｉＮ膜を 350Åの厚さに連続してスパッタ法により形
成する。Next, after the opening of the via hole window and the etching of the via hole, the second layer wiring film 7 is formed. Here, a TiN film as a barrier metal film with a thickness of 1,000Å, an Al film with a thickness of 1.0 μm, and a TiN film as an antireflection film with a thickness of 350Å are successively formed by sputtering. To do.
【００３４】こうして形成した第２層金属配線膜７をエ
ッチングした後、この第２層配線膜７のリーク電流の第
１層配線膜４の膜厚依存性は、図４に示すように、第１
層金属配線膜４の膜厚が０.5μｍより厚い場合が、０.5
μｍより薄い場合に比べてリーク電流が高く、歩留りが
悪くなっている。After the second-layer metal wiring film 7 thus formed is etched, the film thickness dependence of the first-layer wiring film 4 of the leak current of the second-layer wiring film 7 is as shown in FIG. 1
If the thickness of the layer metal wiring film 4 is thicker than 0.5 μm, 0.5
The leakage current is higher and the yield is worse than when the thickness is less than μm.
【００３５】そこで、第２層配線膜７の問題からも第１
層配線膜４のグローバルな膜厚は薄い方が望ましいこと
が分る。すなわち、薄くすることで、第１層配線膜４の
端部での常圧Ｏ3 −ＴＥＯＳ法により形成したＮＳＧ膜
の形状が滑らかになり、レジストの厚膜化を抑制するこ
とができるためである。Therefore, from the problem of the second layer wiring film 7, the first
It is understood that it is desirable that the global film thickness of the layer wiring film 4 is thin. That is, by making the thickness thinner, the shape of the NSG film formed by the atmospheric pressure O 3 -TEOS method at the end portion of the first-layer wiring film 4 becomes smoother, and the thickening of the resist can be suppressed. is there.
【００３６】次に、本発明の第２の実施例として、第１
配線膜４の膜厚が０.5μｍを越える場合の層間絶縁膜６
の形成方法を示す。上記常圧Ｏ3 −ＴＥＯＳ膜成膜後、
ＳＯＧ膜９を 4,000〜5,000 Åの厚さに塗布し、キュア
することで、常圧Ｏ3 −ＴＥＯＳの段差を緩和すること
ができる。Next, as a second embodiment of the present invention, the first
Interlayer insulating film 6 when the film thickness of the wiring film 4 exceeds 0.5 μm
A method of forming the is shown. After forming the atmospheric pressure O 3 -TEOS film,
By applying the SOG film 9 to a thickness of 4,000 to 5,000 Å and curing it, it is possible to mitigate the step difference of the normal pressure O 3 -TEOS.
【００３７】この緩和目的は、図３（ｃ）に示すよう
に、第１層配線膜４が密な場所に対するものではなく、
第１層配線膜４の粗な部分において特に強調される適正
に近い形状により生じた段差によるレジスト膜厚の厚膜
化の防止であり、この段差部において滑らかなＳＯＧ膜
９を形成することが肝心となる。As shown in FIG. 3C, this relaxation purpose is not for a place where the first layer wiring film 4 is dense, but
This is to prevent an increase in the resist film thickness due to a step caused by a shape close to an appropriate shape which is particularly emphasized in the rough portion of the first layer wiring film 4, and a smooth SOG film 9 can be formed in this step portion. It is essential.
【００３８】[0038]
【発明の効果】以上説明したように、本発明によれば、
スタックトキャパシタを有するＤ−ＲＡＭのように、下
地層にセル等の下地電極の段差のある半導体デバイスの
０．５μｍ以下のライン＆スペースを有する第１層配線
膜、及び第２層配線膜のパターン形成に効果を奏し、係
る半導体デバイスの歩留り向上、及び性能向上に寄与す
るところが大きい。As described above, according to the present invention,
In a first-layer wiring film and a second-layer wiring film having a line & space of 0.5 μm or less of a semiconductor device having a step of a base electrode such as a cell in a base layer like a D-RAM having a stacked capacitor. In many cases, it is effective in pattern formation and contributes to improvement in yield and performance of such semiconductor devices.
【図１】 本発明の原理説明図FIG. 1 is an explanatory view of the principle of the present invention.
【図２】 本発明の実施例の説明図（その１）FIG. 2 is an explanatory diagram of an embodiment of the present invention (No. 1)
【図３】 本発明の実施例の説明図（その２）FIG. 3 is an explanatory diagram of an embodiment of the present invention (No. 2)
【図４】 本発明の実施例の説明図（その３）FIG. 4 is an explanatory diagram of an embodiment of the present invention (No. 3)
【図５】 従来例の説明図（その１）FIG. 5 is an explanatory diagram of a conventional example (No. 1)
【図６】 従来例の説明図（その２）FIG. 6 is an explanatory diagram of a conventional example (No. 2)
【図７】 従来例の説明図（その３）FIG. 7 is an explanatory diagram of a conventional example (No. 3)
図において １ 半導体ウェーハ ２ 下地電極膜 ３ 下地絶縁膜 ４ 第１層配線膜 ５ 第１層配線膜形成用フォトレジスト膜 ６ 層間絶縁膜 ７ 第２層配線膜 ８ カバー絶縁膜 ９ ＳＯＧ膜 In the figure, 1 semiconductor wafer 2 underlying electrode film 3 underlying insulating film 4 first layer wiring film 5 first layer wiring film forming photoresist film 6 interlayer insulating film 7 second layer wiring film 8 cover insulating film 9 SOG film
───────────────────────────────────────────────────── フロントページの続き (72)発明者 松永 大輔 神奈川県川崎市中原区上小田中1015番地 富士通株式会社内 (72)発明者 田中 裕之 神奈川県川崎市中原区上小田中1015番地 富士通株式会社内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Daisuke Matsunaga 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited (72) Inventor Hiroyuki Tanaka 1015, Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited
Claims (5)
膜の焦点深度から焦点深度余裕度を差し引いた値を露光
焦点深度と定義した場合、 ０．５μｍ以下のライン＆スペースの配線パターンを有
する半導体装置において、第１層配線膜が形成される下
地層の段差を、該第１層配線膜形成用フォトレジスト膜
の露光焦点深度以下にすることを特徴とする半導体装置
の製造方法。1. When a value obtained by subtracting a depth of focus margin from a depth of focus of a photoresist film at the time of exposing a semiconductor wafer is defined as an exposure depth of focus, a semiconductor device having a wiring pattern of 0.5 μm or less in line & space is provided. A method of manufacturing a semiconductor device, characterized in that a step of a base layer on which a first-layer wiring film is formed is set to be equal to or less than an exposure focal depth of a photoresist film for forming the first-layer wiring film.
ることを特徴とする請求項１記載の半導体装置の製造方
法。2. The method of manufacturing a semiconductor device according to claim 1, wherein the step difference of the underlayer is 1.0 μm or less.
なることを特徴とする請求項１または２記載の半導体装
置の製造方法。3. The method of manufacturing a semiconductor device according to claim 1, wherein the underlayer is a stacked capacitor.
下であることを特徴とする請求項１、２または３記載の
半導体装置の製造方法。4. The method of manufacturing a semiconductor device according to claim 1, wherein the film thickness of the first layer wiring film is 0.5 μm or less.
膜の膜厚が１．５μｍ以下であることを特徴とする請求
項１〜４記載の半導体装置の製造方法。5. The method of manufacturing a semiconductor device according to claim 1, wherein the photoresist film for forming the first layer wiring film has a film thickness of 1.5 μm or less.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6223283A JPH0888162A (en) | 1994-09-19 | 1994-09-19 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6223283A JPH0888162A (en) | 1994-09-19 | 1994-09-19 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0888162A true JPH0888162A (en) | 1996-04-02 |
Family
ID=16795707
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6223283A Withdrawn JPH0888162A (en) | 1994-09-19 | 1994-09-19 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0888162A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6839264B2 (en) | 2002-03-22 | 2005-01-04 | Nec Electronics Corporation | Semiconductor device without adverse effects caused by inclinations of word line and bit line |
| CN112158794A (en) * | 2020-09-04 | 2021-01-01 | 杭州探真纳米科技有限公司 | Method for preparing atomic force microscope probe stepped substrate by adopting plasma etching |
-
1994
- 1994-09-19 JP JP6223283A patent/JPH0888162A/en not_active Withdrawn
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6839264B2 (en) | 2002-03-22 | 2005-01-04 | Nec Electronics Corporation | Semiconductor device without adverse effects caused by inclinations of word line and bit line |
| CN112158794A (en) * | 2020-09-04 | 2021-01-01 | 杭州探真纳米科技有限公司 | Method for preparing atomic force microscope probe stepped substrate by adopting plasma etching |
| CN112158794B (en) * | 2020-09-04 | 2024-03-22 | 杭州探真纳米科技有限公司 | Method for preparing atomic force microscope probe stepped substrate by adopting plasma etching |
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