JPH088695A - Oscillation circuit - Google Patents

Abstract

PURPOSE:To provide the oscillation circuit where the oscillation frequency is easily finely adjusted in an integrated circuit without increasing the number of external parts. CONSTITUTION:Oscillation frequency adjusting resistances 19, 20, and 21 are connected in parallel with the line connecting the output terminal or first inverter circuits 3 and 8 and the input terminal of second inverter circuits 4 and 9, and first inverter circuits 3 and 8, second inverter circuits 4 and 9, and oscillation frequency adjusting resistances 19, 20, and 21 are integrated, and parts of the line to which oscillation frequency adjusting resistances 19, 20, and 21 are connected are connected or disconnected to finely adjust the oscillation frequency of an oscillated clock OUT.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an oscillator circuit, and more particularly to an oscillator circuit suitable for finely adjusting the frequency variation of an oscillation clock.

[0002]

2. Description of the Related Art FIG. 2 is a diagram showing a conventional oscillator circuit.
In FIG. 2, (1), (2), (3), (4), and (5) are P-channel type MOS transistors (hereinafter referred to as PMOS transistors) whose sources are connected to the power supply Vdd. Further, (6), (7), (8), (9) and (10) are N-channel type MOS transistors (hereinafter referred to as NMOS transistors) whose sources are grounded. And PM
The OS transistor (1) and the NMOS transistor (6) are connected in series between the power supply Vdd and the ground to form an inverter circuit A. Similarly, PMOS transistors (2) to (5) and NMOS transistor (7)
(11) are respectively connected in series between the power supply Vdd and the ground to form inverter circuits B, C, D and E. Here, the inverter circuits A, B, C,
D and E are integrated on the integrated circuit chip in a state of being connected in series by mask processing. However, terminals (11) (12) for connecting external parts to the integrated circuit.
(13) are provided and these terminals (11) (1
2) (13) is connected to the input terminals (common gates of PMOS and NMOS transistors) of the inverter circuits A, D and E, respectively. Therefore, in order to protect the inverter circuits A, D, and E from external factors such as electrostatic breakdown, the protection resistors (14), (15), (16) are connected to the terminals (11) (12) (13) and the inverter. Circuit A,
It is inserted between the D and E input terminals. The above is the internal configuration of the integrated circuit. Further, as external parts, (17) is a resistor connected between terminals (11) and (12), and (18)
Is a capacitor connected between the terminals (11) and (13), and the capacitor (18) charges and discharges according to a time constant determined by the resistance value of the resistor (17) and the capacitance of the capacitor (18). The oscillation circuit is configured as described above.

The operation of the oscillator circuit of FIG. 2 will be described below with reference to the waveform diagram of FIG. The power supply voltage Vdd is 5 volts, and the threshold voltage VT of the inverter circuits A, B, C, D and E is 2.5 volts. The solid line in FIG. 3 represents the input terminals of the inverter circuit A, that is, the PMOS and NMO.
The voltage waveform of the common gate of the S transistors (1) and (6) is shown, and the broken line indicates the output terminal of the inverter circuit E, that is, PM.
The voltage waveforms of the common drain of the OS and the NMOS transistors (5) and (10) are shown.

Now, in the initial state when the power source Vdd is turned on, the electric charge is not accumulated in the capacitor (18), so that the voltage of the common gate of the PMOS and NMOS transistors (1) and (6) is 0 volt. That is, the PMOS transistor (3) forming the inverter circuit C is turned on and the NMOS transistor (9) forming the inverter circuit D is turned on. Therefore, the current flowing through the source-drain path of the PMOS transistor (3) flows through the resistor (17) and the capacitor (18) through the drain-source path of the NMOS transistor (9), and
The capacitor (18) charges in the direction of the right arrow according to the time constant. Further, P which constitutes the inverter circuit E
The MOS transistor (5) turns on, and the oscillation clock OU
T is 5 volts (high level).

When the capacitor (18) is further charged and the voltage at the left terminal of the drawing rises and the common gate voltage of the PMOS and NMOS transistors (1) and (6) exceeds the threshold voltage VT at time t1, Inverter circuits A, B, C, D and E perform inversion operation,
The NMOS transistor (8) forming the inverter circuit C is turned on and the PMOS transistor (4) forming the inverter circuit D is turned on. Therefore, the voltage at the right terminal of the capacitor (18) in the drawing rises from 0 volt by + Vdd at once. Along with this, the common gate voltage of the PMOS and NMOS transistors (1) and (6) also rises from the threshold voltage VT by + Vdd all at once to 7.5 volts. At this time, the NMOS transistor (10) forming the inverter circuit E is turned on and the oscillation clock OUT becomes 0 volt (low level).

At the time t1, the charging state of the capacitor (18) is (VT + Vdd + α) volts on the left side of the drawing and Vdd on the right side of the drawing. The above α
Is the resistance (1 to the input terminal of the inverter circuit A
This is the voltage increase due to 4). Therefore, the capacitor (1
The voltage of the terminal on the left side in the drawing of 8) is discharged in the left arrow direction through the resistor (17) and the drain-source path of the NMOS transistor (8) according to the time constant. Then, at time t2, when the common gate voltage of the PMOS and NMOS transistors (1) and (6) drops to the threshold voltage VT, the inverter circuits A, B,
C, D, and E perform an inversion operation, and the PMOS transistor (3) forming the inverter circuit C and the NMOS transistor (9) forming the inverter circuit D are turned on again. Therefore, the voltage of the right terminal of the capacitor (18) in the drawing drops from + Vdd to 0 volt. Along with this, the common gate voltage of the PMOS and NMOS transistors (1) and (6) suddenly drops from the threshold voltage VT by Vdd to −2.5V. At this time, the PMOS transistor (5) forming the inverter circuit E is turned on and the oscillation clock OUT becomes 5 volts.

After that, the current flowing through the source-drain path of the PMOS transistor (3) flows through the resistor (17) and the capacitor (18) into the drain-source path of the NMOS transistor (9), and the capacitor (1
8) starts charging again in the direction of the right arrow according to the time constant. By repeating this operation, 5 volts and 0
It is possible to obtain the oscillation clock OUT that repeats the voltage.

Here, the oscillation frequency of the oscillation clock OUT is, in addition to the resistance value of the resistor (17) and the capacitance of the capacitor (18) externally connected to the integrated circuit, the MOS constituting the inverter circuits A to E. It is determined by the gate length and gate width of the transistor.

[0009]

When it is desired to output the oscillation clock OUT having a predetermined oscillation frequency by using the oscillation circuit of FIG. 2, computer simulation is performed or a breadboard is created as a preparatory work for integration. Therefore, typical values of each element of the oscillation circuit required to obtain the oscillation frequency are obtained in advance. afterwards,
Based on the typical value, the oscillator circuit is integrated on a chip using a mask.

However, even if the oscillator circuit is integrated, the gate width and gate length of the MOS transistors constituting the inverter circuits A to E actually vary,
The actual oscillation frequency often deviates from the ideal oscillation frequency. To correct this oscillation frequency shift,
Since it is almost impossible to redesign the completed integrated circuit due to problems such as cost and design time, it is generally necessary to appropriately select the resistance value of the resistor (17) externally connected to the integrated circuit. Done. However, the resistance (1
Since 7) is a carbon resistor which is commercially available as a discrete component, the resistance value of the resistor (17) is 300 to 60 even if it is the closest resistance value in KΩ unit.
There is a gap of about 0Ω. For example, if the oscillation frequency fluctuates even though the typical value of the resistor (17) is 2.7 KΩ, and the resistance value of the resistor (17) is unavoidably changed within the minimum range, 2.2 KΩ or 3.3 KΩ
There is no choice but to select a resistance value such as. Therefore, the resistance (1
There is a problem that the oscillation frequency cannot be finely adjusted by simply changing the resistance value of 7). In order to realize this fine adjustment of the oscillation frequency, a method of connecting a resistor (17) in KΩ unit with a resistor having a small resistance value in Ω unit in series can be considered.
This causes a problem that the number of external parts increases, resulting in an increase in cost and an increase in size of the oscillation circuit.

Therefore, an object of the present invention is to provide an oscillator circuit which can facilitate fine adjustment of the oscillation frequency inside the integrated circuit without increasing the number of external parts.

[0012]

The present invention has been made to solve the above-mentioned problems, and is characterized in that it has first and second inverter circuits connected in series,
A resistor connected between the input terminal and the output terminal of the first inverter circuit, and a capacitor connected between the output terminal of the second inverter circuit and the input terminal of the first inverter circuit, Oscillation for generating an oscillation clock from the output terminal of the second inverter circuit by operating the first and second inverter circuits in response to charging and discharging of the capacitor performed according to a time constant determined by the resistor and the capacitor. In the circuit, the first
A plurality of oscillation frequency adjusting resistors are connected in parallel to a wire connecting the output terminal of the inverter circuit and the input terminal of the second inverter circuit, and the first and second inverter circuits and the plurality of oscillation frequency adjusting resistors are connected. A resistor is integrated, and the oscillation frequency of the oscillation clock is adjusted by connecting or disconnecting the connection part to which each of the oscillation frequency adjusting resistors is connected.

[0013]

According to the present invention, a plurality of oscillation frequency adjusting resistors are respectively connected in parallel to the connection connecting the output terminal of the first inverter circuit and the input terminal of the second inverter circuit, and the first and second The oscillation frequency of the oscillation clock can be finely adjusted by integrating the inverter circuit and the plurality of oscillation frequency adjusting resistors and connecting or disconnecting the connection part to which each of the oscillation frequency adjusting resistors is connected.

[0014]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. FIG. 1 is a diagram showing an oscillator circuit of the present invention. FIG.
2, the same elements as the elements shown in FIG. 2 are denoted by the same reference numerals, and the description thereof will be omitted. Further, in FIG. 1, the series connection body of the PMOS transistor (3) and the NMOS transistor (8) is a first inverter circuit, P
The series connection of the MOS transistor (4) and the NMOS transistor (9) represents the second inverter circuit.

In FIG. 1, (19) (20) (21)
Are oscillation frequency adjusting resistors, and each is an output of the first inverter circuit, that is, a PMOS transistor (3) and an NMO.
The common drain of the S transistor (8) and the input side of the second inverter circuit, that is, the PMOS transistor (4) and N
It is in a state of being connected in parallel to a connection connecting the common gate of the MOS transistor (9). The resistance values of the oscillation frequency adjusting resistors (19), (20) and (21) are selected from several tens Ω to one hundred and several tens Ω. For example, the resistance values of the oscillation frequency adjusting resistors (19), (20) and (21) are each 1
It is set to 60Ω, 80Ω, and 40Ω.

In this embodiment, the resistance value of the resistor (17) and the capacitance of the capacitor (18) externally connected to the integrated circuit are set to 2.7 kΩ and 56 pF, respectively.
Although it is designed to output the oscillation clock OUT of 2 MHz, the MO generated when the oscillation circuit of FIG. 1 is integrated.
When it is found that the oscillation clock OUT is deviated from 2 MHz due to the variation in the gate length and the gate width of the S transistor, in the oscillation circuit to be integrated thereafter,
The connection portions (metal wires on the integrated circuit chip) corresponding to the oscillation frequency adjusting resistors (19), (20) and (21) may be selectively connected or disconnected. By doing so, the resistance (17) is added to the oscillation frequency adjusting resistor (1
9) (20) and (21) can be selectively connected in series, and the oscillation frequency of the oscillation clock OUT can be easily fine-tuned. Although three oscillation frequency adjusting resistors are used in this embodiment, the number of oscillation frequency adjusting resistors is not limited to three and may be three or less or three or more. The greater the number of oscillation frequency adjustment resistors, the greater the number of connection connections and disconnections, and the finer fine adjustment of the oscillation frequency.

As described above, when the oscillator circuit of FIG. 1 is integrated, the oscillation clock OUT can be obtained without increasing the number of external parts.
It is possible to finely adjust the oscillation frequency of.

[0018]

According to the present invention, when the oscillator circuit is integrated, a plurality of oscillation frequency adjusting resistors are connected to the wiring connecting the output terminal of the first inverter circuit and the input terminal of the second inverter circuit. Since they are connected in parallel, the oscillation clock can be finely adjusted by simply connecting or disconnecting the connection corresponding to each oscillation frequency adjusting resistor in order to adjust the variation in the oscillation clock frequency.

[Brief description of drawings]

FIG. 1 is a diagram showing an oscillator circuit of the present invention.

FIG. 2 is a diagram showing a conventional oscillator circuit.

FIG. 3 is a waveform diagram showing the main waveforms of FIGS. 1 and 2.

[Explanation of symbols]

 (3) (4) PMOS transistor (8) (9) NMOS transistor (17) Resistor (18) Capacitor (19) (20) (21) Oscillation frequency adjustment resistor

Claims (2)

[Claims] 1. A first and a second inverter circuit connected in series, a resistor connected between an input terminal and an output terminal of the first inverter circuit, an output terminal of the second inverter circuit, and the first terminal. A capacitor connected between the input terminal of the inverter circuit and the input terminal of the inverter circuit, and operates the first and second inverter circuits according to charge and discharge of the capacitor performed according to a time constant determined by the resistor and the capacitor. As a result, in the oscillation circuit that generates the oscillation clock from the output terminal of the second inverter circuit, a plurality of wirings are connected to the connection connecting the output terminal of the first inverter circuit and the input terminal of the second inverter circuit. The oscillation frequency adjusting resistors are respectively connected in parallel, and the first and second inverter circuits and the plurality of oscillation frequency adjusting resistors are integrated, By connecting or disconnecting said connection portion, each of the oscillation frequency adjustment resistor is connected,
An oscillation circuit for adjusting the oscillation frequency of the oscillation clock. 2. The oscillator circuit according to claim 1, wherein connection or disconnection of the connection portion is performed by mask processing.