JPH0886838A - Semiconductor testing apparatus equipped with rewrite control - Google Patents

Abstract

PURPOSE: To provide a semiconductor testing apparatus by which a rewrite operation can be controlled on every page, by which the test time is shortened and which is equipped with a rewrite control operation, in the semiconductor testing apparatus which is provided with the simultaneous measuring function of rewritable semiconductor memories such as flash memories or the like. CONSTITUTION: A flip-flop 5 in which the output signal of a quality judgment circuit 1 is applied to a clock input end and in which a fixed-level signal is applied to a data input end, is installed. A flip-flop 11 in which the output signal of the flop-flop 5 is applied to a data input end and in which a clock signal 103 on every page is applied to a clock input end, is installed. A semiconductor testing apparatus equipped with a rewrite control operation is constituted in such a way that a rewrite control part 100 in which an output signal is output as a rewrite inhibition signal 102, is installed. In addition, the semiconductor testing apparatus may be constituted in such a way that a plurality of rewrite control parts 200, 300 which are the same as the rewrite control part 100 are installed according to the number of devices.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a flash memory, etc.
The present invention relates to a semiconductor test apparatus having a simultaneous measurement function of a rewritable semiconductor memory, and particularly to a semiconductor test apparatus having a shortened test time.

[0002]

2. Description of the Related Art A semiconductor tester tests various devices. One of them is a flash EEPROM (Electrically Erasable Program) which is a semiconductor IC memory.
mmableRead Only Memory). Then, in order to improve cost performance, simultaneous measurement is usually performed in which a plurality of measurements are performed simultaneously.

In the flash EEPROM, since the time (number of times) required for writing differs due to the structure of the memory cell, writing is not completed by only the first writing, and the entire device under test is measured depending on the result of writing several times. In general, it is judged whether the quality is good or bad. That is,
With a flash EEPROM, it is not always possible to judge whether the measurement result is good or bad by completing the writing result at the first time.Therefore, what is judged to be a good product for each number of times of writing is collected as a good product that has completed writing, and Other than that, the method of repeatedly writing again, repeating the number of times specified by the specifications, and sequentially determining was adopted.

Further, when a plurality of memories are simultaneously measured by a semiconductor IC test apparatus, the comparison result of each device is fed back to the control circuit as a rewrite prohibition signal for each corresponding channel to prevent an excessive write or write operation. Prevents excessive erasure and improves device measurement reliability.

As described above, in the conventional technique, pass / fail determination is performed for each address, and device measurement is performed while performing the above-mentioned rewriting operation. In recent years, a NAND flash memory has appeared as a type of flash memory. This NAND type is for each page or 1
It is possible to perform pass / fail judgment for each byte and rewrite. It is distinguished from the NOR type in which rewriting is performed for each address as in the past.

FIG. 2 shows a conventional semiconductor test apparatus having a simultaneous measurement function for rewritable semiconductor memories. As shown in FIG. 2, the output signal of the device under measurement is applied to the pass / fail judgment circuit 1. The fail detection signal from the pass / fail judgment circuit 1 is selected by the selector 2 for the corresponding channel according to the device configuration conditions.
For example, a fail signal is selectively output according to the input / output bit configuration of the device such as 4 bits, 8 bits, ... 18 bits.

In the flip-flop 3, this fail signal is latched by the clock ADC 101 for each address. Then, in the AND gate 4, the reference clock M
The logical product is obtained by CLK1. Flip flop 5
In, the high level is fixedly connected to the data input terminal. Then, triggered by the output signal of the AND gate 4, the fail state is stored. In the AND gate 6, the output signal of the flip-flop 5 passes in the write prohibit mode. The selector 7 selects a prohibited channel for the channel. Then, it is timed by the MCLK2 signal in the flip-flop 8 and is output from the rewriting control unit 100 as the inhibition signal (M1) 102.

In the case of simultaneous measurement, an inhibition signal for the number of devices is required, and in addition to the above rewrite control unit 100 for channel 1, 200 for channel 2 and 300 for channel n are provided. .

FIG. 4 shows a flowchart of a control operation for rewriting for each address. As shown in FIG.
After the start (step 501), the initial value (N = 1) of the number of rewrites is set (step 502). next,
A program command is set and a program write operation is performed (step 504). Next, a verify command is set and a verify operation is performed (step 506). If the verification result is not pass, rewriting is performed (step 507). If the rewriting upper limit value (for example, 10 times) is not exceeded, the program command setting routine of step 503 is entered again (step 508). If step 5
If the upper limit value is reached at 08, this device is regarded as failing, and failing ends (step 510).

If the verification result is "pass" in step 507, it is judged whether the test execution address is the final address (step 509). If the final address is not reached, move to the next address (step 5
12) Then, the routine after the start is entered into step 502 and the above operation is repeated. If the final address is reached in step 509, the path end (step 51
It ends with 1).

As described above, in the case of a device in which rewriting is performed for each address, a time-efficient test can be performed. However, when an attempt is made to test a device, such as a NAND flash memory, that operates on a page-by-page basis using the above-described semiconductor test apparatus, the following problems occur. In the conventional semiconductor test apparatus, whether or not rewriting is performed by pass / fail for each address is checked. Therefore, at the end of one page, the result of the address in the middle does not remain. Each control cannot be performed. In addition, when rewriting is performed for each address, the test time is long compared to the case where rewriting is performed collectively for each page. It has such drawbacks.

[0012]

SUMMARY OF THE INVENTION An object of the present invention is to eliminate these drawbacks and to perform rewriting control for each page in a semiconductor test apparatus having a simultaneous measurement function of a rewritable semiconductor memory such as a flash memory. Enable and
An object of the present invention is to provide a semiconductor test device with rewrite control, which shortens the test time.

[0013]

In a semiconductor test apparatus having a pass / fail judgment circuit 1 for applying an output signal of a device under test to detect a failure, an output signal of the pass / fail judgment circuit 1 is applied to a clock input terminal to output data. A flip-flop 5 for applying a fixed level signal is provided at the input end. Then, the output signal of the flip-flop 5 is applied to the data input terminal, and the page-by-page clock signal 10 is applied to the clock input terminal.
A flip-flop 11 for applying 3 is provided. And
A rewrite control unit 100 that outputs the output signal of the flip-flop 11 as a rewrite prohibition signal 102 is provided to configure a semiconductor test device with rewrite control.

Further, a plurality of (200, 300) rewrite control units 100 may be provided in accordance with the number of devices to configure a semiconductor test apparatus with rewrite control.

[0015]

In the flow of the control operation of rewriting for each page, the program command is set, the program write operation is performed (step 504), the verify command is set, and the verify operation is performed (step 506). Then, next, it is determined whether the page is finished (step 601). If the page end has not been reached, the process moves to the next address in the page (step 602) and the program command routine (step 503). If the page end is reached in step 601, it is determined whether the verification result in the page is pass (step 50).
7). If it is not a pass, it will be rewritten. If the upper limit value of rewriting (for example, 10 times) is not exceeded, the program command setting routine of step 503 is entered again. If the upper limit is reached in step 508, this device is considered to have failed, and the failure ends (step 510).

As described above, the determination as to whether or not to perform rewriting is made in page units when the writing of all addresses in the page is completed. Then, if rewriting is necessary, the rewriting operation is collectively performed for each page. Therefore, the entire test time can be shortened as compared with the conventional case where rewriting is performed for each address.

[0017]

Embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows a semiconductor test apparatus with rewrite control, showing an embodiment of the present invention. A circuit for determining pass / fail for each page is provided in the rewrite prohibition control unit, and fail information during execution of one page is held.
At the end of the page, it is determined whether or not a failure has occurred in each device under test, and rewriting is controlled.

As shown in FIG. 1, a flip-flop 5 is provided which applies a pass / fail judgment signal from the device under test to the clock input terminal and applies a high level fixed signal to the data input terminal. The flip-flop 11 applies the output signal of the flip-flop 5 to the data input terminal and applies the page-by-page clock signal PAC 103 to the clock input terminal.
To provide. Then, the output signal of the flip-flop 11 is output as the rewrite inhibition signal (M1) 102. A plurality of channels (200, 300) are provided with the above-described rewrite control unit 100 to configure a semiconductor test device with rewrite control.

FIG. 3 shows a flowchart of a control operation for rewriting for each page. As shown in FIG. 3, after the start (step 501), an initial value (N = 1) of the number of rewrites is set (step 502). Next, a program command is set and a program write operation is performed (step 504). Next, a verify command is set and a verify operation is performed (step 506).

Next, it is determined whether or not the page has ended (step 601). If the page has not reached the end, move to the next address in the page (step 60
2), program command routine (step 503)
Move on to. If the page end is reached in step 601, it is determined whether the verification result in the page is pass (step 507). If it is not a pass, it will be rewritten. If the upper limit value of rewriting (for example, 10 times) is not exceeded, the program command setting routine of step 503 is entered again. If the upper limit is reached in step 508, this device is considered to have failed, and the failure ends (step 510).

If the verify result is "pass" in step 507, it is judged whether the test execution address is the final address (step 509). If the final address is not reached, move to the next address (step 5
12) Then, the routine after the start is entered into step 502 and the above operation is repeated. If the final address is reached in step 509, the path end (step 51
It ends with 1).

As described above, the determination as to whether or not to perform rewriting is made in page units when the writing of all addresses in the page is completed. Then, if rewriting is necessary, the rewriting operation is collectively performed for each page. Therefore, the entire test time can be shortened as compared with the conventional case where rewriting is performed for each address.

In the above embodiment, the clock signal 103 for each page is applied at the end of the page operation, but it is not limited to each page. For example, it may be applied every time the address is completed. In this case, the configuration according to the present invention can cover the conventional operation for each address and operate.

[0025]

Since the present invention is configured as described above, it has the following effects. It is possible to provide a semiconductor test device with rewrite control, which enables rewrite control for each page and shortens the test time in a semiconductor test device having a simultaneous measurement function of a rewritable semiconductor memory such as a flash memory. did it.

[Brief description of drawings]

FIG. 1 is a semiconductor test device with rewrite control showing an embodiment of the present invention.

FIG. 2 shows a semiconductor test apparatus having a simultaneous measurement function of a rewritable semiconductor memory according to the related art.

FIG. 3 shows a flowchart of a control operation for performing rewriting for each page.

FIG. 4 shows a flowchart of a control operation for rewriting for each address.

[Explanation of symbols]

 1 pass / fail judgment circuit 2, 7 selector 3, 5, 8, 11 flip-flop 4, 6 AND gate 100, 200, 300 rewrite controller

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI technical display location G11C 17/00 309 E

Claims (2)

[Claims] 1. A semiconductor test apparatus having a pass / fail judgment circuit (1) for applying an output signal of a device under test to detect a failure, wherein the output signal of the pass / fail judgment circuit (1) is applied to a clock input terminal to output data. A flip-flop (5) for applying a fixed level signal is provided at an input end, an output signal of the flip-flop (5) is applied at a data input end, and a clock signal (1) for each page is applied at a clock input end.
03), a flip-flop (11) is provided, and a rewrite controller (100) that outputs the output signal of the flip-flop (11) as a rewrite inhibit signal (102) is provided. Controlled semiconductor test equipment. 2. The rewriting control unit (1) according to claim 1.
00) according to the number of devices under test (200, 30
0) A semiconductor test device with rewrite control, which is provided and characterized by the above configuration.