JPH088560B2 - Parallel processing type synchronous word detector - Google Patents

Description

The present invention relates to a parallel processing type synchronization word for detecting a synchronization word at high speed by performing parallel processing using a plurality of low speed synchronization word detectors in high speed digital communication. The present invention relates to a detection circuit.

“Prior Art” Conventionally, there is a parallel processing type digital correlation circuit as this kind of circuit, and FIG. 6 shows an example of the configuration in the case of two parallel processing.

1 is an input signal terminal, 2 is an input clock terminal, 3 is a ring counter, 4 is a shift register, 5 and 6 are divided clocks generated by the ring counter 3, 7 and 8 are single digital correlators, and 9 and 10. Is a correlation output signal corresponding to the digital correlators 7 and 8, 11 is a selection circuit for selecting a correlation output signal having a correct clock phase, and 12 is a parallel processing type digital correlation circuit output signal.

FIG. 7 is a time chart for explaining the operation of FIG. 6, where A and B are input signal sequences corresponding to two clock phases, C is an input waveform of the ring counter 3, and D and E are output waveforms. ing.

FIG. 8 is a detailed diagram of the single digital correlator 7 in FIG. 6 (when the register length is 8 bits). Reference numerals 13 and 14 are circuits for determining match / mismatch between the known signal patterns r _{1 to} r ₈ and the input signals s _{1 to} s _8, and 15 is a sum circuit for calculating the sum of the number of matching bits.

The outline of the operation of the conventionally used parallel processing type digital correlation circuit is as follows.

The input signal from the input signal terminal 1 is read into the shift register 4 based on the clock from the input clock terminal 2. The ring counter 3 divides the clock of the input clock terminal 2 (Fig. 6C) to obtain the divided output clocks 5 and 6 (Figs. 7D and 7E) shown in Figs. 7D and 7E. The values of the shift register 4 are input to the single digital correlators 7 and 8 as parallel signals, and are compared with the known signal patterns r _{1 to} r ₈ . The number of matching bits is output based on the comparison result. At this time, the relationship between the clock phase and the input signal phase is
When j = 0 shown in FIG. A, the output signal of the digital correlator 7 is correct. Similarly, when j = 1 shown in FIG. 7B, the output signal of the digital correlator 8 is correct output. . The selection circuit 11 adjusts the relationship between the clock phase and the input signal phase by some suitable method, selects the correct correlator output, and sequentially switches the output signals 9 and 10 to obtain the output signal 12.

Since the serial-parallel converter and the digital correlators 7 and 8 are not separated and integrated as described above, that is, in order to read the signal of the shift register 4 into the digital correlators 7 and 8, the shift register 4 This has to be done before the contents change, and therefore the operating speed of the digital correlators 7 and 8 needs to be equal to that of the shift register 4, which has the following drawbacks. First, the input signal at the input signal terminal 1 shown in FIG. 6 passes through the shift register 4 and the digital correlators 7, 8
Since it is input to the internal shift register, the propagation delay t _pd in the shift register 4 and the digital correlator 7, 8 which is the low speed part
The upper limit operating frequency f _up is limited by the equation (3) due to the setup time t _su of the shift register in the above.

That is, no matter how high-speed shift register is used as the shift register 4, even if t _pd is reduced and the number of parallel low-speed parts is increased, a high-speed input signal with an upper limit operating frequency f _up or more dominated by t _su of the low-speed part There was a drawback that it could not handle.

Further, this conventional circuit has a drawback that it does not have a function of automatically removing the uncertainty of the clock phase.

[Means for Solving the Problems] According to the present invention, an input digital signal sequence is converted into two columns of digital signals by a serial-parallel conversion circuit, and the two columns of digital signals ₁ and ₂ are two rearrangement circuits. Due to
The following two types of layout conversion are performed.

Indicates that the Pi signal (i = 1, 2) is delayed by 1 bit. The output signals P ₁ and P ₂ of this rearrangement circuit are detected by two digital correlators in two kinds of sync words, and are correct based on the two kinds of low speed sync word detection pulses output from these digital correlators. A high-speed sync word detection pulse of clock phase is generated by the sync word detection pulse selection circuit.

In this sync word detection pulse selection circuit, a high-speed clock with a frequency f ₀ Hz is divided by 2, and the clock width is 1 / f ₀ seconds and the period is 2 /.
Clocks of two clock phases of f ₀ seconds are generated, output clocks DP ₁ and DP ₂ and two types of sync word detection pulses UWh ₁ and UWh ₂ corresponding to these clock phases are input, and UWh = The correct sync word detection pulse can be obtained by the calculation UWh ₁ · DP ₂ + UWh ₂ · DP ₁ .

As described above, according to the present invention, since the serial-parallel converter and the digital correlator are completely separated from each other, the operating frequency of the digital correlator can be lowered according to the number of parallel processes. As a result, the operating frequency can be increased, and the correct high-speed sync word detection pulse without the uncertainty of the clock phase can be obtained.

"Embodiment" FIG. 1 shows an embodiment of the present invention.

16 is a serial signal input terminal, 17 is a serial-parallel conversion circuit, 18 is a clock input terminal, 19 is a counter, 20 is a divided clock, 2
1, 22 are stand-alone digital correlators, 23 is a decoder, 24 is a selector, and 25 is a sync word detection pulse output terminal.

FIG. 2 is a time chart for explaining the operation of the serial-parallel conversion circuit of FIG. 1, where A is an input clock, B is an input serial signal, C is a divided clock of the counter 19, and D and E are serial-parallel conversion circuits. It is a parallel signal of 17 outputs.

FIG. 3 is a time chart for explaining the operation of the decoder 23, where A is an input clock and F and G are output pulse signals of the decoder 23.

In order to operate the parallel processing type synchronous word detector shown in FIG. 1, a high-speed serial signal B is input from the input terminal 16, and the serial-parallel conversion circuit 17 and the counter 19 cause a low-speed operation having a half operating frequency. Convert to parallel signals D and E.

The time chart of the input / output signals at this time is as shown in FIG. In the case of serial-parallel conversion of an input signal, there are two cases in the phase relationship between the input clock and the divided clock in this example, and the output patterns of the serial-parallel converted signals differ corresponding to each case. By providing the slow sync word detectors, that is, the digital correlators 21 and 22 corresponding to these two signal patterns, the sync word detection pulse can be obtained from one of the two detectors. Depending on which of the digital correlators 21 and 22 the detection pulse is obtained from, the uncertainty of the clock can be removed and a high-speed sync word detection pulse can be obtained again. That is, the decoder 23 generates two kinds of pulse trains (DP ₁ , DP ₂ ) as shown in FIG. In the selector 24, output signals of the digital correlators 21 and 22 (U
By selecting one of the two types of pulse trains using Wh ₁ , UWh ₂ ) as a control input, it becomes possible to obtain the correct high-speed synchronization word detection pulse UWh. The relationship at this time is UWh =
Obtained by UWh ₁ · DP ₂ + UWh ₂ · DP ₁ .

 However, {•} indicates a logical product, and {+} indicates a logical sum.

FIG. 4 is a diagram for explaining in detail the configuration of the digital correlators 21 and 22 shown in FIG. 26 and 27 are input signal terminals for inputting the output signals P1 and P2 of the serial-parallel conversion circuit 17, 28 is a rearrangement circuit, 29 is a divided clock input terminal of the counter 19, and 30 and 31 are rearrangement circuit 28. An output signal, 32 is a digital correlation detector, 33 is an adder, 34 is a comparator, 35 is a threshold input terminal, and 36 is a correlation detection pulse output terminal.

FIG. 5 is a detailed diagram of the rearrangement circuit 28 in FIG. 4, and has rearrangement circuit configurations of A and B, respectively, corresponding to the digital correlators 21 and 22, where A is the equation (1) above. And the operation B is performed by the equation (2).

To operate this circuit, a reference pattern is set in advance in the register of the digital correlation detecting section 32, and parallel signals are input to the digital correlation detecting section 32 from the terminals 26 and 27 via the rearrangement circuit 28. Digital correlation detector 32
Then, the matching bit number of the reference pattern and the input pattern is calculated, and the adder 33 calculates the matching bit number of the entire digital correlation detecting unit. Output signal of adder 33 is comparator
It is input to 34 and compared with the threshold value input in advance from the threshold value input terminal 35. If the threshold value is exceeded, a sync word detection pulse is output from the output terminal 36.

As shown in FIG. 1, the serial-parallel conversion circuit 17 requiring high-speed operation and the synchronous word detector capable of low-speed operation, that is, the digital correlators 21 and 22 are completely separated. Therefore, if the number of parallel processings is essentially increased, the conventional upper limit of the operating speed does not exist.

"Effects of the Invention" As described above, in the synchronous word detection circuit of the present invention, the high-speed processing circuit of the serial-parallel conversion circuit 17 and the digital correlator 2
By completely separating the low-speed processing circuits of 1, 22 from each other, the operating speed of the digital correlators 21 and 22 can be slowed down, and if the number of parallel processings is increased, it does not depend on the operating frequency of the low-speed processing circuits. There is an advantage that a synchronous word of a high speed signal can be detected.

Further, the synchronous word detection circuit of the present invention has been described for the case where one system is used as an input signal such as a two-phase PSK modulation / demodulation system, but a plurality of sequences when a multiphase phase modulation system such as four-phase PSK is used. It is also applicable to the case where is an input signal.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a time chart explaining the operation of the serial-parallel conversion circuit 17 in FIG. 1, and FIG. 3 is an operation of the decoder 23 in FIG. 4 is a block diagram showing a detailed configuration example of the digital correlator 21 alone in FIG. 1, FIG. 5 is a detailed diagram of the rearrangement circuit 28 in FIG. 4, and FIG. Block diagram showing a configuration of a conventional parallel processing type digital correlation circuit, No. 7
6 is a time chart for explaining the operation of FIG. 6, and FIG. 8 is a block diagram showing details of the single digital correlator 7 in FIG.

Claims (2)

[Claims] 1. A serial-parallel conversion circuit for converting an input digital signal sequence into two digital signal sequences, and the output signals ₁ and ₂ of the serial-parallel conversion circuit as inputs to the equations (1) and (2). Perform 2 types of layout conversion 2
Relocation circuits, However, _i indicates that the Pi signal (i = 1, 2) is delayed by 1 bit. Based on two digital correlators for detecting two kinds of sync words using the output signals P ₁ and P ₂ of these rearrangement circuits as parallel input signals, and two kinds of low speed sync word detection pulses of these digital correlator outputs. A parallel processing type synchronous word detector having a synchronous word detecting pulse selection circuit for generating a high speed synchronous word detecting pulse having a correct clock phase. 2. The sync word detection pulse selection circuit has a frequency f _0.
A high-speed clock of Hz is divided into two, and a circuit for generating two types of clock phases having a clock width of 1 / f ₀ sec and a period of 2 / f ₀ sec is provided, and the circuit output signals DP ₁ and DP ₂ and the clock thereof are provided. The parallel synchronous word detecting pulse according to claim ₁ , wherein two kinds of synchronous word detecting pulses UWh ₁ and UWh ₂ corresponding to a phase are input, and a correct synchronous word detecting pulse is obtained by the calculation shown in the equation (3). Processed sync word detector. UWh = UWh ₁ · DP ₂ + UWh ₂ · DP ₁ (3) where {•} is a logical product and {+} is a logical sum.