JPH0884305A - Equipment and method for transducing video signal to image display segment of combination video signal - Google Patents

Abstract

PURPOSE: To simultaneously vie pixel data from multiple non-broadcasting video signals or from broadcasting and non-broadcasting video signals on a single display screen. CONSTITUTION: A video circuit 10 coverts selected video signals to display segments of synthetic video signals. An input circuit 12 has receiving terminals VB and VNB1 -VNBX and any one of these receiving terminals VNB1 -VNBX receives non-broadcasting signals as one of selected video signals. The input circuit 12 stores pixel data representing a field of selected video signals in field buffers 34a-34y and 36a-36y. A synthesizer circuit converts the field to display segments and synthesizes the display segment to the display field.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates generally to a video signal converting apparatus and method, and more particularly to an apparatus and method for converting a video signal into a video display segment of a combined video signal.

[0002]

2. Description of the Related Art Many video display devices are capable of converting a plurality of selected broadcast video signals into a combination video signal of a plurality of display segments, and the combination video signal is a single display signal. Multiple display segments can be displayed simultaneously on the screen. The multiple video signals are
Typically carrying video information, the video signal is arranged in a plurality of horizontal lines, which are grouped into a plurality of fields. In interlaced transmission, each field is an odd field or an even field, and is included in one frame every other line, and one frame includes one odd field interlaced by one even field. A display device, such as a television receiver, supplies horizontal lines to a display screen, such as a cathode ray tube (CRT), one field or frame at a time, which converts the signal into visible pixels. Each broadcast video signal typically occupies a different channel frequency. Display devices often have one broadcast input terminal that simultaneously receives multiple broadcast signals from a source such as a cable hookup, satellite dish, or antenna.

Recently, digital display systems have been improved to provide "picture-in-picture" or multiple picture displays. In the combined video signal, the different sections of the field each contain one of the video display segments, and each video display segment contains pixel data from one of the selected broadcast signals. For example, the section of a multi-field displayed in the center of the display screen, i.e., the central section of the field, may include the first of the two segments displayed in the center of the screen. Similarly, the peripheral section of the field includes a second segment for display in the screen portion surrounding the center. The first segment is the sports carried by the first broadcast video signal.
Pixel data for the event may be included and the second segment may include pixel data for the movie carried by the second broadcast video signal. Thus, while watching a movie on the periphery of the screen, you can watch a sporting event in the center of the screen.

[0004]

Further, such display devices typically provide non-broadcast video generated by local devices such as video game consoles or video cassette players / recorders (VCRs). It can also receive signals. However, most display devices cannot simultaneously receive multiple non-broadcast video signals, or both broadcast video signals and non-broadcast video signals.

A display system capable of receiving a non-broadcast video signal can perform this reception by two methods. When the display device receives a non-broadcast video signal at its broadcast input terminal, an adapter switch is often provided for disconnecting the broadcast signal from the broadcast input terminal and connecting the non-broadcast signal thereto. Therefore, the display device can only receive and display one non-broadcast signal at a time. When the display device receives a non-broadcast signal on another input terminal, a circuit for disconnecting the broadcast signal from the signal processing circuit and connecting the non-broadcast signal to another input terminal is provided in the display device. Therefore, it is possible to display only one of the broadcast signal and the non-broadcast signal, not both.

[0006]

The first feature of the present invention is to:
A video circuit for converting a selected video signal into a plurality of display segments of a combined video signal. The input circuit has two terminals, at least one of which is for receiving a non-broadcast signal as one of the selected video signals. The input circuit stores pixel data representing a plurality of fields of the selected video signal. The combination circuit converts the fields into display segments.

The effect obtained by the present invention is to convert the selected broadcast video signal and non-broadcast video signal into a plurality of display segments of the combined video signal. Another feature of the invention is to convert the selected non-broadcast video signal into multiple display segments of the combined video signal. Therefore, the pixel data of the multiplexed non-broadcast video signal or the pixel data of the combined signal of the broadcast video signal and the non-broadcast video signal can be simultaneously viewed on one display screen.

[0008]

The preferred embodiment of the present invention and its advantages are best understood by referring to FIGS. 1-3 of the drawings, in which like numerals refer to like and corresponding parts of the various drawings.

1A-1D show example segment modes for arranging display segments on a display screen 22 within a display field of a combined video signal. Each segment contains pixel data from one of the selected video signals and is included in a different section of the display field.

FIG. 1A shows a display screen 22 displaying segments A and B. These include 2 selected
It includes pixel data from one video signal VA and VB. As shown, segments A and B are contained within the central and peripheral sections of the display field. Although segment A is shown in the center, it can be anywhere within the field of segment B. Furthermore, segment A
The display field portion occupied by may differ from that shown in FIG. 1A.

FIG. 1B shows a display screen 22 displaying segments A to D, which have four selected screens.
Pixel data from one video signal VA to VD is included. As shown, segment A is contained in the upper left section of the display field, segment B is contained in the upper right section, segment C is contained in the lower left section, and segment D is contained in the lower right section.
This format is undistorted and non-overlapping2
Alternatively, the three segments can be displayed and the unused display segment can be left blank.

FIG. 1C shows a display screen 22 displaying segments A and B. As shown, segment A
Is shown in the section in the upper half of the display field and segment B is shown in the lower half.

FIG. 1D shows a display screen 22 displaying segments A and B. Segment A is included in the left half section of the display field and segment B is included in the right half section.

The segments of FIGS. 1A and 1B retain the aspect ratio (the ratio of width to height of the displayed field or field section) for each section of the display field. Therefore, FIGS. 1A and 1B
Segment of typically contains pixel data taken from the entire field of each selected signal. Conversely, FIG. 1C
And the segments in FIG. 1D do not retain their respective aspect ratios. Therefore, they typically contain pixel data taken from only one section of the field of each selected signal. Instead, they can display distorted images. Since many games can be played with distorted images, or when displaying only a section of the field showing game actions, the segment mode of FIGS. 1C and 1D is often a video game mode. Suitable for display.

2A and 2B are schematic diagrams of the video circuit 10, which converts the pixel data of each selected broadcast signal into different display segments of the combined video signal V _c . As mentioned above, a video display device such as a television receiver (not shown) which receives the combined video signal simultaneously displays these display segments on a display screen 22 such as a CRT according to the selected segment mode. To do.

In the first embodiment, the video circuit 10 is
Multiplexed non-broadcast video signals are received simultaneously as if all selected video signals were non-broadcast video signals. For example, two players may play two video game consoles on the video circuit 10 so that they can play separate video games on different parts of the same display screen.
You can connect if you want to connect to.

In the second embodiment, the video circuit 10 is
At least one broadcast video signal and at least one non-broadcast video signal are simultaneously received so that the selected video signal may include a combination of non-broadcast video signals and broadcast video signals. For example, if a VCR is playing a video tape and you want to watch a broadcast sporting event on different parts of the same screen, you can watch it. However, in any of the embodiments, the video circuit 10 can supply a non-broadcast video signal as one of the selected video signals.

The video circuit 10 includes an input circuit 12 for storing a plurality of fields of a selected video signal and a combination circuit for converting the fields into a plurality of display segments and combining these segments into a plurality of display fields. 14 and an output circuit 16 for converting a plurality of display fields into a combined video signal. Alternatively, the video circuit 10 may omit the output circuit 16 and provide the plurality of display fields directly to a device such as a display device that converts the plurality of display fields into a combined video signal.

In addition, the video circuit 10 may include a mode processor 18 which controls the input circuit 12, the combination circuit 14 and the output circuit 16. Input device 2
0 selects both the video signal to be combined and the segment mode. An input device 20, which may be a display control panel or part of a remote control unit, makes a selection to the mode processor 18. The mode processor 18 identifies the selected video signal to the input circuit 12 and provides the segment mode to the selected combination circuit 14.

In particular, the input circuit 12 enables selection of a predetermined number Y of video signals for combination. Typically,
Y is in the range of 3 to 4, but may be larger. The input circuit 12 receives the received multiplex (multipl).
e) It includes a tuner 24 for outputting a video signal selected from the video signals, and the selected video signal is identified by the mode processor 18. In the first embodiment of the video circuit 10 described above, the tuner 24 outputs the multiplexed non-broadcast video signal V
_NBL ~V _NBx receives multiple input terminals _{V NBl～V
With NBx} . In the above-described second embodiment, the tuner 24 includes one or more non-broadcast video signals _{VNB1 to VNB1.}
Receiving a _NBx 1 or more input terminals _{V NBL} ~
It has V _NBx and has an input terminal V _B for receiving one or more broadcast video signals. In any of the embodiments, the tuner 24 lowers the selected video signals to the baseband frequency by mixing and outputs each baseband signal to Y.
It is supplied to one of the conversion circuits 26a to 26Y.

Each Y conversion circuit 26a-26Y digitizes the respective baseband signals, stores the digitized baseband signals of a plurality of fields, and processes them by the combination circuit 14. Y conversion circuits 26a to 26
Since Y has the same structure and operation, only the Y conversion circuit 26a will be described in detail. The Y conversion circuit 26a includes a corresponding synchronous stripper 28a for extracting a synchronous pulse and a voice signal from the baseband signal. The analog-to-digital converter (ADC) 30a converts the extracted signal from analog format to digital format. Frame buffer 32
a is pixel data representing each odd field of the digitized baseband signal, and the odd field section 3
4a and the pixel data representing each even field is stored in the even field section 36a. In addition, odd field section 34a includes at least two odd field buffers, and even field section 36a includes at least two even field buffers, as described below.

The buffer controller 38a controls the sequence of writing and reading to the display field buffer and the even field buffer. For example, for a sequence starting with the first odd field, the buffer controller 38a loads the first odd field into the first odd field buffer and the first even field into the first even field. Buffer, load the second odd field into the second odd field buffer, load the second even field into the second even field buffer, and so on. Load until all field buffers in buffer 32a have been loaded. The buffer controller 38a then repeats the cycle by overwriting the first odd field buffer with the next odd field and the first even field buffer with the next even field.

In the odd field section 34a and even field section 36a
a) odd field buffers and multiple even field buffers, respectively, to allow fields of the same type to be written and read simultaneously without buffer conflict or other errors. For example, while buffer controller 38a is loading an even field, combinational circuit 14 requests that the even field be read. If the buffers read and write at the same time, some pixel data may be lost, and if there is only one even field buffer, there is a risk of conflict. When the buffer controller 38a is waiting for the combinational circuit 14 to read one even field buffer, it loses pixel data from the current even field; When the combinatorial circuit 14 is waiting to load, then it loses the stored pixel data of the field. Combining circuit 1 to obtain a previously stored even field from another even field buffer
4 while controlling the buffer controller 38a
Allows multiple even field buffers to load one even field buffer with the current field of the baseband signal.

The combination circuit 14 comprises a processing circuit 40 and a filter circuit 42. The filter circuit 42 converts the pixel data from the field of the selected video signal into a display segment and combines the display segment with the display field according to the selected segment mode. The filter circuit 42 includes filters 47a to 47Y that reduce the fields stored in the corresponding frame buffers 32a to 32Y. Filters 47a-4
7Y performs this reduction by obtaining the desired pixel data from the field, i.e. by filtering.
Then, the filters 47a to 47Y supply this desired pixel data to the multiplexer (MUX) 49. By selective switching at the appropriate times, multiplexer 49 generates multiple display segments from the desired pixel data and combines these display segments to form multiple display fields. As shown in FIG. 1A, in some cases the desired pixel data filtered from field (B) may be equal to the total pixel data filtered from field (B). Therefore, the switching operation of the multiplexer 49 can only generate the display segment (B).

The processing circuit 40 includes a display processor 44, which displays the selected segment.
According to the mode, the filters 47a to 47Y are programmed to recognize desired pixel data, and a program for switching the multiplexer 49 is executed.
Further, according to the selected segment mode, the display pulse generator 46 generates display sync pulses which are combined by the output circuit 16 with the plurality of display fields. Further, these display sync pulses provide timing signals to the display processor 44. Display pulse generator 46 typically acquires these display sync pulses from one of the selected video signals. However, the display pulse generator 46 can also generate these display sync pulses independently of the selected video signal pulses.

The output circuit 16 converts the display field received from the multiplexer 49 into a combined video signal suitable for display by the display device. The output circuit 16 includes a digital-to-analog converter (DAC) 48 that converts the display field from digital format to analog format. The sync pulse inserter 50 combines the sync pulses provided by the display pulse generator 46 with the digital display field. The audio multiplexer 52, which is controlled by the mode processor 18, connects the desired one of the selected video signals to the mixer 54. Voice multiplexer 5
2 further connects some or all of the remaining audio signals to an output terminal (not shown). These output terminals listen to the audio from one of the video signals selected by one person via the display audio system, while the audio from another of the video signals selected by another person. To be able to hear through the headphones. The mixer 54 combines the desired audio signal with the synchronized display field and mixes this combined signal with the broadcast frequency, typically channel 3 or 4, to produce a combined video signal. Alternatively, the output circuit 16 may connect the synchronized display field combined with the desired audio signal directly to the display device.

Memory 56 stores programs executed by mode processor 18 and display processor 44. The video circuit 10 further includes Y conversion circuits 26a-26.
Multiplexer 58 for bypassing Y, combination circuit 1
4 and an output circuit 16 for viewing only one video signal at a time. The tuner 24 selects one such signal and the mode processor 18 commands the multiplexer 58 to provide this signal to the display device instead of the combined video signal.

In operation, tuner 24 supplies the selected video signal to sync strippers 28a-28Y. The extracted signals are digitized by ADCs 30a-30Y, and their odd and even fields are stored in frame buffers 32a-32Y as previously described. The extracted sync pulse is used by the sync stripper 2
8a-28Y to ADCs 30a-30Y, respectively, and buffer controllers 38a-38 to properly synchronize the digitization and storage of the fields.
Load Y. The extracted synchronizing pulse is further supplied to the display pulse generator 46, and the display pulse generator 4
6 provides sync pulses from one of the selected signals to display processor 44 and sync pulse inserter 50, as described above.

The display processor 44 is responsive to the segment mode and sync pulses from the display pulse generator 46 and is associated with the buffer controller 38a ... 38Y is commanded to connect to the filters 47a to 47Y at a given time. Display processor 44
Further programs the filters 47a-47Y with an algorithm that operates to filter the desired pixel data from the field of the selected video signal. By instructing multiplexer 49 to selectively supply the filtered pixel data from filters 47a-47Y, display processor 44 generates display segments from the simultaneously stored fields and displays them in combination. Form a field.

For example, referring to the display mode shown in FIG. 1A, the selected video signals VA and VB are filtered by the filter 47.
Assuming they are processed by a and 47b respectively,
The filter 47b supplies the pixel data representing the pixel of each field from the frame buffer 32b to the multiplexer 49. The multiplexer 49 has an upper section 6
0, the bottom section 64, and the filter 4 to the DAC 48 when forming multiple portions of the central section 62 to the left and right of the central section of the display field.
Providing the output of 7b produces a display field section containing segment B.

Since segment A is contained within the central section of the display field, filter 47a is
The field stored in the buffer 32b is reduced. For example, the displayed segment A has dimensions equal to approximately one-half the horizontal and vertical dimensions of display screen 22. Therefore, to approximate the pixel data representing the entire field of signal VA, filter 47a includes approximately one horizontal line of each field provided by frame buffer 32a.
/ 2 is effectively removed and about 1/2 from each horizontal line
The pixels of are removed. As the scan of each line in central section 62 reaches edge 66, display processor 44 switches multiplexer 49 to output the output of filter 47a.
Supply to AC48. When the scan reaches edge 08, display processor 44 switches multiplexer 49 to provide the output of filter 47b.

The filter 47a has a line every other line,
And instead of effectively filtering every other pixel in the remaining lines from the fields of the video signal VA, pixel data representative of each field in its entirety can be provided. As a result of the operation of the multiplexer 49, the alternative segment A contains the pixel data representing the central section of the field by the video signal VA. A similar combination of filter algorithm and switching of multiplexer 49 can generate the segment mode of FIG. 1B.

To generate the display of FIG. 1C, the filter 47a is scanning the upper half of the display screen 22 from the frame buffer 32a to the upper half of each field, or
Alternatively, pixel data representing each pixel from the lower half section is supplied to the multiplexer 49. Similarly, filter 4
7b is the frame buffer 3 during scanning of the lower half 72.
Pixel data representing each pixel in the upper half section or the lower half section of each pixel is supplied to the multiplexer 49 from 2b. By selectively switching the multiplexer 49, the display processor 44 generates the desired display segment with the supplied pixel data and combines the display segment with the display field. In particular, the multiplexer 49
DAC outputs the output of the filter 47a during scanning of the upper half 70 and the output of the filter 47b during scanning of the lower half 72.
Supply to 48.

To produce the display of FIG. 1D, the filter 47a filters each pixel from the left or right half section of each field from the frame buffer 32a during the scan of the left half 73 of the display screen 22. The pixel data to be represented is supplied to the multiplexer 49. Similarly, filter 47b multiplexes pixel data representing each pixel in the left or right half section of each field from frame buffer 32b during the scan of right half 75.
Supply to. At the midpoint of each scan line, display processor 44 causes multiplexer 49 to output the output of filter 47b.
Since it is connected to the AC 48, the output of the filter 47b is switched to be connected to the DAC 48.

2A and 2B, the DAC 48 converts the display field output by the multiplexer 49 from digital format to analog format from digital format to analog format. The sync pulse inserter 50 combines the sync pulse provided by the display pulse generator 46 with the analog display field. Mode processor 18 typically selects, via audio multiplexer 52, an audio signal with the same selected video signal whose sync pulse is provided to sync pulse inserter 50. However, the mode processor 18 can select the audio signal from any of the selected video signals.

The mixer 54 combines the audio signal and the synchronized display field to generate a combined video signal.
The mixer 54 typically transitions the combined video signal to a broadcast channel such as channel 3 or 4. Alternatively, mixer 54 may leave the combined video signal at its baseband frequency.

In the one-signal display mode, the tuner 24 supplies the selected video signal to the multiplexer 58. Multiplexer 58 is responsive to mode processor 18 to provide this single broadcast signal instead of the combined video signal for the display.

FIG. 3 is a schematic diagram of a video adapter 74 using the video circuit 10 of FIGS. 2A and 2B. In the first and second embodiments, the housing 79 houses the first and second embodiments of the video circuit 10 described above, respectively, and the power supply 81 supplies power to the video adapter 74. Therefore, the video adapter 74 can supply the combined video signal to a display device such as a television receiver (not shown) that cannot generate the combined video signal.

A third embodiment of video adapter 74 is
It is suitable for use in a display device that combines a selected broadcast video signal with a combined video signal. Therefore, the video adapter 74 adds the function of generating a selected non-broadcast video signal or a combined video signal from the selected broadcast video signal and non-broadcast video signal to such a display device.

A third embodiment of video adapter 74 is
In addition to the video circuit 10, it includes a channel shifter 76, a channel combiner 78, and a multiplexer 80. In operation, the channel shifter 76 can provide one or more non-broadcast video signals on the desired broadcast channel. The channel combiner 78 combines the shifted non-broadcast signal with the received broadcast video signal and supplies the combined channel signal to the multiplexer 80.
The multiplexer 80 is responsive to the mode processor 18 to provide a combined channel signal or combined video signal to the display device. Therefore, by transitioning the frequency of the non-broadcast video signal to the broadcast channel, the video adapter 74 "falsifies" the television receiver to recognize the non-broadcast video signal as a broadcast video signal.

For example, assuming a particular geographical area, the broadcast channel 28 is unoccupied. Input device 2
0 through the mode processor 18
, And the mode processor 18 supplies this information to the channel shifter 76. Then, the channel shifter 76 frequency-shifts the selected non-broadcast video signal to the broadcast channel 28. Channel combiner 78
Combines this broadcast channel 28 with the rest of the broadcast channels to form a combined channel signal. The user programs the television receiver to select the broadcast channel 28 and combines it with other video signals. Thus, the video adapter 74 allows the television receiver to combine non-broadcast video signals with broadcast video signals or multiplex non-broadcast video signals for simultaneous display.

Alternatively, the channel combiner 78 is
The broadcast video signal can be separated from the multiplexer 80 to provide one or more non-broadcast signals at the channel frequency occupied by the channel shifter 76.

In another embodiment of the invention, the first display segment transparently overlays the second display segment. The display processor 44 includes the multiplexer 4
By correctly switching 9 it is possible to periodically replace one display segment or part thereof with another display segment or part thereof in the section of the display field. The visible effect is that two or more display segments appear to be transparently superimposed. For example, the first display field can include the entire display of segment B of FIG. 1A, and the second display field can include segments A and B, as shown in FIGS. 1A and 1B. Instead, the display of these two fields transparently overlaps the display center of segment B, producing the visible effect of segment A. In another embodiment, segment A transparently overlaps segment B in its entirety.

In the above example, every other display field includes the segment A, but the ratio of the relative number display field including the segment A to the relative number display field including the segments A and B is changed to change the segment B to the segment B. The perceived transparency of segment A with respect to may be varied.

For interlaced video displays, each odd field and even field may be selected to include different display segments as described above, or the fields, or frames, of each odd / even field pair. May be limited to include the same display segment.

Although the present invention and its effects have been described in detail,
It is to be understood that various changes, substitutions and alternatives can be made without departing from the spirit and scope of the invention as defined by the claims. For example, the signal VB
_{And VNBl- VNBx} (or any _combination thereof) are in digital form, the ADCs 30a-30Y (or corresponding combinations thereof) can be omitted. Similarly,
The DAC 48 may be omitted if the display device is capable of receiving the VC in digital form. Furthermore,
If the signals VB and _{VNB1- VNBx} (or any _combination thereof) are non-interlaced, then only one set of odd field sections 34a-34Y or even field sections 36a-36Y may be required.

The following items are further disclosed with respect to the above description.

(1) A video circuit for converting a selected video signal into a display segment of a composite video signal, which is an input circuit having two terminals, wherein at least one of the terminals serves as one of the selected video signals. A video circuit including the input circuit for receiving pixel data representing a field of the selected video signal for receiving a non-broadcast video signal, and a synthesizing circuit for converting the field into the display segment.

(2) In the video circuit according to the first aspect, the input circuit is a tuner for converting the selected video signal into a baseband signal, and a plurality of conversion circuits, each of the conversion circuits being the baseband signal. A stripper circuit for removing a sync signal from one of said plurality, a converter for digitizing the stripped signal resulting from said sync signal removal, and a frame buffer for storing pixel data representing a field of said digitized signal. Video circuit, including the conversion circuit of.

(3) In the video circuit according to the first aspect, the input circuit includes a plurality of frame buffers, and each of the frame buffers has one of the selected video signals.
A number of odd field buffers for storing pixel data representing one odd field, and one of the selected video signals
A video circuit including a number of even field buffers for storing pixel data representing one even field.

(4) In the video circuit according to the item (1), the synthesizing circuit filters out desired pixel data from the pixel data, converts the desired pixel data into the segments, and converts the segments into the synthesized video. A video circuit comprising a filter circuit for synthesizing a signal into a display field, a controller for controlling the filter circuit and responsive to a sync pulse from the selected video signal.

(5) The video circuit according to the first aspect, wherein a converter for converting pixel data representing the display segment from a digital format to an analog format, and analog pixel data and a sync pulse in response to the synthesizing circuit. A video circuit further comprising a sync inserter for synthesizing the above and generating the synthesized video signal.

(6) The video circuit according to item 1, further comprising a mode processor for discriminating between the selected video signal to the input circuit and the display segment to the synthesizing circuit.

(7) An adapter which supplies an output signal and which converts pixel data from a selected video signal among a number of video signals into a display field of a composite video signal according to the segment mode. The adapter in which the segment mode is selected by using an input device has a multiplex non-broadcast terminal for receiving a multiplex non-broadcast video signal as a first number signal of the plurality of video signals, and the selection An input circuit for storing pixel data representing a field of a video signal, a synthesizing circuit for converting the field into a display segment and synthesizing the segment into the display field, an output circuit for generating the synthesized video signal from the display field, And executing a mode program, the selected video signal to the input circuit and the An adapter including a mode processor for identifying the segmentation mode to a compositing circuit in response to the input device and selectively coupling the composite video signal as the output signal.

(8) In the adapter described in item 7,
A tuner for converting the selected video signal into a baseband signal; a plurality of conversion circuits, each of the conversion circuits removing a synchronization signal from one of the baseband signals; and the synchronization signal. A converter that digitizes the stripped signal resulting from the removal of
A frame buffer storing pixel data from a digital signal representing a field of the one baseband signal, the adapter including the plurality of conversion circuits including a controller controlling the frame buffer.

(9) In the adapter described in item 7,
The input circuit includes a plurality of frame buffers, each of the frame buffers storing pixel data representing one odd field of the selected video signal, and a multiple odd field buffer, and the one even field of the selected video signal. An adapter including multiple even field buffers for storing pixel data representing the.

(10) The adapter according to claim 7, wherein the input circuit includes a broadcast terminal for receiving a broadcast video signal as a second number signal of the multiplexed signals.

(11) In the adapter described in the seventh item, the output circuit is responsive to the converter for converting the pixel data representing the display field from a digital format to an analog format and the synthesizing circuit, and is converted to the analog format. A sync inserter for synthesizing analog pixel data with a sync pulse, an audio multiplexer responsive to the synthesizing circuit for selecting an audio signal from one of the selected video signals, and the audio signal for generating the composite video signal And a mixer for synthesizing the synchronized analog pixel data.

(12) The adapter according to the seventh item, wherein the phase conversion switch responds to the mode processor to convert the phase of the selected non-broadcast video signal into a broadcast channel, and generates the composite channel signal in response to the mode processor. An adapter further comprising a channel synthesizer for synthesizing one or more broadcast video signals and a phase-converted non-broadcast signal, and a multiplexer responsive to the mode processor for combining the synthesized channel signals as the output signals.

(13) In the adapter described in the twelfth aspect, the synthesizing circuit generates a display synchronizing pulse in response to the mode processor and the synchronizing pulse of the selected video signal. A plurality of filter circuits for filtering out pixel data, a multiplexer for converting the desired pixel data into the display segment and synthesizing the segment into the display field;
And a display processor for executing a display program and selectively coupling the pixel data to the filter circuit and controlling the filter circuit and the multiplexer in response to the mode processor and the synchronization circuit.
adapter.

(14) A method of converting a selected video signal into a display segment of a composite video signal, the method comprising the steps of providing two terminals, wherein at least one of the terminals is non-selected as one of the selected video signals. A method comprising: receiving a broadcast video signal, providing the terminal, storing pixel data representing a field of the selected video signal, and converting the field into the display segment.

(15) In the method described in item 14,
The storing step includes converting the selected video signal to a baseband signal, removing a sync signal from the baseband signal, digitizing a stripped signal resulting from the removal of the sync signal, and A method comprising storing the pixel data from a digitized signal.

(16) In the method described in item 14,
Storing the pixel data representing each odd field of the selected video signal in multiple odd field buffers, and storing the pixel data representing each even field of the selected video signal in multiple even field buffers Storing the data,
Method.

(17) The method according to item 14,
Converting the pixel data representing the display segment from a digital format to an analog format, synthesizing analog pixel data resulting from the converting to the analog format and a sync pulse, 1 of the selected video signals
Selecting an audio signal from one of the two, and synthesizing a synchronous analog signal resulting from the synthesizing the sync pulse to generate the synthetic video signal with the acoustic signal.

(18) In the method described in item 14,
The method wherein converting the field to the display segment comprises filtering desired pixel data from the pixel data.

(19) The method according to item 14,
The method further comprising combining the display segment into a display field of the composite video signal.

(20) A video circuit for generating a display field of a composite video signal having an overlapping display segment, the input circuit receiving a field from a selected video signal, and converting the field into the display segment, Video comprising a synthesis circuit for synthesizing a segment into the display field and periodically using in the section of the display field the first segment or a portion of the first segment instead of the second segment or a portion of the second segment. circuit.

(21) In the video circuit according to the twentieth item, the synthesizing circuit substitutes the first segment or a portion of the first segment for the second segment or the second segment in alternate fields of the display field. Video circuit used.

(22) The video circuit according to item 20, wherein the input circuit stores pixel data representing the field.

(23) A method of generating a display field of a composite video signal having an overlapping display segment, the method comprising: receiving a field from a selected video signal; converting the field into the display segment; A method comprising merging into the display field, and cyclically using a first segment or a portion of the first segment in place of a second segment or a portion of the second segment in a section of the display field.

(24) In the method described in the paragraph 23,
The method wherein the synthesizing step comprises using a first segment or a portion of the first segment in place of the second segment or the second segment in alternating fields of the display field.

(25) A method according to item 23, wherein
The method further comprising storing pixel data representing the field.

(26) The video circuit converts the selected video signal into the display segment of the composite video signal. The input circuit has two or more receiving terminals, and at least one of the receiving terminals receives a non-broadcast signal as one of the selected video signals. The input circuit stores pixel data representing a field of the selected video signal. A compositing circuit converts the field into the display segment and combines the display segment into a display field.

CROSS REFERENCE TO RELATED APPLICATION The present invention is directed to an apparatus and method for converting a combined video signal of display segments into a display field of multiple video signals (D
device and Method ForConve
rending Display Segments of
A Combined Video Signals
Into Display Fields of M
"The Multiple Video Signals" in Houston (Theodore W. House)
on) in the United States Patent Application No.

[Brief description of drawings]

FIG. 1 is a diagram showing a mode in which display segments are arranged in a field of a combined video signal.

FIG. 2 is a schematic diagram of a circuit for converting a selected video signal into a display segment of a combined video signal.

FIG. 3 is a schematic diagram of an adapter associated with the circuits of FIGS. 2A and 2B.

[Explanation of symbols]

 10 video circuit 14 combination circuit 16 output circuit 18 mode processor 28a-28Y synchronous stripper 32a-32Y frame buffer 34a-34Y odd field section 36a-36Y even field section 38a-38Y buffer controller 40 processing circuit 42 filter Circuit 44 Display processor 46 Display synchronization generator 47a to 47Y filter 49, 58, 80 Multiplexer

Claims (2)

[Claims] 1. A video circuit for converting a selected video signal into a display segment of a composite video signal, the input circuit having two terminals, wherein at least one of the terminals is non-selected as one of the selected video signals. A video circuit including the input circuit for receiving a broadcast video signal, storing pixel data representing a field of the selected video signal, and a compositing circuit for converting the field into the display segment. 2. A method of converting a selected video signal into display segments of a composite video signal, the method comprising the steps of providing two terminals, at least one of said terminals being non-broadcast as one of said selected video signals. A method comprising: receiving a video signal, providing the terminal, storing pixel data representing a field of the selected video signal, and converting the field into the display segment.