JPH088344A - Redundant circuit - Google Patents

Abstract

PURPOSE:To repair more than one circuit elements by connecting one signal I/O part selectively with X+1 contiguous circuit elements through X+ 1 contacts each of N switch elements disposed between M circuit elements of identical circuitry larger, in number, by X than N signal I/O parts. CONSTITUTION:N switch elements SW1-SW2, each having X+1 contacts F1-FX, FX+1, are disposed between M circuit elements C1-CM of identical circuitry larger, in number, by X than N signal I/O parts D1-DN of identical circuitry. X+1 contiguous circuit elements C.-C. is connected selectively with one signal I/O part D1 through X+1 contacts of each switch element SW1-SW2. When a single defect is found in a circuit element, the circuit element can be repaired by shifting one element to the right for each defect. In the case of continuous defect the circuit element can be repaired by shifting two elements to the right for each defect.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a redundant circuit for replacing a defective circuit element with a redundant portion having the same structure as the circuit element to repair the defect. Generally, in a semiconductor integrated circuit including a large number of circuit elements of the same configuration such as a semiconductor memory, some redundant circuit elements may be formed in advance to replace a defective circuit element with a redundant portion. Done.

[0002]

[Prior art]

"First Prior Art" FIG. 17 shows a conventional example of a redundant circuit.
It is an example of application to a semiconductor memory. In this figure, 1 is a row address buffer for fetching a row address signal, 2 is a row decoder for decoding the row address signal to select a row of the memory cell array 3, and 4 is a column address for fetching a column address signal. A buffer 5 is a column decoder that decodes a column address signal to select a column of the memory cell array 3, 6 is a row driver, and 7 is a column switch. Here, 8 is a redundant row decoder, 9 is a redundant column decoder, 10 is a redundant row, and 11 is a redundant column. These redundant row decoder 8, redundant column decoder 9, redundant row 10 and redundant column 11 are integrated. The redundant circuit 12 is configured.

In such a configuration, the output of the column address buffer 4 is input to the column decoder 5 and the redundant column decoder 9. When the input address matches the defective column address programmed in the redundant column decoder 9, the redundant column 11 is selected, and at the same time, the column decoder 5 is deactivated by a predetermined signal (NED) to replace the defective column. Is done. Similarly, when repairing a row, the address of the defective row is programmed in the redundant row decoder 8.

By the way, in the conventional technique, the fuses in the redundant row decoder 8 and the redundant column decoder 9 are cut to program the defective address. However, there is a disadvantage that the number of cut fuses increases as the capacity increases. Yes, and redundant row decoder 8 as capacity increases
There is a disadvantage that the structure of the redundant column decoder 9 becomes complicated and the speed difference between the row decoder 2 and the column decoder 5 becomes large. "Second Conventional Technique" As a conventional technique for solving such an inconvenience, for example, "Examination of Redundancy Circuit for Large Capacity RAM" (refer to 1989 IEICE Autumn National Congress Draft C-144) is known. .

This technique is intended to relieve a defect by shifting a column (or row; hereinafter referred to as a column) represented by each address by one to the side. In FIG. 18, 13 is a column decoder, 14 is a column switch, and n column decoder outputs D ₁ to
Against D _n, and n pieces of switching element 15 ₁ to 15 _n,
There are provided _{n + 1} columns C _{1 to} C _{n + 1} .

If there is no defect, D₁~ D_nAt C₁~
C_nTo select each switch element 15₁~ 15_nof
The contact is tilted to the left, for example, column C₃Has a defect
If it occurs, D₃~ D_nAt C_Four~ C_{n + 1}Select
Switch element 15₃~ 15_nOn the other side
Switch. FIG. 19 is a specific configuration diagram showing a fuse.
16₁~ 16_FourAnd inverter gate 17₁~ 17_Fouras well as
Transmission gate 18_1a, 18_1b~ 18_4a1
8 _4bIt is an example in which a switch element is configured with.

Fuse 16 connected in series₁~ 16
_FourHas its left end at the ground potential V_SSIn addition, the right end is
+ Power source V through anti-19_CCIs connected to the fuse
Inverter gate 17 when not disconnected₁~ 17_FourInput
Is the ground potential V_SSIs given. Therefore,
In this configuration, all fuses 16₁~ 16_FourIs uncut
As long as there are all inverter gates 17₁~ 17_Fourof
Since the output becomes high level, the a side transmission
Gate 18_1a, 18_2a, 18_3a, 18_4aTurn on
D₁~ D_nAt C₁~ C_nCan be selected. On the other hand, for example,
Column C₃If the fuse is defective, the fuse 16₃
Disconnect. In this way, the inverter gate 17 ₃1
7_FourOutput goes low, which results in a
Session gate 18_3bAnd 18_4bIs turned on, D₃
~ D_nAt C_Four~ C_{n + 1}Can be selected. That is, the defect
Ram C₃Redundant column C_{n + 1}Can be rescued with.

[0008]

However, the second conventional circuit is effective in that the number of fuses to be cut can be reduced and the speed difference between the row decoder and the column decoder can be reduced. However, since each switch element has only two contacts, the number of circuit elements repaired is "1" (one column or one row in FIGS. 18 and 19).
There was room for improvement from a practical point of view.

[0009]

It is therefore an object of the present invention to provide a practically sufficient redundant circuit by repairing at least two or more circuit elements.

[0010]

FIG. 1 shows the principle of the present invention. In this figure, D ₁ to D _N are signal input-output unit (which may be either of the input and output without being limited input or output signal), C ₁ ~C _M circuit elements, SW ₁ to SW _N Is a switch element, and CNT _{1 to} CNT _N are control means.

Signal input / output units D _{1 to} D _N and circuit elements C ₁ to
C _M is respectively have the same configuration, the number of circuit elements C ₁ -C _M is X number (X is a number of 2 or more) than the number of signal input and output unit D ₁ to D _N only Many. Example of FIG. 1 is for the "2" Number of minimum required number of X, therefore, in this example, the circuit element C ₁ -C _M includes two redundant portion of the C _M-1 and C _M Will be included.

Each of the switch elements SW _{1 to} SW _N has at least X + 1 contacts (three contacts F _{1 to} F _{3 because} X = 2 in the example of FIG. 1), and by switching the contacts. , Adjacent X + 1 circuit elements (C _i , ...,
C _{i + X-1} , C _{i + X} ; i is 1, 2, ... N) and one signal input / output unit (D _i ) is selectively connected.

Each of the control means CNT _{1 to} CNT _N determines the switching number of the contact of the switch element (SW _i ) which it is in charge of. The determination is the first circuit element arranged in a predetermined order. It is desirable to perform it based on the total number of defects generated from (C ₁ ) to the i-th circuit element (C _i ).

[0014]

[Action]

 (1) No defect FIG. 2 is a state diagram when there is no defect in any circuit element.
It In this case, all switch elements SW_i-1~ SW
_{i + 3}Contact point F₁Is closed, as shown by the thick line in the figure,
The circuit elements with the same subscript and the signal input / output section are connected.
Have been. That is, C_i-1And D_i-1While C_iAnd D_i
While C_{i + 1}And D_{i + 1}While C_{i + 2}And D_{i + 2}While C
_{i + 3}And D_{i + 3}Between and C_{i + 4}And D_{i + 4}Between each
Has been continued. (2) Single defect FIG. 3 shows one circuit element (for example, C_{i + 1}) Has a defect
FIG. In this case, switch element SW
_i-1And SW_iContact point F₁Closed but defects occur
Circuit element C_{i + 1}And the switch element S with the same subscript
W_{i + 1}And all switch elements SW on the right side_{i + 2},
SW_{i + 3}, Contact point F₂Is closed. Therefore,
In this case, as indicated by the thick line in the figure,
Element C_{i + 1}To the right side circuit element C_{i + 2}, C_{i + 3},
C_{i + 4}, ... are contacts F respectively₂Signal input / output via
Part D_{i + 1}, D_{i + 2}, D_{i + 3}, ............
In the end, shift the circuit elements one position to the right by the number of defects.
Can be rescued. (3) Continuous Defect FIG. 4 shows two circuit elements (for example, C_{i + 1}And C_{i + 2}) Continuous
It is a figure when a defect occurs. In this case, switch required
Elementary SW_i-1And SW_iContact point F₁Closed but defective
Circuit element C at the beginning of_{i + 1}And matching subscript
Switch element SW _{i + 1}And all switches to the right
Elementary SW_{i + 2}, SW_{i + 3}, Contact point F₃Is closed.
Therefore, in this case, as shown by the bold line in the figure,
Circuit element C in which a defect occurs_{i + 1}And C_{i + 2}To the right side circuit element
C_{i + 3}, C_{i + 4}, ... are contacts F respectively₃Through
No. I / O section D_{i + 1}, D_{i + 2}, D_{i + 3}, ... connected to
In the end, the circuit elements should be moved to the right by two by the number of defects.
Can be saved and rescued.

The contact control of each switch element may be performed individually for each switch element, but as can be understood from FIGS. 3 and 4, the first circuit element in a predetermined arrangement order is used. Since the position of the contact is determined by the total number of defects, it is preferable to sequentially transmit the number of defects to each control means. The number of repaired defects depends on the number of contacts (and the number of redundant parts) of each switch element. For example, FIGS.
If the number of contacts is set to "3" (the same number of redundant parts) as described above, the repairable number becomes "2", which is one less than that. Therefore, in order to realize the repair number of "3" or more, the number of contacts and the number of redundant parts may be increased by one more than the required repair number.

Incidentally, FIGS. 6 to 9 are principle diagrams in the case where the repair number is "3". Each switch element SW _{i-1 to} S
W _{i + 3} is provided with _four contacts F _{1 to} F ₄ , respectively, and connects the right end contact F ₄ to the circuit element on the right of the next two contacts (see the broken line). In the case of no defect, as shown in FIG. 7, the contacts F _{1 of} all the switch elements SW _{i-1 to} SW _{i + 3} are closed, and in the case of continuous defect (for example, the number of continuous 3),
As shown in FIG. 8, the contact points of the switch element SW _{i + 1} whose subscript matches the circuit element C _{i + 1 at} the beginning of the defect and all the switch elements SW _{i + 2} , SW _{i + 3,} ... F ₄ closes. In addition, intermittent defects (for example, C _{i + 1} , C _{i + 3,} and C _{i
i + 4} ), as shown in FIG. 9, the switch element SW _{i + 1} whose subscript matches the circuit element C _{i + 1 at} the beginning of the defect.
Along with contact F ₂ is closed, all of the right side switch elements _{SW i + 2, SW i +} 3 ...... of contact F ₄ is closed.

[0017]

Embodiments of the present invention will be described below with reference to the drawings. 10 to 15 are diagrams showing an embodiment of the redundant circuit according to the present invention, and are examples applied to a large-capacity semiconductor memory like the second prior art at the beginning. First, the configuration will be described. In FIG. 10, 30 is a column decoder (see reference numeral 13 in FIG. 18), 31 is a column switch (see FIG. 18).
14).

The column decoder 30 is composed of N parts having the same structure, but in the figure, four parts (D _i-1 , D _i , D _{i + 1} , D _{i + 2} ) of them are representative. It is shown in. Each of these parts (D _i-1 , D _i , D _{i + 1} , D _{i + 2} )
Is a signal to the column switch 31 (decode signal in the figure)
To output a signal from the column switch 31 to a bus (not shown), and corresponds to a signal input / output unit described in the gist of the present application. Hereinafter, four parts of the column decoder 30 (D _i-1 , D _i , D _{i + 1} , D
_{i + 2} ) are called signal input / output units.

Further, the number of column switches 31 is X rather than N (where X is a number of 2 or more, and here, for convenience sake, X =
However, like the column decoder 30, four parts (C _i , C _{i + 1} , C _{i + 2} , C _{i + 3)} of them are shown in the figure like the column decoder 30. ) Is representatively shown. Each of these parts (C _i , C _{i + 1} , C
_{i + 2} , C _{i + 3} ) are used for inputting / outputting signals by the column decoder 30, and correspond to the circuit elements described in the gist of the present application. Below, column switch 31 4
The two parts (C _i , C _{i + 1} , C _{i + 2} , C _{i + 3} ) are called circuit elements.

Although not shown, the column switch 31
X circuit elements are the redundant parts (see symbols C _M-1 and C _{M in} FIG. 1) to be replaced with the defective circuit when any of the N circuit elements has a defect. . N + X circuit elements (C _i , C _{i + 1} , C _{i + 2} , C _{i + 3} ) and N signal input / output units (D _i-1 , D _i , D _{i + 1} , D _{i + 2)} Between)
A switch group 33 is provided, and this switch group 33
Is composed of N switch elements (typically SW _i-1 , SW _i , SW _{i + 1} , SW _{i + 2} ) as many as the signal input / output section.

Each switch element is composed of X + 1 transistor switches (here, three because X = 2), and in short, has three contacts F ₁ , F ₂ , and F ₃ . Contacts F ₁ , F ₂ , F of each switch element
₃ are control means CNT _i-1 , CNT _i , CNT, respectively
ON / OFF is controlled by _{i + 1} and CNT _{i + 2} , but the number of contacts turned on for each switch element is always 1
Is one. For example, if the contacts F ₁ of all the switch elements are turned on, the circuit element C _i-1 and the signal input / output unit D
_{i− 1} , between the circuit element C _i and the signal input / output unit D _i , between the circuit element C _{i + 1} and the signal input / output unit D _{i + 1} , and the circuit element C _{i + 2}
And the signal input / output unit D _{i + 2} are connected to each other. This connection state is a normal state in which no defect has occurred in any circuit element.

If a defect occurs in one circuit element (for example, C _{i + 1} ), the contact points F ₂ of the switch element SW _{i + 1} and all switch elements SW _{i + 2} on the right side of the switch element SW _{i + 1} are connected. Just close it. By doing this, the circuit element C _{i + 2} and the signal input / output unit D _{i + 1} are connected, and the circuit element C _{i + 3} and the signal input / output unit D _{i + 2} are connected, and this is This is done for all switch elements on the right. Therefore, the connection order is shifted to the right by one and the defective circuit element (in this case, C
_{i + 1} ) can be rescued.

In the above example, the number of defects is "1", but when it is "2", the contact F _{3 of the} switch element may be closed. Further, "3" may be closed and the contacts is incremented by 1 contact (reference numeral F ₄ in FIG. 6) in the case of. That is, since it suffices to increase / decrease the number of contacts (and of course, the number of redundant parts) according to the number of required repairs, it is possible to provide a practically useful technique, which is particularly suitable for a large-capacity semiconductor memory. Redundant technology can be realized.

FIG. 11 shows control means (typically CNT _i )
FIG. In this figure, 34 is a decoder which activates one of the eight outputs O _{0 to} O ₇ (high level) in accordance with a combination of 3-bit inputs I ₀ , I ₁ and I _2. . Inputs I ₀ , I ₁ ,
I ₂ is the signal S _i from the fuse circuit 35,
Signals A _i-1 and B _i-1 from the control means CNT _{i-1 in the} preceding stage
, And the truth value of the input / output of the decoder 34 is shown in Table 1 below.

[0025] The outputs O ₁ and O ₂ and O _{3 to} O ₇ of the decoder 34 are ORed by a 2-input OR gate 36 and a 5-input OR gate 37, respectively, and the output (signal A _i ) of the 2-input OR gate 36 is O. _It goes high when either ₁ or O ₂ is active. Further, the output (signal B _i ) of the 5-input OR gate 37 becomes high level when any one of O _{3 to} O ₇ becomes active.

The output O _{0 of the} decoder 34 is applied to the contact F ₁ on the left side of the switch element SW _i , and the output (signal A _i ) of the 2-input OR gate 36 is the switch element SW _{i.
It is applied to} the middle contact F ₂ of _i , and the output (signal B _i ) of the 5-input OR gate 37 is applied to the left contact F ₃ of the switching element SW _i . Therefore, according to this configuration, the signal S from the fuse circuit 35 is
_{When i} is at a low level (fuse is not cut) and the signals A _i-1 and B _i-1 from the control means CNT _i-1 at the previous stage are also at a low level, in other words, when no defect has occurred, Since the output O _{0 of the} decoder 34 becomes high active, the contact F ₁ on the left side of the switch element SW _i can be turned on (connection of C _i and D _i ).

Further, when either of the outputs O ₁ and O ₂ becomes active, from Table 1 above, when the fuse of the fuse circuit 35 is blown (signal S _i = H), or the control means of the previous stage. when the signal a _i-1 from the CNT _i-1 becomes high level, in other words, is when the number of defects is "1", at this time, the output of the two-input OR gate 36 (signal a _i) is at high level Therefore, the center contact F ₂ of the switch element SW _i can be turned on (connection of C _{i + 1} and D _i ).

Further, when any one of the outputs O _{3 to} O ₇ becomes active, from Table 1 above, when the fuse of the fuse circuit 35 is blown (signal S _i = H), and
When the signal A _i-1 from the controller CNT _i-1 of the previous stage becomes a high level, or, either when the signal B _i-1 from the controller CNT _i-1 of the preceding stage becomes the high level In other words, when the number of defects is “2”, and the output (signal B _i ) of the 5-input OR gate 37 becomes high level at this time, the contact F ₃ on the right side of the switch element SW _i is turned on. Can be done (connection of C _{i +2} and D _i ).

The configuration of the control means is not limited to the above example. For example, the configuration may be as shown in FIG. In FIG. 12, the control means CNT _i includes two fuse circuits 40 and 41 and two NAND gates 42 and 4.
It is composed of three, three inverter gates 44 to 46, and one NOR gate 47. In the two fuse circuits 40 and 41, the resistor 48 and the fuse 49 are connected in series between the + power supply V _CC and the ground potential, and the potential at the connection point is inverted by the inverter gate 50 to generate the signal SRA _i. (The signal SRB _{i in the} fuse circuit 41) is taken out, and the output of the inverter gate 50 controls the on / off of the transistor 51 connected to both ends of the resistor 48.

The input / output of the inverter gate 44 is used for the control signal of the contact F ₁ (transmission gate in the figure) at the left end of the switch element SW _i , and
The input / output of the inverter gate 46 is the contact F _{2 in} the middle of the switch element SW _i (transmission gate in the figure).
Further, the input / output of the inverter gate 45 is used as the control signal of the contact F ₃ (transmission gate in the figure) at the right end of the switch element SW _i .

When the input of the inverter gate 44 (the output of the NAND gate 42) is at the low level, the left contact F ₁ is closed, and when the input of the inverter gate 46 (the output of the NOR gate 47) is at the high level, the middle contact is formed. When F ₂ is closed and the input of the inverter gate 45 (output of the NAND gate 43) is at high level, the contact F ₃ on the right side is closed.

Therefore, according to this example, when the input of the inverter gate 44 (the output of the NAND gate 42) becomes the low level and the fuse 49 of the fuse circuit 40 is not cut (signal SRA _i = H), and, (note that it is the logical opposite of that of FIG. 11) signal a _i-1 from the controller CNT _i-1 of the preceding stage at a high level, in other words, there when the number of defects is "0" At this time, since the contact F ₁ on the left side is closed, the same operation as in FIG. 11 can be obtained.

When the input of the inverter gate 46 (the output of the NOR gate 47) becomes high level, the fuse 49 of the fuse circuit 40 is blown (signal SR).
A _i = L), or, when signal A _i-1 from the controller CNT _i-1 of the previous stage is at the low level (note that the 11 is the inverse of logic), and, in the fuse circuit 41 When the fuse 49 is not cut (signal SRB _i = H) and the signal B _i-1 from the control means CNT _{i-1 at the} previous stage is at high level (note that the logic is the opposite of that in FIG. 11). In other words, when the number of defects is "1" and the contact F _{2 in} the middle is closed at this time, the same operation as in FIG. 11 is obtained.

Further, the input of the inverter gate 45 (n
Output of the gate 43) goes high.
When the fuse 49 of the reset circuit 41 is blown (signal S
RB _i= L) or the control means CNT of the preceding stage_i-1from
Signal B_i-1Is at a low level (the reverse logic of Fig. 11
Note that there are two defects.
The right side contact point F₃Closes
The same effect as in FIG. 11 is obtained.

Alternatively, the control means is constructed as shown in FIG.
You may. In FIG. 13, the control means CNT_iIs
Constant control signal CK_AIn the cycle of
NT _i-1Signal A from_i-1Transistor 60 that takes in
And a predetermined control signal CK_BControl of the previous stage with the cycle
Means CNT_i-1Signal from B_i-1Transis to capture
61 and the captured signal A_i-1Regis to latch
62 and the captured signal B_i-1Regis to latch
63 and control signal CK_AIs the control means C of the next stage
NT_{i + 1}An inverter gate 64 for inverting and outputting
Control signal CK_BThe next-stage control means CNT_{i + 1}To
And an inverter gate 65 for inverting and outputting. What
Inverter gates 44, 45, 46 and NOR gate
Since 47 has the same role as that of the same reference numeral in FIG. 12,
I will omit the explanation here.

According to this structure, the data for contact control can be externally written to the registers 62 and 63, and the program by the fuse is not required, so that the efficiency of the redundant work can be improved. . Note that FIG. 14 is a chip floor plan of a large capacity semiconductor memory to which the present invention is applied. In this floor plan, a block 70 including a column predecoder circuit and a sense write circuit and a block 71 including a row predecoder circuit are laid out in a cross shape in the center of the chip, and further, the cross is surrounded by 4 The memory sections 72 to 75 are laid out in each of the two areas. Each of the memory units 72 to 75 has the same configuration. For example, when describing the upper left memory unit 72, one global word decoder 76, a plurality of local memory cell arrays 77 to 79, and each memory cell array are provided. Each of the local column decoders 80 to 82 and the local word decoders 83 to 85 are provided.

FIG. 15 is a partially enlarged view of the memory section 72. The local memory cell arrays 77 to 79 are each composed of several cell matrices 86 to 91, and each cell matrix is provided with a large number of local word lines 92 as represented by one cell matrix 91. . These local word lines 92 are global word lines 93 via the blocks of the local word decoders 83 to 85 and the switch circuit (see the hatched portion).
Connected to.

This switch circuit includes the switch element SW _i and the control means CNT _i of the above-mentioned embodiment. For example, the switch element SW _i has a multiplexer (MUX).
16 corresponds to the broken line portion in FIG. In FIG. 16, 94 to 96 are switch elements, 97 to 99 are control means, and 100 to 102 are ROMs for programming defect information.

[0039]

According to the present invention, between N signal input / output sections of the same configuration and M circuit elements of the same configuration, which is X more than the N signal input / output sections, are provided. N switch elements each having X + 1 contacts are provided, and adjacent X + 1 circuit elements and one signal input / output unit are selectively connected via X + 1 contacts of each switch element. With this configuration, the number of circuit elements corresponding to X can be relieved, and a redundant circuit having a practically sufficient effect can be provided.

[Brief description of drawings]

FIG. 1 is a principle diagram of the present invention.

FIG. 2 is a state diagram of the present invention without defects.

FIG. 3 is a state diagram in the case of a single defect of the present invention.

FIG. 4 is a state diagram in the case of continuous defects of the present invention.

FIG. 5 is a state diagram in the case of the intermittent defect of the present invention.

FIG. 6 is a principle diagram corresponding to the number of defects of 3 of the present invention.

FIG. 7 is a state diagram in the case of no invention defect corresponding to the number of defects of 3;

FIG. 8 is a state diagram in the case of continuous defects of the invention corresponding to the number of defects of 3;

FIG. 9 is a state diagram in the case of an intermittent defect of the invention corresponding to three defects.

FIG. 10 is a configuration diagram of an embodiment.

FIG. 11 is a configuration diagram of a control unit according to an embodiment.

FIG. 12 is a block diagram of another control means of an embodiment.

FIG. 13 is a configuration diagram of still another control unit according to the embodiment.

FIG. 14 is a chip floor plan of one embodiment.

FIG. 15 is a partially enlarged view of FIG.

16 is a block diagram of the switch circuit of FIG.

FIG. 17 is a schematic block diagram of a first conventional example.

FIG. 18 is a schematic block diagram of a second conventional example.

FIG. 19 is a configuration diagram of a second conventional example.

[Explanation of symbols]

C ₁ -C _M: circuitry CNT ₁ to CNT _N: control means D ₁ to D _N: signal output unit _{F 1, ......, F X,} F X + 1: contact SW ₁ to SW _N: switch elements

Claims (2)

[Claims] 1. N signal input / output units (D _{1 to} D) having the same structure.
And _N), between the N signals input section (D ₁ to D _N) by X number than many of M circuit elements of the same configuration (C ₁ ~C _M), each X + 1 single contact _{(F 1, ......, F X} , F X + 1) provided with N number of switching element (SW ₁ to SW _N) having, through the X + 1 pieces of contacts of each switch element (SW ₁ to SW _N) And adjacent X + 1 circuit elements (C _i , ..., C
_{i + X-1} , C _{i + X} ; i is configured so as to selectively connect between 1, 2, ..., N) and one signal input / output unit (D _i ). Redundant circuit. 2. _N control means (CNT _{1 to} CNT) for controlling the operation of each switch element (SW _{1 to} SW _N ).
_N ) and each control means (CNT _i ) is self-checking based on the total number of defects generated from the _first circuit element (C ₁ ) to the i-th circuit element (C _i ) arranged in a predetermined order. 2. The redundant circuit according to claim 1, wherein the number of switching of the contacts of the switch element (SW _i ) in charge of the redundant circuit is determined.