JPH088288B2 - Integrated circuit and manufacturing method thereof - Google Patents

Integrated circuit and manufacturing method thereof

Info

Publication number
JPH088288B2
JPH088288B2 JP5051397A JP5139793A JPH088288B2 JP H088288 B2 JPH088288 B2 JP H088288B2 JP 5051397 A JP5051397 A JP 5051397A JP 5139793 A JP5139793 A JP 5139793A JP H088288 B2 JPH088288 B2 JP H088288B2
Authority
JP
Japan
Prior art keywords
electrode
integrated circuit
high frequency
main surface
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP5051397A
Other languages
Japanese (ja)
Other versions
JPH06244252A (en
Inventor
智昭 左▲梁▼
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP5051397A priority Critical patent/JPH088288B2/en
Publication of JPH06244252A publication Critical patent/JPH06244252A/en
Publication of JPH088288B2 publication Critical patent/JPH088288B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は集積回路及びその製造方
法に関し、特にモノリシックマイクロ波集積回路に関す
る。
FIELD OF THE INVENTION The present invention relates to integrated circuits and methods of making the same, and more particularly to monolithic microwave integrated circuits.

【0002】[0002]

【従来の技術】従来のモノリシックマイクロ波集積回路
の接地方法は主として、ボンディングワイヤによる方法
とバイアホール(貫通孔)を用いて接地する方法が採ら
れてきた。10[GHZ ]以下の比較的周波数が低い領
域ではボンディングワイヤによる接地方法が採られる。
しかし、ミリ波等の高い周波数領域では、ボンディング
ワイヤによる接地方法はインダクタンスが高いためにモ
ノリシックマイクロ波集積回路が特性劣化するのでバイ
アホールによる接地方法が多く用いられる。
2. Description of the Related Art Conventionally, a grounding method for a monolithic microwave integrated circuit has mainly been a method using a bonding wire or a method using a via hole (through hole). A grounding method using a bonding wire is adopted in a region of 10 [GHZ] or less, which has a relatively low frequency.
However, in a high frequency region such as a millimeter wave, the grounding method using a bonding wire is often used because the grounding method using a bonding wire has a high inductance and deteriorates the characteristics of the monolithic microwave integrated circuit.

【0003】バイアホールは作成工程上、透明なガラス
板等の支持板にモノリシックマイクロ波集積回路の裏面
を表にして貼りつけ、裏面からバイアホールを加工する
方法が一般的に行われる。
In the process of forming the via hole, a method is generally used in which the back surface of the monolithic microwave integrated circuit is attached to a supporting plate such as a transparent glass plate so that the back surface is the front surface, and the via hole is processed from the back surface.

【0004】[0004]

【発明が解決しようとする課題】最近はオンウエハによ
る測定技術が発達し、ミリ波でもオンウエハの測定プロ
ーブによってSパラメータ等の高周波特性を精度良く測
定することが可能となってきた。
Recently, on-wafer measurement technology has been developed, and it has become possible to accurately measure high-frequency characteristics such as S-parameters even with millimeter waves by using an on-wafer measurement probe.

【0005】しかし、上述したバイアホールを用いたモ
ノリシックマイクロ波集積回路では、ウエハ状態ではガ
ラス板等に貼りつけてしまうため、オンウエハ測定する
ことができない。したがって、特開平2−27746号
公報に開示されているように、ウエハからチップ化した
状態で測定したり、コプレーナ回路やFET単体を裏面
のバイアホール工程する前に測定したりしていた。
However, in the above-described monolithic microwave integrated circuit using via holes, since it is stuck to a glass plate or the like in a wafer state, on-wafer measurement cannot be performed. Therefore, as disclosed in Japanese Unexamined Patent Publication No. 2-27746, it is measured in a state of being made into a chip from a wafer, or before the coplanar circuit or the single FET is subjected to the via hole process on the back surface.

【0006】チップ化してオンウエハで測定する例が図
2に示されている。これは、高周波プローブ101の接
地電極107と集積回路102のバイアホール100の
電極104とを電気的に接触させ、高周波プローブの信
号ライン106とモノリシックマイクロ波集積回路の入
出力端子103とを電気的に接触させて測定を行うもの
である。なお、105は電源端子、108は電源プロー
ブである。
FIG. 2 shows an example of on-wafer measurement after being made into chips. This electrically contacts the ground electrode 107 of the high frequency probe 101 and the electrode 104 of the via hole 100 of the integrated circuit 102, and electrically connects the signal line 106 of the high frequency probe and the input / output terminal 103 of the monolithic microwave integrated circuit. The measurement is carried out by contacting with. In addition, 105 is a power supply terminal and 108 is a power supply probe.

【0007】このチップ化して測定する方法では、チッ
プ毎に高周波プローブ101と電源プローブ108とを
アライメントする必要があり、時間がかかるため、選別
等には向かないという欠点がある。コプレーナ回路にし
てバイアホールを形成する前に測定する方法では、バイ
アホールを形成した前後で伝送線路の構成が変化するた
めに特性が変化し、やはり高周波での選別作業には適し
ていないという欠点がある。
[0007] In this method of making a chip for measurement, it is necessary to align the high frequency probe 101 and the power supply probe 108 for each chip, and it takes time, so that it is not suitable for selection and the like. In the method of measuring before forming via holes in a coplanar circuit, the characteristics change because the configuration of the transmission line changes before and after the via holes are formed, which is also not suitable for high-frequency sorting work. There is.

【0008】本発明は上述した従来の欠点を解決するた
めになされたものであり、その目的はオンウエハによる
高周波特性の測定を容易に行うことのできる集積回路及
びその製造方法を提供することである。
The present invention has been made to solve the above-mentioned conventional drawbacks, and an object of the present invention is to provide an integrated circuit capable of easily measuring high-frequency characteristics on-wafer and a manufacturing method thereof. .

【0009】[0009]

【課題を解決するための手段】上記欠点を解決するため
本発明による集積回路は、半導体ウエハ基板のスクライ
ブ領域に設けられ前記基板の一主表面上の電極と他主表
面上の電極とを電気的に接続する貫通孔を有し、前記他
主表面上の電極を用いて自回路の高周波特性を測定する
ようにしたことを特徴とする。
In order to solve the above-mentioned drawbacks, an integrated circuit according to the present invention has an electrode provided on a scribe region of a semiconductor wafer substrate and electrically connected to an electrode on one main surface of the substrate and an electrode on the other main surface thereof. It is characterized in that it has a through hole that is electrically connected thereto, and that the high frequency characteristic of the own circuit is measured by using the electrode on the other main surface.

【0010】また、本発明による集積回路の製造方法
は、半導体ウエハ基板上の回路の一主表面上の電極と他
主表面上の電極とを電気的に接続する貫通孔を、前記基
板のスクライブ領域に設ける第1のステップと、前記他
主表面上の電極を用いて前記回路の高周波特性を測定し
て、この測定後に前記スクライブ領域により前記基板を
切断してチップ化する第2のステップとを含むことを特
徴とする。
Further, in the method of manufacturing an integrated circuit according to the present invention, a through hole for electrically connecting an electrode on one main surface of a circuit on a semiconductor wafer substrate and an electrode on the other main surface is formed with a scribe of the substrate. A first step of providing the region, and a second step of measuring the high-frequency characteristic of the circuit using the electrode on the other main surface, and cutting the substrate by the scribe region to form a chip after the measurement. It is characterized by including.

【0011】[0011]

【実施例】次に、本発明について図面を参照して説明す
る。
Next, the present invention will be described with reference to the drawings.

【0012】図1は本発明による集積回路の一実施例の
概略構成図であり、ウエハの表面(a)と裏面(b)と
が示されている。図において、表面(a)のFET8
は、高周波入出力端子1及び電源端子4に接続されてい
る。そして、表面(a)の高周波入出力端子1を、スク
ライブ領域2に形成したバイアホール3を介して裏面に
接続する。電源端子4も同様に、バイアホール5によっ
て裏面に接続する。裏面(b)では、マイクロストリッ
プラインの接地導体とコプレーナ線路化した測定用の高
周波入出力端子6を電極として形成し、また電源端子4
とバイアホール5で接続された端子7を電極として形成
する。なお、ウエハ上のすべての回路について同様に端
子を形成するものとする。
FIG. 1 is a schematic configuration diagram of an embodiment of an integrated circuit according to the present invention, showing a front surface (a) and a back surface (b) of a wafer. In the figure, the FET 8 on the surface (a)
Are connected to the high frequency input / output terminal 1 and the power supply terminal 4. Then, the high frequency input / output terminal 1 on the front surface (a) is connected to the rear surface through the via hole 3 formed in the scribe region 2. Similarly, the power supply terminal 4 is also connected to the back surface by the via hole 5. On the back surface (b), a grounding conductor of a microstrip line and a high-frequency input / output terminal 6 for measurement, which is a coplanar line, are formed as electrodes, and a power supply terminal 4 is also provided.
The terminal 7 connected to the via hole 5 is formed as an electrode. Note that terminals are similarly formed for all circuits on the wafer.

【0013】かかる構成によれば、裏面のバイアホール
形成工程完了後、高周波入出力端子6に高周波プローブ
を接触させ、電源端子7に電源用プローブを接触させれ
ば高周波測定を行うことが可能になる。
According to this configuration, after the completion of the via hole forming process on the back surface, the high frequency input / output terminal 6 is brought into contact with the high frequency probe, and the power source terminal 7 is brought into contact with the power source probe. Become.

【0014】ここで、バイアホールによる測定上の影響
は、バイアホール部のインダクタンスとして考えること
ができるが、バイアホールを形成する場合、モノシリッ
クマイクロ波集積回路の半導体基板厚は100[μm]
程度と少なく、バイアホールのインダクタンスは小さい
ためほとんど無視できる。
Here, the influence of the via hole on the measurement can be considered as the inductance of the via hole portion, but when forming the via hole, the semiconductor substrate thickness of the monolithic microwave integrated circuit is 100 [μm].
It is negligible, and the inductance of the via hole is small, so it can be almost ignored.

【0015】つまり、本実施例による集積回路は、以下
のように製造するのである。すなわち、半導体ウエハ基
板上の回路の表面電極と裏面電極とを電気的に接続する
貫通孔(バイアホール)を基板上のスクライブ用領域に
設ける。その後にその裏面電極を用いて回路の高周波特
性を測定して、この測定後にスクライブ領域により基板
を切断してチップ化するのである。そして、高周波測定
後、スクライブ領域2はチップ化するために除去され、
バイアホール3,5も除去される。そのため、裏面部の
端子と表面部の端子とは分離されるため、チップ化後の
特性上の影響はないのである。
That is, the integrated circuit according to this embodiment is manufactured as follows. That is, a through hole (via hole) for electrically connecting the front surface electrode and the back surface electrode of the circuit on the semiconductor wafer substrate is provided in the scribe region on the substrate. After that, the high frequency characteristics of the circuit are measured using the back surface electrode, and after this measurement, the substrate is cut into chips by the scribe region. Then, after the high frequency measurement, the scribe area 2 is removed to form a chip,
The via holes 3 and 5 are also removed. Therefore, the terminals on the back surface and the terminals on the front surface are separated from each other, and there is no influence on the characteristics after chip formation.

【0016】従来のようにチップ化して測定する場合
は、チップ毎に方向が定まらないので高周波プローブを
アライメントする必要があった。これに対し、本実施例
ではウエハ状態であるため、従来のテスタと同様の方法
でウエハとしてのアライメントで測定が可能である。そ
して、最終のチップ化した状態とほぼ同様の伝送線路の
状態として測定できるため高周波選別の方法として有効
である。
When the chip is measured as in the conventional case, it is necessary to align the high frequency probe because the direction is not fixed for each chip. On the other hand, in the present embodiment, since the wafer is in a wafer state, it is possible to perform the alignment measurement as a wafer by the same method as the conventional tester. Since it can be measured as a state of the transmission line which is almost the same as the state of the final chip, it is effective as a method of high frequency selection.

【0017】なお、高周波特性に限らず、各種の電気的
特性を測定できる。
Not only the high frequency characteristics but also various electric characteristics can be measured.

【0018】[0018]

【発明の効果】以上説明したように、本発明によれば、
裏面からバイアホールを形成する工程を持つモノリシッ
クマイクロ波集積回路において表面電極と裏面電極とを
電気的に接続する貫通孔をスクライブ領域に設けること
により、高周波測定による選別が効率良く行え、不良混
入率を下げることができるという効果がある。
As described above, according to the present invention,
In a monolithic microwave integrated circuit that has a process of forming a via hole from the back surface, by providing a through hole that electrically connects the front surface electrode and the back surface electrode in the scribe area, selection by high frequency measurement can be performed efficiently, and the defect mixing rate There is an effect that can be lowered.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の実施例による集積回路の概略構成図で
り、(a)はウエハの表面、(b)はウエハの裏面で
る。
[1] Ri <br/> Oh a schematic diagram of an integrated circuit according to an embodiment of the present invention, (a) shows the surface of the wafer, (b) is a rear surface of the wafer
Oh Ru.

【図2】従来の集積回路の高周波測定方法の概略図であ
る。
FIG. 2 is a schematic diagram of a conventional integrated circuit high frequency measurement method.

【符号の説明】[Explanation of symbols]

1,6 高周波入出力端子 2 スクライブ領域 3,5 バイアホール 4,7 電源端子 8 FET 1,6 High frequency input / output terminal 2 Scribing area 3,5 Via hole 4,7 Power supply terminal 8 FET

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 半導体ウエハ基板のスクライブ領域に設
けられ前記基板の一主表面上の電極と他主表面上の電極
とを電気的に接続する貫通孔を有し、前記他主表面上の
電極を用いて自回路の高周波特性を測定するようにした
ことを特徴とする集積回路。
1. An electrode on the other main surface having a through hole provided in a scribe region of a semiconductor wafer substrate for electrically connecting an electrode on the one main surface of the substrate and an electrode on the other main surface. An integrated circuit characterized in that a high frequency characteristic of its own circuit is measured by using.
【請求項2】 半導体ウエハ基板上の回路の一主表面上
の電極と他主表面上の電極とを電気的に接続する貫通孔
を、前記基板のスクライブ領域に設ける第1のステップ
と、前記他主表面上の電極を用いて前記回路の高周波
性を測定して、この測定後に前記スクライブ領域により
前記基板を切断してチップ化する第2のステップとを含
むことを特徴とする集積回路の製造方法。
2. A first step of providing a through hole for electrically connecting an electrode on one main surface of a circuit on a semiconductor wafer substrate and an electrode on another main surface in a scribe region of the substrate, A second step of measuring a high frequency characteristic of the circuit by using an electrode on the other main surface, and cutting the substrate by the scribe region into chips after the measurement. Manufacturing method of integrated circuit.
JP5051397A 1993-02-17 1993-02-17 Integrated circuit and manufacturing method thereof Expired - Fee Related JPH088288B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5051397A JPH088288B2 (en) 1993-02-17 1993-02-17 Integrated circuit and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5051397A JPH088288B2 (en) 1993-02-17 1993-02-17 Integrated circuit and manufacturing method thereof

Publications (2)

Publication Number Publication Date
JPH06244252A JPH06244252A (en) 1994-09-02
JPH088288B2 true JPH088288B2 (en) 1996-01-29

Family

ID=12885813

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5051397A Expired - Fee Related JPH088288B2 (en) 1993-02-17 1993-02-17 Integrated circuit and manufacturing method thereof

Country Status (1)

Country Link
JP (1) JPH088288B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3737405B2 (en) 2001-09-13 2006-01-18 Necマイクロシステム株式会社 Chip manufacturing method and system, circuit board, and circuit chip

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0245339B2 (en) * 1982-09-20 1990-10-09 Mitsubishi Electric Corp HANDOTAISHUSEKIKAIROSOCHI

Also Published As

Publication number Publication date
JPH06244252A (en) 1994-09-02

Similar Documents

Publication Publication Date Title
US5594358A (en) Radio frequency probe and probe card including a signal needle and grounding needle coupled to a microstrip transmission line
US20060170438A1 (en) Probe card
JPH05283487A (en) Wiring for high-frequency signal and bonding device therefor
EP0257870B1 (en) A semiconductor device, making and testing thereof
EP0605812A1 (en) Microwave monolithic integrated circuit testing
JPH088288B2 (en) Integrated circuit and manufacturing method thereof
JPH07122602A (en) High frequency probe and probe circuit
JP2002334935A (en) High-frequency circuit chip, high-frequency circuit device having the chip, and method of manufacturing the same
JPH0227746A (en) Microwave integrated circuit and manufacture thereof
JP3435241B2 (en) Evaluation device for tape-shaped semiconductor mounting device
JPH04206845A (en) High frequency probe pin
JP2568495B2 (en) Semiconductor device
JP2990141B2 (en) Method for manufacturing high frequency multi-chip module
JP2002280428A (en) Semiconductor device manufacturing method
JP3852589B2 (en) Microwave integrated circuit, dielectric substrate
JPS62294303A (en) Semiconductor device and its manufacture
JPH02285264A (en) Probe card for testing microwave semiconductor part
JPS62115783A (en) Semiconductor device
JPH09102521A (en) Probe card
JP6536283B2 (en) High frequency module and method of manufacturing high frequency module
JPH04336441A (en) Microwave probe head
JPH03108350A (en) Measuring jig
JPH02242165A (en) Probe unit
JPS6378070A (en) Semiconductor device
JPH02210269A (en) Probe device

Legal Events

Date Code Title Description
A621 Written request for application examination

Effective date: 20031215

Free format text: JAPANESE INTERMEDIATE CODE: A621

A977 Report on retrieval

Effective date: 20060501

Free format text: JAPANESE INTERMEDIATE CODE: A971007

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20060620

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20070227

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20070418

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20080507

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20080602

FPAY Renewal fee payment (prs date is renewal date of database)

Year of fee payment: 3

Free format text: PAYMENT UNTIL: 20110606

R150 Certificate of patent (=grant) or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

LAPS Cancellation because of no payment of annual fees