JPH088259A - Manufacture of semiconductor electrode - Google Patents

Manufacture of semiconductor electrode

Info

Publication number
JPH088259A
JPH088259A JP6141954A JP14195494A JPH088259A JP H088259 A JPH088259 A JP H088259A JP 6141954 A JP6141954 A JP 6141954A JP 14195494 A JP14195494 A JP 14195494A JP H088259 A JPH088259 A JP H088259A
Authority
JP
Japan
Prior art keywords
copper
sulfur
bump
plating bath
strength
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP6141954A
Other languages
Japanese (ja)
Other versions
JP3463353B2 (en
Inventor
Kichiji Abe
吉次 阿部
Kazuo Tanaka
和夫 田中
Keiji Mayama
恵次 真山
Motoki Ito
基樹 伊藤
Motoaki Hyodo
元昭 兵藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Denso Corp
Original Assignee
NipponDenso Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NipponDenso Co Ltd filed Critical NipponDenso Co Ltd
Priority to JP14195494A priority Critical patent/JP3463353B2/en
Publication of JPH088259A publication Critical patent/JPH088259A/en
Application granted granted Critical
Publication of JP3463353B2 publication Critical patent/JP3463353B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation

Landscapes

  • Electroplating And Plating Baths Therefor (AREA)

Abstract

PURPOSE:To ensure the strength of junction between a copper bump and a solder layer and the durability and strength of electrodes with reliability, by controlling the concentration of sulfur in the copper bump to a specified value or below. CONSTITUTION:A solder layer 231, 232 is placed on circuit conductors 251, 252 formed on the surface of a ceramic substrate 24. Heat is applied to melt the solder 231, 232 so that copper bumps 221, 222 will be mechanically and electrically connected with the circuit conductors 251, 252 on the ceramic substrate 24 through the solder 231, 232. When the concentration of sulfur in the copper bumps is set to 50ppm or below, it is possible to form semiconductor electrodes without degradation in endurance and strength. The solder bath used is composed of 50g/l of copper sulfate and sulfuric acid, each and 60ppm of chlorine with additive concentration varied as required. This ensures the strength of junction between the copper bumps and the solder layer and the durability and strength of the electrodes.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】この発明は、半導体ウエハ上に純
度の高い銅バンプを形成することにより、耐久強度低下
の少ないフリップチップIC用の電極、すなわち半導体
電極の製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for producing a flip-chip IC electrode, that is, a semiconductor electrode, in which durability bumps are less deteriorated by forming highly pure copper bumps on a semiconductor wafer.

【0002】[0002]

【従来の技術】フリップチップICは、回路要素を集積
形成した半導体チップに対して、その回路要素に対応し
た導出端子部に位置して突出電極を形成し、この電極を
介して回路配線が施されたセラミック等により構成され
る基板に接続して構成される。ここで、半導体チップに
形成される突出電極はバンプ電極として知られているも
ので、図4はそのバンプ電極部の断面構成を示してい
る。
2. Description of the Related Art In a flip chip IC, a protruding electrode is formed at a lead-out terminal portion corresponding to a circuit element on a semiconductor chip on which circuit elements are integrated, and circuit wiring is provided through this electrode. It is configured by being connected to a substrate made of a ceramic or the like. Here, the protruding electrode formed on the semiconductor chip is known as a bump electrode, and FIG. 4 shows a sectional configuration of the bump electrode portion.

【0003】すなわち、回路要素が集積形成された半導
体チップ11の面に、バンプ12が突設形成されているもの
で、このバンプ12とセラミック基板13の表面に形成され
た導体回路14とが、はんだ15によって機械的に且つ電気
的に接続されるようにしている。バンプ12は、はんだ濡
れ性の良好な金属、例えば金、銀、銅等の材料を用いて
構成され、コスト等の面を考慮した場合には銅が一般的
に使用されるもので、電解メッキによって半導体チップ
11表面の所定の個所に突設形成される。
That is, bumps 12 are formed so as to project from the surface of a semiconductor chip 11 on which circuit elements are integrated, and the bumps 12 and the conductor circuit 14 formed on the surface of a ceramic substrate 13 are It is designed to be mechanically and electrically connected by the solder 15. The bumps 12 are composed of a metal having a good solder wettability, for example, a material such as gold, silver, or copper, and copper is generally used when cost is taken into consideration. By semiconductor chip
11 Protrudingly formed at a predetermined position on the surface.

【0004】しかし、この様に電解メッキによって形成
されたバンプ12に対して、セラミック基板13の表面の導
体回路14にはんだ15を介して接続した状態で、100℃
以上の高温下に長時間放置すると、はんだ15中に含まれ
る錫がバンプ12を構成する銅と合金を生成するようにな
り、バンプ12とはんだ15との間が接続不良の状態に至る
ようになる問題を有する。
However, the bumps 12 thus formed by electrolytic plating are connected to the conductor circuits 14 on the surface of the ceramic substrate 13 via the solders 15 at 100 ° C.
If left in the above high temperature for a long time, the tin contained in the solder 15 will form an alloy with the copper forming the bump 12, so that the connection between the bump 12 and the solder 15 may become defective. Have a problem.

【0005】この様な接続不良の問題に対処するため、
銅によって構成されるバンプ12を、銅−錫拡散膜厚を考
慮して充分に厚く形成することが考えられる。しかし、
バンプ12の厚さが20〜30μm程度に設定される場合
に、銅−錫拡散層の生長量は20μm以下となり、接続
不良の問題は解決されるが、半導体チップ11とセラミッ
ク基板13との接合強度、すなわち電極強度が、耐久性保
証の目安である初期強度の半分以下となってしまう。し
たがって、特に高温環境下において使用に適さなくな
る。
In order to deal with such a problem of poor connection,
It is conceivable to form the bump 12 made of copper sufficiently thick in consideration of the copper-tin diffusion film thickness. But,
When the thickness of the bump 12 is set to about 20 to 30 μm, the growth amount of the copper-tin diffusion layer becomes 20 μm or less, and the problem of connection failure is solved, but the bonding between the semiconductor chip 11 and the ceramic substrate 13 is solved. The strength, that is, the electrode strength, becomes half or less of the initial strength, which is a standard for guaranteeing durability. Therefore, it becomes unsuitable for use especially in a high temperature environment.

【0006】図4で示したような銅バンプ12をはんだ15
を介してセラミック基板13の導体回路14に接続するよう
にした電極構造において、これを例えば150℃の高温
環境の下に1000時間放置すると、バンプ12を構成す
る銅とはんだ15に含まれる錫とが相互拡散し、銅−錫拡
散(合金)層16が生成される。この様に生成された拡散
層16の近傍をミクロ観察してみると、銅バンプ12と拡散
層16との境界部分に多数のボイド17が生成されているこ
とが確認され、同時にこれらのボイド17の内部に硫黄が
偏析していることが確認された。
A copper bump 12 as shown in FIG.
In the electrode structure that is connected to the conductor circuit 14 of the ceramic substrate 13 via the, when this is left for 1000 hours in a high temperature environment of, for example, 150 ° C., copper that forms the bump 12 and tin contained in the solder 15 Interdiffuse to form a copper-tin diffusion (alloy) layer 16. When microscopically observing the vicinity of the diffusion layer 16 thus formed, it was confirmed that a large number of voids 17 were formed at the boundary portion between the copper bump 12 and the diffusion layer 16, and at the same time, these voids 17 were formed. It was confirmed that sulfur was segregated inside the.

【0007】この様にボイド17が形成され、その内部に
硫黄が偏析される過程を経時的に精査した結果、バンプ
12を形成する電解メッキを行うときに、その皮膜中に共
析した硫黄が高熱環境下での放置によって銅によって構
成されたバンプ12の上に偏析し、銅−錫の相互拡散によ
って生じた微小ボイドを成長させ、耐久強度が低下され
るようになることを見出した。
As a result of scrutinizing the process in which the voids 17 are formed and the sulfur is segregated inside the voids 17,
When electrolytic plating is performed to form 12, the co-deposited sulfur in the film segregates on the bumps 12 made of copper when left in a high-temperature environment, resulting in minute amounts of copper-tin interdiffusion. It was found that the voids grow and the durability strength is lowered.

【0008】ここで、バンプ12を形成する電解銅メッキ
は、毒性の低い酸性のメッキ浴を適用しているものであ
るが、この電解メッキに際してメッキ皮膜に共析して光
沢化をもたらすために、メッキ浴に対してジメルカプト
ベンゾチアゾール等の硫黄含有有機物と、メッキ界面に
吸着して皮膜の均一性を向上させるポリエチレングリコ
ール等の高分子界面活性剤が同時に添加されている。そ
して、このメッキ浴に対する添加剤である硫黄含有有機
物に含まれる硫黄が偏析して、電極の耐久強度に大きな
影響を与えている。
Here, the electrolytic copper plating for forming the bumps 12 uses an acidic plating bath having low toxicity. In order to bring about brightening by electro-depositing on the plating film during this electrolytic plating. Further, a sulfur-containing organic substance such as dimercaptobenzothiazole and a polymer surfactant such as polyethylene glycol which is adsorbed on the plating interface to improve the uniformity of the coating are simultaneously added to the plating bath. Then, the sulfur contained in the sulfur-containing organic substance, which is an additive to the plating bath, is segregated and has a great influence on the durability strength of the electrode.

【0009】[0009]

【発明が解決しようとする課題】この発明は上記のよう
な点に鑑みなされたもので、銅メッキによって形成され
たバンプにおいて、特にこの銅バンプとはんだ層との間
の接合強度が確実に確保されて、電極の耐久強度が確実
に得られるようにして、高温環境下においても充分な信
頼性が確保されるようにする半導体電極の製造方法を提
供しようとするものである。
SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and in a bump formed by copper plating, particularly the bonding strength between the copper bump and the solder layer is reliably ensured. Thus, it is an object of the present invention to provide a method for manufacturing a semiconductor electrode that ensures the durability of the electrode and ensures sufficient reliability even in a high temperature environment.

【0010】[0010]

【課題を解決するための手段】この発明に係る半導体電
極の製造方法は、半導体チップ面のバンプ電極形成領域
に対応して開口の形成されたマスクを用い、電解メッキ
によって銅バンプを形成するもので、このバンプ形成工
程により形成された前記銅バンプの上にはんだ層を形成
する。前記電解メッキによるバンプ形成工程では、メッ
キ浴に含まれる不純物である硫黄含有有機物の含有量に
よって、硫黄の共析量が50ppm以下に制御されるよ
うにしている。このために、例えばメッキ浴は硫酸銅浴
によって構成し、このメッキ浴に硫黄含有有機物および
高分子ポリマーが添加剤として添加した場合に、硫黄含
有有機物の含有量が0.5vol%以下に管理されるよ
うにしている。
A method of manufacturing a semiconductor electrode according to the present invention forms a copper bump by electrolytic plating using a mask having an opening corresponding to a bump electrode forming region on a semiconductor chip surface. Then, a solder layer is formed on the copper bumps formed in the bump forming step. In the bump forming step by the electroplating, the amount of sulfur eutectoid is controlled to 50 ppm or less depending on the content of the sulfur-containing organic substance which is an impurity contained in the plating bath. For this reason, for example, the plating bath is composed of a copper sulfate bath, and when the sulfur-containing organic substance and the polymer are added to the plating bath as an additive, the content of the sulfur-containing organic substance is controlled to 0.5 vol% or less. I am trying to do it.

【0011】[0011]

【作用】この様に構成される半導体電極の製造方法にあ
っては、銅メッキ皮膜中に共析した硫黄成分が電極の耐
久強度の低下に影響を及ぼすものであることに着目し、
銅バンプ中の硫黄濃度と高温環境下での放置による電極
の耐久強度との関係に基づいて、銅バンプ中の硫黄濃度
を50ppm以下とすることにより、電極耐久強度の低
下の少ない半導体電極が形成できることを見出した。そ
して、電解メッキ浴に対する添加剤において硫黄含有有
機物の含有量を適正化して、銅バンプ中の硫黄濃度を下
げるようにしているもので、高温環境下で長時間放置し
ても電極耐久強度の低下されない、信頼性に富む半導体
電極が形成されるようになる。
In the method of manufacturing a semiconductor electrode having such a structure, paying attention to the fact that the sulfur component co-deposited in the copper plating film has an influence on the decrease in the durability strength of the electrode.
Based on the relationship between the sulfur concentration in the copper bumps and the durability strength of the electrode when left in a high temperature environment, the sulfur concentration in the copper bumps is set to 50 ppm or less to form a semiconductor electrode with little decrease in electrode durability strength. I found that I could do it. Then, the content of the sulfur-containing organic substance in the additive to the electrolytic plating bath is optimized to reduce the sulfur concentration in the copper bumps, and the durability of the electrode is reduced even when left in a high temperature environment for a long time. As a result, a highly reliable semiconductor electrode is formed.

【0012】[0012]

【実施例】以下、図面を参照してこの発明の一実施例を
説明する。図1においてまず回路要素が集積形成された
半導体チップ21の表面にレジストマスクが形成されるも
ので、このマスクには半導体チップ21に形成される回路
要素の電極導出部に対応して開口が形成されている。そ
して、このレジストマスク上から、その開口部に対応し
て半導体チップ21の表面に部分銅メッキを施し、銅バン
プ221 、222 を突設形成する。この場合、銅バンプ221
、222 の厚さは、それぞれ35μmとされるようにメ
ッキ時間が制御される。この様に銅バンプ221 、222 が
メッキ形成されたならば、レジストマスク等の不要部分
をエッチング除去し、半導体チップ21面に突設された銅
バンプ221 、222 それぞれの頂部にはんだ231 、232 の
層を形成する。ここで、このはんだ231 、232 の組成は
Sn40%とした。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. In FIG. 1, a resist mask is first formed on the surface of a semiconductor chip 21 on which circuit elements are integrally formed, and openings are formed in this mask in correspondence with the electrode lead-out portions of the circuit elements formed on the semiconductor chip 21. Has been done. Then, partial copper plating is applied to the surface of the semiconductor chip 21 corresponding to the openings from above the resist mask to form copper bumps 221 and 222 in a protruding manner. In this case, the copper bump 221
The plating time is controlled so that the thickness of each of the electrodes 222 and 222 is 35 μm. When the copper bumps 221 and 222 are formed by plating in this way, unnecessary portions such as a resist mask are removed by etching, and the solder bumps 231 and 232 on the tops of the copper bumps 221 and 222 protruding from the surface of the semiconductor chip 21 respectively. Form the layers. Here, the composition of the solders 231 and 232 was Sn 40%.

【0013】この様に銅バンプ221 、222 さらにその上
にはんだ231 、232 の層が形成されたならば、洗浄しカ
ットされた半導体チップ21をセラミック基板24に組み付
けて一体化する。すなわち、セラミック基板24の表面に
形成された回路導体25に上にはんだ231 、232 の層を対
接し、熱を加えてはんだ231 、232 を溶解して、銅バン
プ221 、222 がはんだ231 、232 を介してセラミック基
板24の回路導体251 、252 に機械的に且つ電気的に接合
されるようにする。
After the copper bumps 221 and 222 and the layers of the solders 231 and 232 are formed on the copper bumps 221 and 222 in this manner, the cleaned and cut semiconductor chip 21 is assembled and integrated with the ceramic substrate 24. That is, the layers of solder 231 and 232 are contacted on the circuit conductor 25 formed on the surface of the ceramic substrate 24, heat is applied to melt the solders 231 and 232, and the copper bumps 221 and 222 are soldered to the solders 231 and 232. And the circuit conductors 251 and 252 of the ceramic substrate 24 are mechanically and electrically bonded to each other.

【0014】銅メッキ皮膜中に共析した硫黄成分が、電
極の耐久強度の低下に影響を及ぼすものであることに着
目して、銅バンプ中の硫黄濃度と電極耐久強度との関係
をみると図2で示すようになる。すなわち、銅バンプ中
の硫黄濃度を50ppm以下の状態とすると、耐久強度
低下の少ない半導体電極が形成可能とされる。
Looking at the relationship between the sulfur concentration in the copper bumps and the electrode durability strength, paying attention to the fact that the sulfur component co-deposited in the copper plating film affects the reduction of the electrode durability strength. As shown in FIG. That is, when the sulfur concentration in the copper bumps is set to 50 ppm or less, it is possible to form a semiconductor electrode with a small decrease in durability strength.

【0015】この様な銅バンプ221 、222 を形成するた
めの銅メッキ工程を考察すると、この銅メッキ工程にお
いては毒性の少ない酸性銅メッキ浴を使用し、2A/d
2程度の電流密度下で実施される。この際、使用され
るメッキ浴は硫酸銅および硫酸が各50g/リットル、
および塩素60ppmとされるもので、添加剤の濃度は
適宜変化される。
Considering a copper plating process for forming such copper bumps 221 and 222, in this copper plating process, an acidic copper plating bath having low toxicity is used and 2 A / d is used.
It is carried out under a current density of about m 2 . At this time, the plating bath used contains copper sulfate and sulfuric acid at 50 g / liter each,
And chlorine of 60 ppm, and the concentration of the additive is appropriately changed.

【0016】添加剤として、プリント基板のスルーホー
ルのメッキ等に用いられる市販の酸性銅メッキ添加剤
(主成分:ジメルカプトベンゾチアゾールおよびポリエ
チレングリコール)を適用して銅バンプ221 、222 を形
成した例について説明する。
Example in which copper bumps 221 and 222 are formed by applying a commercially available acidic copper plating additive (main components: dimercaptobenzothiazole and polyethylene glycol) used for plating through-holes of a printed circuit board as an additive Will be described.

【0017】図3はこの様な添加剤を使用した場合にお
ける、メッキ浴中の硫黄含有有機物(ジメルカプトベン
ゾチアゾール等)と、銅バンプ中に共析する硫黄濃度と
の関係を示すもので、メッキ浴中の硫黄含有有機物の濃
度増加に伴って、硫黄の共析量が増加する傾向にある。
この様な添加剤を使用した場合、メッキ浴中の硫黄含有
有機物濃度を、0.5vol%以下に管理するようにす
れば、電極の耐久強度の低下を抑制することが可能とさ
れる。
FIG. 3 shows the relationship between the sulfur-containing organic substance (dimercaptobenzothiazole etc.) in the plating bath and the concentration of sulfur co-deposited in the copper bump when such an additive is used. The amount of sulfur eutectoid tends to increase with an increase in the concentration of the sulfur-containing organic substance in the plating bath.
When such an additive is used, if the concentration of the sulfur-containing organic substance in the plating bath is controlled to 0.5 vol% or less, it is possible to suppress the deterioration of the durability strength of the electrode.

【0018】添加剤はユーザにおいて管理されているも
ので、その消費量に応じてメッキ浴中に適時補給され
る。一般にメッキ浴中の硫黄含有有機物の濃度は、初期
建浴時に比べて、時間の経過と共に徐々に上昇する傾向
にあり、したがってメッキ浴中の硫黄含有有機物濃度を
0.5vol%以下に維持するためには、特定される周
期(例えば1〜2か月程度)において所定のメッキ浴を
少量づつ更新して、硫黄含有有機物の濃度を低くされる
ようにすればよい。この場合、形成される銅バンプの硬
度によって、メッキ浴中の硫黄濃度および共析硫黄濃度
をモニタリングすることができる。
The additive is controlled by the user, and is replenished in the plating bath in a timely manner according to the amount of consumption. Generally, the concentration of the sulfur-containing organic substance in the plating bath tends to gradually rise with time as compared with the time of the initial construction bath, and therefore the concentration of the sulfur-containing organic substance in the plating bath is maintained at 0.5 vol% or less. In order to reduce the concentration of the sulfur-containing organic substance, the predetermined plating bath may be updated little by little in a specified cycle (for example, about 1 to 2 months). In this case, the hardness of the formed copper bump can monitor the sulfur concentration and the eutectoid sulfur concentration in the plating bath.

【0019】メッキ浴中に添加される硫黄含有有機物の
作用は、この添加物における硫黄が銅メッキの皮膜中に
硫化銅として取り込まれて、銅の結晶をち密化してこの
皮膜に対して光沢を与えるようになる。実施例で示した
ような銅バンプを形成するための銅メッキ工程において
は、この様な光沢を与える作用は必ずしも必要としな
い。したがって、所定のメッキ浴に対して添加される前
述した市販の添加剤の中から、硫黄含有有機物を取り除
き、メッキ皮膜の均一性を確保する効果を有する高分子
界面活性剤(ポリエチレングリコール等)のみを添加剤
として適用するようにしてもよい。
The function of the sulfur-containing organic compound added to the plating bath is that the sulfur in this additive is taken into the copper plating film as copper sulfide to densify the copper crystals and make the film glossy. To give. In the copper plating step for forming the copper bumps as shown in the embodiment, such an effect of giving luster is not always necessary. Therefore, only polymeric surfactants (polyethylene glycol, etc.) that have the effect of removing the sulfur-containing organic substances from the above-mentioned commercially available additives that are added to the prescribed plating bath and ensuring the uniformity of the plating film May be applied as an additive.

【0020】この場合、銅バンプ中に対する硫黄の共析
は、10ppm以下となるものであり、電極耐久強度低
下を充分に抑制することができる。また、メッキ浴中に
有機硫黄成分が存在しないものであるため、メッキ浴中
の硫黄濃度の変動等を考慮する必要がなく、メッキ浴管
理が容易となると共にメッキ浴の更新サイクルを例えば
1年以上にもすることができる。
In this case, the co-deposition of sulfur in the copper bumps is 10 ppm or less, and the decrease in electrode durability strength can be sufficiently suppressed. In addition, since there is no organic sulfur component in the plating bath, it is not necessary to consider the fluctuation of the sulfur concentration in the plating bath, the plating bath management becomes easy, and the plating bath renewal cycle is, for example, one year. You can do more than that.

【0021】[0021]

【発明の効果】以上のようにこの発明に係る半導体電極
の製造方法によれば、メッキ浴に対する添加剤におい
て、このメッキ浴中の硫黄含有有機物と銅バンプ中の硫
黄濃度との関係を把握して、硫黄の共析量が50ppm
以下に制御されるように管理することによって、銅メッ
キによって形成されたバンプにおいて、特にこの銅バン
プとはんだ層との間の接合強度が確実に確保されて、電
極の耐久強度が確実に得られるようにして、高温環境下
においても充分な信頼性が確保される。
As described above, according to the method of manufacturing a semiconductor electrode of the present invention, in the additive to the plating bath, the relationship between the sulfur-containing organic substance in the plating bath and the sulfur concentration in the copper bump is grasped. And the amount of co-deposition of sulfur is 50ppm
By controlling so as to be controlled below, particularly in the bump formed by copper plating, the bonding strength between the copper bump and the solder layer is surely ensured, and the durability strength of the electrode is surely obtained. In this way, sufficient reliability is secured even in a high temperature environment.

【図面の簡単な説明】[Brief description of drawings]

【図1】この発明の一実施例に係る製造方法によって作
成された銅バンプを備えた半導体装置の電極構造を説明
する断面図。
FIG. 1 is a sectional view illustrating an electrode structure of a semiconductor device including a copper bump formed by a manufacturing method according to an embodiment of the present invention.

【図2】銅バンプ中の硫黄濃度と電極耐久強度との関係
を示す図。
FIG. 2 is a diagram showing a relationship between a sulfur concentration in a copper bump and electrode durability strength.

【図3】メッキ浴中の硫黄含有有機物濃度と銅バンプ中
の硫黄濃度との関係を示す図。
FIG. 3 is a diagram showing a relationship between a sulfur-containing organic substance concentration in a plating bath and a sulfur concentration in a copper bump.

【図4】従来の半導体装置に設けられるバンプ電極を説
明する図。
FIG. 4 is a diagram illustrating a bump electrode provided in a conventional semiconductor device.

【符号の説明】[Explanation of symbols]

21…半導体チップ、221 、222 …銅バンプ、231 、232
…はんだ、24…セラミック基板、251 、252 …回路導
体。
21 ... Semiconductor chip, 221, 222 ... Copper bump, 231, 232
… Solder, 24… Ceramic substrate, 251, 252… Circuit conductor.

───────────────────────────────────────────────────── フロントページの続き (72)発明者 伊藤 基樹 愛知県刈谷市昭和町1丁目1番地 日本電 装株式会社内 (72)発明者 兵藤 元昭 愛知県刈谷市昭和町1丁目1番地 日本電 装株式会社内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Motoki Ito 1-1, Showa-cho, Kariya city, Aichi Prefecture Nihon Denso Co., Ltd. (72) Inventor Motoaki Hyodo 1-1-chome, Showa town, Kariya city, Aichi prefecture Sozo Co., Ltd.

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 半導体チップの端子導出面に、バンプ電
極形成領域に対応して開口の形成されたパターンマスク
を介して電解メッキによって銅バンプを形成するバンプ
形成工程と、 このバンプ形成工程により形成された前記銅バンプの上
にはんだ層を形成する工程とを具備し、 前記バンプ形成工程にあっては、メッキ浴に含まれる不
純物である硫黄含有有機物の含有量によって、硫黄の共
析量が50ppm以下に制御されるようにしたことを特
徴とする半導体電極の製造方法。
1. A bump forming step of forming a copper bump on a terminal lead-out surface of a semiconductor chip by electrolytic plating through a pattern mask having openings corresponding to bump electrode forming regions, and a bump forming step. And a step of forming a solder layer on the copper bumps, wherein in the bump forming step, the content of sulfur-containing organic matter, which is an impurity contained in the plating bath, results in a co-deposition amount of sulfur. A method for manufacturing a semiconductor electrode, which is controlled to 50 ppm or less.
【請求項2】 前記メッキ浴は硫酸銅および硫酸を含む
硫酸銅浴によって構成され、このメッキ浴に硫黄含有有
機物および高分子ポリマーが添加剤として添加されるも
ので、前記硫黄含有有機物の含有量が0.5vol%以
下に管理されるようにした請求項1記載の半導体電極の
製造方法。
2. The plating bath is composed of copper sulfate and a copper sulfate bath containing sulfuric acid, and a sulfur-containing organic substance and a polymer are added to the plating bath as an additive. The method for manufacturing a semiconductor electrode according to claim 1, wherein the content is controlled to 0.5 vol% or less.
【請求項3】 前記メッキ浴が特定される周期で更新さ
れて、前記硫黄含有有機物の含有量が0.5vol%以
下に維持されるようにした請求項2記載の半導体電極の
製造方法。
3. The method of manufacturing a semiconductor electrode according to claim 2, wherein the plating bath is renewed at a specified cycle so that the content of the sulfur-containing organic material is maintained at 0.5 vol% or less.
JP14195494A 1994-06-23 1994-06-23 Manufacturing method of semiconductor electrode Expired - Fee Related JP3463353B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14195494A JP3463353B2 (en) 1994-06-23 1994-06-23 Manufacturing method of semiconductor electrode

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14195494A JP3463353B2 (en) 1994-06-23 1994-06-23 Manufacturing method of semiconductor electrode

Publications (2)

Publication Number Publication Date
JPH088259A true JPH088259A (en) 1996-01-12
JP3463353B2 JP3463353B2 (en) 2003-11-05

Family

ID=15303998

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14195494A Expired - Fee Related JP3463353B2 (en) 1994-06-23 1994-06-23 Manufacturing method of semiconductor electrode

Country Status (1)

Country Link
JP (1) JP3463353B2 (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100440468C (en) * 2005-01-31 2008-12-03 三洋电机株式会社 Method for manufacturing circuit device
US8334594B2 (en) 2009-10-14 2012-12-18 Advanced Semiconductor Engineering, Inc. Chip having a metal pillar structure
US8552553B2 (en) 2009-10-14 2013-10-08 Advanced Semiconductor Engineering, Inc. Semiconductor device
US8686568B2 (en) 2012-09-27 2014-04-01 Advanced Semiconductor Engineering, Inc. Semiconductor package substrates having layered circuit segments, and related methods
US8884443B2 (en) 2012-07-05 2014-11-11 Advanced Semiconductor Engineering, Inc. Substrate for semiconductor package and process for manufacturing

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100440468C (en) * 2005-01-31 2008-12-03 三洋电机株式会社 Method for manufacturing circuit device
US8334594B2 (en) 2009-10-14 2012-12-18 Advanced Semiconductor Engineering, Inc. Chip having a metal pillar structure
US8552553B2 (en) 2009-10-14 2013-10-08 Advanced Semiconductor Engineering, Inc. Semiconductor device
US8884443B2 (en) 2012-07-05 2014-11-11 Advanced Semiconductor Engineering, Inc. Substrate for semiconductor package and process for manufacturing
US8686568B2 (en) 2012-09-27 2014-04-01 Advanced Semiconductor Engineering, Inc. Semiconductor package substrates having layered circuit segments, and related methods

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