JP3463353B2 - Manufacturing method of semiconductor electrode - Google Patents
Manufacturing method of semiconductor electrodeInfo
- Publication number
- JP3463353B2 JP3463353B2 JP14195494A JP14195494A JP3463353B2 JP 3463353 B2 JP3463353 B2 JP 3463353B2 JP 14195494 A JP14195494 A JP 14195494A JP 14195494 A JP14195494 A JP 14195494A JP 3463353 B2 JP3463353 B2 JP 3463353B2
- Authority
- JP
- Japan
- Prior art keywords
- sulfur
- copper
- bump
- plating bath
- concentration
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
Description
【発明の詳細な説明】
【０００１】
【産業上の利用分野】この発明は、半導体ウエハ上に純
度の高い銅バンプを形成することにより、耐久強度低下
の少ないフリップチップＩＣ用の電極、すなわち半導体
電極の製造方法に関する。
【０００２】
【従来の技術】フリップチップＩＣは、回路要素を集積
形成した半導体チップに対して、その回路要素に対応し
た導出端子部に位置して突出電極を形成し、この電極を
介して回路配線が施されたセラミック等により構成され
る基板に接続して構成される。ここで、半導体チップに
形成される突出電極はバンプ電極として知られているも
ので、図４はそのバンプ電極部の断面構成を示してい
る。
【０００３】すなわち、回路要素が集積形成された半導
体チップ11の面に、バンプ12が突設形成されているもの
で、このバンプ12とセラミック基板13の表面に形成され
た導体回路14とが、はんだ15によって機械的に且つ電気
的に接続されるようにしている。バンプ12は、はんだ濡
れ性の良好な金属、例えば金、銀、銅等の材料を用いて
構成され、コスト等の面を考慮した場合には銅が一般的
に使用されるもので、電解メッキによって半導体チップ
11表面の所定の個所に突設形成される。
【０００４】しかし、この様に電解メッキによって形成
されたバンプ12に対して、セラミック基板13の表面の導
体回路14にはんだ15を介して接続した状態で、１００℃
以上の高温下に長時間放置すると、はんだ15中に含まれ
る錫がバンプ12を構成する銅と合金を生成するようにな
り、バンプ12とはんだ15との間が接続不良の状態に至る
ようになる問題を有する。
【０００５】この様な接続不良の問題に対処するため、
銅によって構成されるバンプ12を、銅−錫拡散膜厚を考
慮して充分に厚く形成することが考えられる。しかし、
バンプ12の厚さが２０〜３０μｍ程度に設定される場合
に、銅−錫拡散層の生長量は２０μｍ以下となり、接続
不良の問題は解決されるが、半導体チップ11とセラミッ
ク基板13との接合強度、すなわち電極強度が、耐久性保
証の目安である初期強度の半分以下となってしまう。し
たがって、特に高温環境下において使用に適さなくな
る。
【０００６】図４で示したような銅バンプ12をはんだ15
を介してセラミック基板13の導体回路14に接続するよう
にした電極構造において、これを例えば１５０℃の高温
環境の下に１０００時間放置すると、バンプ12を構成す
る銅とはんだ15に含まれる錫とが相互拡散し、銅−錫拡
散（合金）層16が生成される。この様に生成された拡散
層16の近傍をミクロ観察してみると、銅バンプ12と拡散
層16との境界部分に多数のボイド17が生成されているこ
とが確認され、同時にこれらのボイド17の内部に硫黄が
偏析していることが確認された。
【０００７】この様にボイド17が形成され、その内部に
硫黄が偏析される過程を経時的に精査した結果、バンプ
12を形成する電解メッキを行うときに、その皮膜中に共
析した硫黄が高熱環境下での放置によって銅によって構
成されたバンプ12の上に偏析し、銅−錫の相互拡散によ
って生じた微小ボイドを成長させ、耐久強度が低下され
るようになることを見出した。
【０００８】ここで、バンプ12を形成する電解銅メッキ
は、毒性の低い酸性のメッキ浴を適用しているものであ
るが、この電解メッキに際してメッキ皮膜に共析して光
沢化をもたらすために、メッキ浴に対してジメルカプト
ベンゾチアゾール等の硫黄含有有機物と、メッキ界面に
吸着して皮膜の均一性を向上させるポリエチレングリコ
ール等の高分子界面活性剤が同時に添加されている。そ
して、このメッキ浴に対する添加剤である硫黄含有有機
物に含まれる硫黄が偏析して、電極の耐久強度に大きな
影響を与えている。
【０００９】
【発明が解決しようとする課題】この発明は上記のよう
な点に鑑みなされたもので、銅メッキによって形成され
たバンプにおいて、特にこの銅バンプとはんだ層との間
の接合強度が確実に確保されて、電極の耐久強度が確実
に得られるようにして、高温環境下においても充分な信
頼性が確保されるようにする半導体電極の製造方法を提
供しようとするものである。
【００１０】
【課題を解決するための手段】この発明は、半導体チッ
プの端子導出面に、バンプ電極形成領域に対応して開口
の形成されたパターンマスクを介して電解メッキによっ
て銅バンプを形成するバンプ形成工程と、このバンプ形
成工程により形成された前記銅バンプの上にはんだ層を
形成する工程とを具備し、前記バンプ形成工程にあって
は、メッキ浴に含まれる不純物である硫黄含有有機物の
含有量によって、硫黄の濃度が５０ｐｐｍ以下に制御さ
れ、前記メッキ浴は硫酸銅および硫酸を含む硫酸銅浴に
よって構成され、このメッキ浴に硫黄含有有機物および
高分子ポリマーが添加剤として添加されるもので、この
添加剤はその消費量に応じてメッキ浴中に適時補給さ
れ、前記メッキ浴中の硫黄含有有機物の濃度は時間の経
過と共に徐々に上昇する傾向に管理され、この硫黄含有
有機物の濃度を前記５０ｐｐｍ以下に維持するため、周
期的に前記メッキ浴を少量づつ更新するようにしてい
る。
【００１１】
【作用】この様に構成される半導体電極の製造方法にあ
っては、銅メッキ皮膜中に共析した硫黄成分が電極の耐
久強度の低下に影響を及ぼすものであることに着目し、
銅バンプ中の硫黄濃度と高温環境下での放置による電極
の耐久強度との関係に基づいて、銅バンプ中の硫黄濃度
を５０ｐｐｍ以下とすることにより、電極耐久強度の低
下の少ない半導体電極が形成できることを見出した。そ
して、電解メッキ浴に対する添加剤において硫黄含有有
機物の含有量を適正化して、銅バンプ中の硫黄濃度を下
げるようにしているもので、高温環境下で長時間放置し
ても電極耐久強度の低下されない、信頼性に富む半導体
電極が形成されるようになる。
【００１２】
【実施例】以下、図面を参照してこの発明の一実施例を
説明する。図１においてまず回路要素が集積形成された
半導体チップ21の表面にレジストマスクが形成されるも
ので、このマスクには半導体チップ21に形成される回路
要素の電極導出部に対応して開口が形成されている。そ
して、このレジストマスク上から、その開口部に対応し
て半導体チップ21の表面に部分銅メッキを施し、銅バン
プ221 、222 を突設形成する。この場合、銅バンプ221
、222 の厚さは、それぞれ３５μｍとされるようにメ
ッキ時間が制御される。この様に銅バンプ221 、222 が
メッキ形成されたならば、レジストマスク等の不要部分
をエッチング除去し、半導体チップ21面に突設された銅
バンプ221 、222 それぞれの頂部にはんだ231 、232 の
層を形成する。ここで、このはんだ231 、232 の組成は
Ｓｎ４０％とした。
【００１３】この様に銅バンプ221 、222 さらにその上
にはんだ231 、232 の層が形成されたならば、洗浄しカ
ットされた半導体チップ21をセラミック基板24に組み付
けて一体化する。すなわち、セラミック基板24の表面に
形成された回路導体25に上にはんだ231 、232 の層を対
接し、熱を加えてはんだ231 、232 を溶解して、銅バン
プ221 、222 がはんだ231 、232 を介してセラミック基
板24の回路導体251 、252 に機械的に且つ電気的に接合
されるようにする。
【００１４】銅メッキ皮膜中に共析した硫黄成分が、電
極の耐久強度の低下に影響を及ぼすものであることに着
目して、銅バンプ中の硫黄濃度と電極耐久強度との関係
をみると図２で示すようになる。すなわち、銅バンプ中
の硫黄濃度を５０ｐｐｍ以下の状態とすると、耐久強度
低下の少ない半導体電極が形成可能とされる。
【００１５】この様な銅バンプ221 、222 を形成するた
めの銅メッキ工程を考察すると、この銅メッキ工程にお
いては毒性の少ない酸性銅メッキ浴を使用し、２Ａ／ｄ
ｍ2程度の電流密度下で実施される。この際、使用され
るメッキ浴は硫酸銅および硫酸が各５０ｇ／リットル、
および塩素６０ｐｐｍとされるもので、添加剤の濃度は
適宜変化される。
【００１６】添加剤として、プリント基板のスルーホー
ルのメッキ等に用いられる市販の酸性銅メッキ添加剤
（主成分：ジメルカプトベンゾチアゾールおよびポリエ
チレングリコール）を適用して銅バンプ221 、222 を形
成した例について説明する。
【００１７】図３はこの様な添加剤を使用した場合にお
ける、メッキ浴中の硫黄含有有機物（ジメルカプトベン
ゾチアゾール等）と、銅バンプ中に共析する硫黄濃度と
の関係を示すもので、メッキ浴中の硫黄含有有機物の濃
度増加に伴って、硫黄の共析量が増加する傾向にある。
この様な添加剤を使用した場合、メッキ浴中の硫黄含有
有機物濃度を、０．５ｖｏｌ％以下に管理するようにす
れば、電極の耐久強度の低下を抑制することが可能とさ
れる。
【００１８】添加剤はユーザにおいて管理されているも
ので、その消費量に応じてメッキ浴中に適時補給され
る。一般にメッキ浴中の硫黄含有有機物の濃度は、初期
建浴時に比べて、時間の経過と共に徐々に上昇する傾向
にあり、したがってメッキ浴中の硫黄含有有機物濃度を
０．５ｖｏｌ％以下に維持するためには、特定される周
期（例えば１〜２か月程度）において所定のメッキ浴を
少量づつ更新して、硫黄含有有機物の濃度を低くされる
ようにすればよい。この場合、形成される銅バンプの硬
度によって、メッキ浴中の硫黄濃度および共析硫黄濃度
をモニタリングすることができる。
【００１９】メッキ浴中に添加される硫黄含有有機物の
作用は、この添加物における硫黄が銅メッキの皮膜中に
硫化銅として取り込まれて、銅の結晶をち密化してこの
皮膜に対して光沢を与えるようになる。実施例で示した
ような銅バンプを形成するための銅メッキ工程において
は、この様な光沢を与える作用は必ずしも必要としな
い。したがって、所定のメッキ浴に対して添加される前
述した市販の添加剤の中から、硫黄含有有機物を取り除
き、メッキ皮膜の均一性を確保する効果を有する高分子
界面活性剤（ポリエチレングリコール等）のみを添加剤
として適用するようにしてもよい。
【００２０】この場合、銅バンプ中に対する硫黄の共析
は、１０ｐｐｍ以下となるものであり、電極耐久強度低
下を充分に抑制することができる。また、メッキ浴中に
有機硫黄成分が存在しないものであるため、メッキ浴中
の硫黄濃度の変動等を考慮する必要がなく、メッキ浴管
理が容易となると共にメッキ浴の更新サイクルを例えば
１年以上にもすることができる。
【００２１】
【発明の効果】以上のようにこの発明に係る半導体電極
の製造方法によれば、メッキ浴に対する添加剤におい
て、このメッキ浴中の硫黄含有有機物と銅バンプ中の硫
黄濃度との関係を把握して、硫黄の濃度が５０ｐｐｍ以
下に制御されるように管理することによって、銅メッキ
によって形成されたバンプにおいて、特にこの銅バンプ
とはんだ層との間の接合強度が確実に確保されて、電極
の耐久強度が確実に得られるようにして、高温環境下に
おいても充分な信頼性が確保される。Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrode for a flip-chip IC, which has a small reduction in durability by forming a high-purity copper bump on a semiconductor wafer, that is, a semiconductor. The present invention relates to a method for manufacturing an electrode. 2. Description of the Related Art In a flip chip IC, a protruding electrode is formed on a semiconductor chip on which circuit elements are integrated and formed at a lead terminal portion corresponding to the circuit element. It is connected to a substrate made of ceramic or the like provided with wiring. Here, the protruding electrode formed on the semiconductor chip is known as a bump electrode, and FIG. 4 shows a cross-sectional configuration of the bump electrode portion. That is, a bump 12 is formed to project from a surface of a semiconductor chip 11 on which circuit elements are integrated and formed. The bump 12 and a conductor circuit 14 formed on the surface of a ceramic substrate 13 are formed as follows. The connection is made mechanically and electrically by the solder 15. The bump 12 is made of a metal having good solder wettability, for example, a material such as gold, silver, or copper.When cost and other aspects are taken into consideration, copper is generally used. By semiconductor chip
11 Protrusions are formed at predetermined locations on the surface. However, the bumps 12 formed by the electrolytic plating are connected to a conductor circuit 14 on the surface of the ceramic substrate 13 via solder 15 at 100 ° C.
If left for a long time at the above high temperature, the tin contained in the solder 15 will form an alloy with the copper constituting the bump 12, so that a poor connection between the bump 12 and the solder 15 may occur. Problems. In order to deal with such a problem of poor connection,
It is conceivable to form the bump 12 made of copper sufficiently thick in consideration of the copper-tin diffusion film thickness. But,
When the thickness of the bump 12 is set to about 20 to 30 μm, the growth amount of the copper-tin diffusion layer becomes 20 μm or less, and the problem of poor connection is solved, but the bonding between the semiconductor chip 11 and the ceramic substrate 13 is solved. The strength, that is, the electrode strength, is less than half the initial strength, which is a measure for guaranteeing durability. Therefore, it is not suitable for use especially in a high temperature environment. [0006] Copper bumps 12 as shown in FIG.
In the electrode structure that is connected to the conductor circuit 14 of the ceramic substrate 13 through the above, if this is left under a high temperature environment of, for example, 150 ° C. for 1000 hours, copper included in the bump 12 and tin contained in the solder 15 Are mutually diffused, and a copper-tin diffusion (alloy) layer 16 is generated. Microscopic observation of the vicinity of the diffusion layer 16 generated in this way confirms that a large number of voids 17 are generated at the boundary between the copper bump 12 and the diffusion layer 16, and at the same time, these voids 17 are formed. It was confirmed that sulfur was segregated in the inside. [0007] As a result of closely examining the process in which the void 17 is formed and the segregation of sulfur inside the void 17 with time,
When performing electroplating to form 12, the eutectoid sulfur in the film segregates on the bump 12 made of copper by being left in a high-temperature environment, and the fine particles generated by the interdiffusion of copper-tin It was found that the voids grew and the durability was reduced. Here, the electrolytic copper plating for forming the bumps 12 employs an acidic plating bath with low toxicity. However, in this electrolytic plating, it is necessary to codeposit a plating film to bring about gloss. A sulfur-containing organic substance such as dimercaptobenzothiazole and a polymer surfactant such as polyethylene glycol which adsorb to the plating interface and improve the uniformity of the film are simultaneously added to the plating bath. Then, the sulfur contained in the sulfur-containing organic substance, which is an additive to the plating bath, is segregated, and greatly affects the durability of the electrode. SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and in the case of a bump formed by copper plating, particularly, the bonding strength between the copper bump and the solder layer is low. It is an object of the present invention to provide a method of manufacturing a semiconductor electrode, which is ensured to ensure the durability of the electrode and ensures sufficient reliability even in a high temperature environment. According to the present invention, a copper bump is formed on a terminal lead-out surface of a semiconductor chip by electrolytic plating through a pattern mask having an opening corresponding to a bump electrode forming region. A bump forming step; and a step of forming a solder layer on the copper bump formed in the bump forming step. In the bump forming step, a sulfur-containing organic material which is an impurity contained in a plating bath is included. , The sulfur concentration is controlled to 50 ppm or less, and the plating bath is constituted by a copper sulfate bath containing copper sulfate and sulfuric acid, and a sulfur-containing organic substance and a polymer are added as additives to the plating bath. This one
Additives may be replenished in the plating bath in a timely manner according to their consumption.
The concentration of the sulfur-containing organic substance in the plating bath is changed over time.
It is controlled to increase gradually with excess
In order to maintain the concentration of organic substances at 50 ppm or less,
A small amount of the fiscal year to the plating bath is in so that you at a time update. In the method of manufacturing a semiconductor electrode configured as described above, attention is paid to the fact that a sulfur component co-deposited in a copper plating film has an effect on a decrease in durability of the electrode. ,
Based on the relationship between the sulfur concentration in the copper bump and the durability of the electrode after being left in a high-temperature environment, a semiconductor electrode with less reduction in electrode durability is formed by setting the sulfur concentration in the copper bump to 50 ppm or less. I found what I could do. In addition, the content of sulfur-containing organic substances in the additive to the electrolytic plating bath is optimized to lower the sulfur concentration in the copper bumps, and the electrode durability decreases even when left for a long time in a high-temperature environment. In this case, a highly reliable semiconductor electrode is formed. An embodiment of the present invention will be described below with reference to the drawings. In FIG. 1, first, a resist mask is formed on the surface of a semiconductor chip 21 on which circuit elements are integrated and formed. In this mask, openings are formed corresponding to electrode lead-out portions of the circuit elements formed on the semiconductor chip 21. Have been. Then, partial copper plating is applied to the surface of the semiconductor chip 21 corresponding to the opening from the resist mask, and copper bumps 221 and 222 are formed to project. In this case, copper bump 221
, 222 are each controlled to have a thickness of 35 μm. When the copper bumps 221 and 222 are thus formed by plating, unnecessary portions such as a resist mask are removed by etching, and solder 231 and 232 are formed on the tops of the copper bumps 221 and 222 projecting from the surface of the semiconductor chip 21. Form a layer. Here, the composition of the solders 231 and 232 was Sn 40%. After the copper bumps 221 and 222 and the layers of the solders 231 and 232 are formed on the copper bumps 221 and 222, the washed and cut semiconductor chip 21 is assembled to the ceramic substrate 24 and integrated. That is, the layers of the solders 231 and 232 are brought into contact with the circuit conductor 25 formed on the surface of the ceramic substrate 24, and the heat is applied to melt the solders 231 and 232, so that the copper bumps 221 and 222 become the solders 231 and 232. Through the substrate and mechanically and electrically connected to the circuit conductors 251 and 252 of the ceramic substrate 24. Focusing on the fact that the sulfur component co-deposited in the copper plating film affects the durability of the electrode, the relationship between the sulfur concentration in the copper bump and the electrode durability is examined. As shown in FIG. That is, when the sulfur concentration in the copper bump is set to 50 ppm or less, it is possible to form a semiconductor electrode with a small decrease in durability. Considering the copper plating process for forming such copper bumps 221 and 222, the copper plating process uses an acidic copper plating bath with low toxicity and uses 2A / d.
It is performed under a current density of about m 2 . At this time, the plating bath used was 50 g / liter of copper sulfate and sulfuric acid each.
And the concentration of chlorine is 60 ppm, and the concentration of the additive is appropriately changed. Example in which copper bumps 221 and 222 are formed by applying a commercially available acidic copper plating additive (main component: dimercaptobenzothiazole and polyethylene glycol) used for plating through holes in a printed circuit board as an additive. Will be described. FIG. 3 shows the relationship between sulfur-containing organic substances (such as dimercaptobenzothiazole) in the plating bath and the concentration of sulfur co-deposited in the copper bump when such an additive is used. As the concentration of the sulfur-containing organic substance in the plating bath increases, the amount of sulfur eutectoid tends to increase.
When such an additive is used, if the concentration of the sulfur-containing organic substance in the plating bath is controlled to 0.5 vol% or less, it is possible to suppress a decrease in the durability of the electrode. Additives are managed by the user and are replenished in the plating bath at appropriate times according to their consumption. Generally, the concentration of the sulfur-containing organic substance in the plating bath tends to gradually increase with the passage of time as compared with the time of the initial building bath. Therefore, in order to maintain the sulfur-containing organic substance concentration in the plating bath at 0.5 vol% or less. In such a case, a predetermined plating bath may be renewed little by little in a specified cycle (for example, about 1 to 2 months) so that the concentration of the sulfur-containing organic substance is reduced. In this case, the sulfur concentration and the eutectoid sulfur concentration in the plating bath can be monitored by the hardness of the formed copper bump. The effect of the sulfur-containing organic substance added to the plating bath is that the sulfur in this additive is taken in as copper sulfide in the copper plating film, densifying the copper crystals and increasing the gloss of the film. To give. In a copper plating process for forming a copper bump as shown in the embodiment, such an effect of giving luster is not necessarily required. Therefore, from the above-mentioned commercially available additives that are added to a predetermined plating bath, only a polymer surfactant (such as polyethylene glycol) having an effect of removing the sulfur-containing organic substances and ensuring the uniformity of the plating film. May be applied as an additive. In this case, the eutectoid content of sulfur in the copper bumps is 10 ppm or less, and the decrease in electrode durability can be sufficiently suppressed. Further, since the organic sulfur component does not exist in the plating bath, it is not necessary to consider the fluctuation of the sulfur concentration in the plating bath, etc., so that the plating bath can be easily managed and the renewal cycle of the plating bath can be, for example, one year. You can do more than that. As described above, according to the method of manufacturing a semiconductor electrode according to the present invention, in the additive to the plating bath, the relationship between the sulfur-containing organic matter in the plating bath and the sulfur concentration in the copper bumps. By controlling so that the sulfur concentration is controlled to 50 ppm or less, the bonding strength between the copper bump and the solder layer is particularly ensured in the bump formed by the copper plating. In addition, sufficient durability can be ensured even in a high-temperature environment by ensuring the durability of the electrode.
【図面の簡単な説明】
【図１】この発明の一実施例に係る製造方法によって作
成された銅バンプを備えた半導体装置の電極構造を説明
する断面図。
【図２】銅バンプ中の硫黄濃度と電極耐久強度との関係
を示す図。
【図３】メッキ浴中の硫黄含有有機物濃度と銅バンプ中
の硫黄濃度との関係を示す図。
【図４】従来の半導体装置に設けられるバンプ電極を説
明する図。
【符号の説明】
21…半導体チップ、221 、222 …銅バンプ、231 、232
…はんだ、24…セラミック基板、251 、252 …回路導
体。BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a cross-sectional view illustrating an electrode structure of a semiconductor device having a copper bump formed by a manufacturing method according to an embodiment of the present invention. FIG. 2 is a diagram showing a relationship between a sulfur concentration in a copper bump and electrode durability. FIG. 3 is a diagram showing a relationship between the concentration of a sulfur-containing organic substance in a plating bath and the concentration of sulfur in a copper bump. FIG. 4 is a diagram illustrating a bump electrode provided in a conventional semiconductor device. [Description of References] 21: Semiconductor chip, 221, 222: Copper bump, 231, 232
... solder, 24 ... ceramic substrate, 251, 252 ... circuit conductors.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 伊藤 基樹 愛知県刈谷市昭和町１丁目１番地 日本 電装株式会社内 (72)発明者 兵藤 元昭 愛知県刈谷市昭和町１丁目１番地 日本 電装株式会社内 (56)参考文献 特開 平７−211722（ＪＰ，Ａ) 特開 昭54−60557（ＪＰ，Ａ) 特開 昭49−107933（ＪＰ，Ａ) 特開 昭61−41787（ＪＰ，Ａ) 特開 昭63−14886（ＪＰ，Ａ) 特開 平５−335314（ＪＰ，Ａ) (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 21/60 C25D 3/38 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Motoki Ito 1-1-1, Showa-cho, Kariya-shi, Aichi Japan Inside Denso Co., Ltd. (72) Inventor Motoaki Hyodo 1-1-1, Showa-cho, Kariya-shi, Aichi Japan Japan Denso Stock In-company (56) References JP-A-7-212722 (JP, A) JP-A-54-60557 (JP, A) JP-A-49-107933 (JP, A) JP-A-61-41787 (JP, A) JP-A-63-14886 (JP, A) JP-A-5-335314 (JP, A) (58) Fields investigated (Int. Cl. 7 , DB name) H01L 21/60 C25D 3/38
Claims (1)
極形成領域に対応して開口の形成されたパターンマスク
を介して電解メッキによって銅バンプを形成するバンプ
形成工程と、 このバンプ形成工程により形成された前記銅バンプの上
にはんだ層を形成する工程とを具備し、 前記バンプ形成工程にあっては、メッキ浴に含まれる不
純物である硫黄含有有機物の含有量によって、硫黄の濃
度が５０ｐｐｍ以下に制御され、 前記メッキ浴は硫酸銅および硫酸を含む硫酸銅浴によっ
て構成され、このメッキ浴に硫黄含有有機物および高分
子ポリマーが添加剤として添加されるもので、この添加
剤はその消費量に応じてメッキ浴中に適時補給され、前
記メッキ浴中の硫黄含有有機物の濃度は時間の経過と共
に徐々に上昇する傾向に管理され、この硫黄含有有機物
の濃度を前記５０ｐｐｍ以下に維持するため、周期的に
前記メッキ浴を少量づつ更新することを特徴とする半導
体電極の製造方法。(57) [Claim 1] A bump formation for forming a copper bump by electrolytic plating on a terminal lead-out surface of a semiconductor chip through a pattern mask having an opening corresponding to a bump electrode formation region. And a step of forming a solder layer on the copper bumps formed in the bump forming step. In the bump forming step, a sulfur-containing organic substance which is an impurity contained in a plating bath is contained. Depending on the amount, the sulfur concentration is controlled to 50 ppm or less, and the plating bath is constituted by a copper sulfate bath containing copper sulfate and sulfuric acid, and a sulfur-containing organic substance and a polymer are added to the plating bath as additives. , This addition
The agent is replenished in the plating bath in a timely manner according to its consumption.
The concentration of sulfur-containing organic matter in the plating bath increases with time.
This sulfur-containing organic matter is controlled to increase gradually
Periodically to maintain the concentration of
The method of manufacturing a semiconductor electrode, characterized that you portionwise update the plating bath.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14195494A JP3463353B2 (en) | 1994-06-23 | 1994-06-23 | Manufacturing method of semiconductor electrode |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14195494A JP3463353B2 (en) | 1994-06-23 | 1994-06-23 | Manufacturing method of semiconductor electrode |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH088259A JPH088259A (en) | 1996-01-12 |
| JP3463353B2 true JP3463353B2 (en) | 2003-11-05 |
Family
ID=15303998
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14195494A Expired - Fee Related JP3463353B2 (en) | 1994-06-23 | 1994-06-23 | Manufacturing method of semiconductor electrode |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3463353B2 (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4812429B2 (en) * | 2005-01-31 | 2011-11-09 | 三洋電機株式会社 | Circuit device manufacturing method |
| TWI445147B (en) | 2009-10-14 | 2014-07-11 | Advanced Semiconductor Eng | Semiconductor device |
| TW201113962A (en) | 2009-10-14 | 2011-04-16 | Advanced Semiconductor Eng | Chip having metal pillar structure |
| US8884443B2 (en) | 2012-07-05 | 2014-11-11 | Advanced Semiconductor Engineering, Inc. | Substrate for semiconductor package and process for manufacturing |
| US8686568B2 (en) | 2012-09-27 | 2014-04-01 | Advanced Semiconductor Engineering, Inc. | Semiconductor package substrates having layered circuit segments, and related methods |
-
1994
- 1994-06-23 JP JP14195494A patent/JP3463353B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH088259A (en) | 1996-01-12 |
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