JPH0879960A - Incorrect sampling detector for digital protective relay - Google Patents

Abstract

PURPOSE: To detect shift of sampling pulse interval which causes incorrect evaluation of AC input value and thereby erroneous function or malfunction in a digital protective relay where predetermined relay operation is performed by sampling analog input signals and then converting the sampled analog input signals digitally. CONSTITUTION: A CPU 5 counts the sampling signals using an incorporated clock circuit 2 according to software. Since no timer and the like is additionally employed, the input signal can be evaluated correctly thus realizing a digital protective relay where erroneous function and malfunction are eliminated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sampling failure detecting device capable of detecting a deviation of a sampling interval from a normal value in a digital protection relay.

[0002]

2. Description of the Related Art The structure of a general digital protection relay is shown in FIG. The digital protection relay 11 is provided with a sample and hold circuit 3 for sampling analog input values such as current and voltage at regular intervals. The sample and hold circuit 3 is provided with a sample clock circuit 8 for every 30 °, for example. A sampling pulse is provided. C
The PU 5 performs a predetermined relay calculation based on this sample value and outputs a signal to operate the auxiliary relay 9 when a predetermined condition is satisfied.

If the sampling pulse interval is exactly as planned, the relay operates correctly based on the sampled value, but if it deviates from the planned value,
The CPU 5 cannot accurately evaluate the AC input value, which causes malfunction or malfunction. Therefore, it is necessary to constantly monitor the sampling pulse interval and take measures such as immediately outputting an alarm command to the alarm device or locking the trip command to the circuit breaker if it deviates from the normal value. To monitor the above, it is possible to install a dedicated timer that can measure the sampling pulse interval. This timer measures the time from when a certain sampling pulse is received until when the next sampling pulse is received.

[0004]

However, in the above configuration, a dedicated timer is required, which complicates the configuration of the relay. Therefore, an object of the present invention is to solve the above-mentioned technical problems and to realize a sampling failure detection device that can easily obtain a sampling interval by using the existing equipment as much as possible.

[0005]

According to another aspect of the present invention, there is provided a sampling failure detecting device for counting a sampling signal at a constant time based on a time signal from a clock provided in a relay. Then, the deviation of the sampling interval is obtained from this result.

[0006]

According to the above-mentioned structure, it is possible to obtain the deviation of the sampling interval by counting the sampling signals at a fixed time by software by using the clock provided as a standard in the relay.

[0007]

Embodiments will be described in detail below with reference to the accompanying drawings showing embodiments. FIG. 1 shows an internal block diagram of a digital protection relay 1 incorporating a sampling failure detection device.
The digital protection relay 1 includes a filter circuit 10 for passing a fundamental wave component of an analog input such as current and voltage, a sample clock circuit 8 for sending a sampling signal, a sample hold circuit 3, and an A / D conversion circuit for digitally converting an analog signal. 4, a CPU 5 for performing a predetermined relay calculation, an output circuit 6 attached to the CPU 5, a memory circuit 7, a timepiece 2, and an auxiliary relay 9.

In the present embodiment, the sample clock circuit 8 sends out sampling signals at intervals of 30 ° (1.38 msec for 60 Hz), and the sample hold circuit 3
Performs sampling based on the sampling signal from the sample clock circuit 8. The CPU 5 counts how many times sampling is performed in one second according to the flowchart (FIG. 2). That is, based on the time signal received from the clock 2, the counting is started at 00 seconds per minute and stopped at 01 seconds. Then, it is determined whether the counted number is within a certain range (step (4)
). Since this fixed range is 720 times in the case of normal sampling, it is set to, for example, 719-721. Therefore, it can be understood that it is not normal if it is out of the fixed range and only counted, for example, 718 times, the sampling is 30.08 °, and there is a shift of 0.08 °.

If it is determined that the sampling is defective (step (5)), the CPU 5 issues an alarm command or locks the trip command to the circuit breaker. With the above processing, it is possible to determine whether the sampling interval is normal by using the time signal from the clock 2 and to start a predetermined operation thereafter.

It should be noted that the present invention is not limited to the above-mentioned embodiment, for example, instead of counting at 00 seconds to 01 seconds per minute, other time (for example, 58 seconds to 59 minutes per minute).
Seconds) may be counted. The counting time is not limited to 1 second, and may be 10 seconds, for example. The longer the counting time, the more accurately the sampling interval can be detected. Further, it goes without saying that the sample clock may be set at other angles than 30 °. Other various modifications can be made without changing the gist of the present invention.

[0011]

As described above, according to the sampling failure detection apparatus of the present invention, it is possible to detect the deviation of the sampling interval by software using the existing equipment.
As a result, the input signal can be correctly evaluated, and a digital protection relay without malfunction or malfunction can be realized.

[Brief description of drawings]

FIG. 1 is an internal block diagram of a digital protection relay incorporating a sampling failure detection device.

FIG. 2 is a flowchart showing a software process in which sampling signals are counted for a certain period of time based on a time signal from a clock and a sampling interval shift is obtained from the result.

FIG. 3 is a block diagram showing a configuration of a general digital protection relay.

[Explanation of symbols]

 1 Digital protection relay 2 Watch 3 Sample and hold circuit 4 A / D conversion circuit 5 CPU 8 Sample clock circuit

Claims (1)

[Claims] 1. A sampling means for sampling an analog input signal, a digital converting means for digitally converting a sampling output value, an arithmetic means for performing a predetermined relay operation based on an output signal of the digital converting means, and a time signal output. In the digital protection relay having a clock, the calculating means counts the sampling signal at a constant time based on the time signal from the clock, and obtains the deviation from the normal value of the sampling interval based on this result. A sampling failure detection device characterized by the above.