JPH0879026A - Comparator circuit - Google Patents

Abstract

PURPOSE: To realize the comparator circuit from which a normal comparison result is provided as an output at a high speed clock frequency. CONSTITUTION: The comparator circuit is provided with an input voltage comparator section 1 including resistors R1 , R2 and NPN transistors(TRs) Q1 , Q2 whose bases receive analog input voltages V11 , V12 respectively and whose emitters are connected in common, a positive feedback latch section 2 including NPN TRs Q3 , Q4 , a current switch 3 including NPN TRs Q5 , Q6 whose collectors connect to the common emitters of the NPN TRs Q1 , Q2 , Q3 , Q4 , whose gates receive respectively a noninverting clock signal ϕ11 and an inverting clock signal ϕ12 and whose emitters are connected in common, a constant current source 4, and a switch 5 connected between the collectors of the NPN TRs Q1 , Q2 .

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a comparison circuit, and more particularly to a comparison circuit used in a high speed A / D converter or the like.

[0002]

2. Description of the Related Art Conventionally, an example of this type of comparison circuit is shown in FIG. As shown in FIG. 8, in this conventional example, the resistance R
₁ , R ₂ and a collector are connected to a power supply terminal V _cc through resistors R ₁ and R ₂ , respectively, and analog input voltages V _i1 and V _i2 are input to the base, respectively, and an emitter is commonly connected. and NPN transistors Q _1, Q ₂ Metropolitan input voltage comparing unit 1 consists of being a collector connected to the collector of NPN transistor Q _2, Q _1, respectively, base to the collector of NPN transistor Q _1, Q _2, respectively A positive feedback latch unit 2 composed of NPN transistors Q ₃ and Q ₄ which are connected and whose emitters are commonly connected, and a common emitter of NPN transistors Q ₁ and Q ₂ and collectors of NPN transistors Q ₃ and Q _{4, respectively.} Of the positive-phase clock signal φ connected to the common emitter of
₁₁ and the negative-phase clock signal φ ₁₂ are input, and the current switch 3 is composed of NPN transistors Q ₅ and Q ₆ whose emitters are commonly connected, and one end is connected to the common emitter of the NPN transistors Q ₅ and Q _6. And a constant current source 4 whose other end is grounded.

Further, FIGS. 2 (a), 2 (b), 2 (c),
(D) and (e) are output waveform diagrams of an embodiment of the present invention described later and a conventional comparison circuit, and FIGS. (C) and (d) are analog input voltages V _i1 and V _i2 , respectively. The positive phase clock signal φ ₁₁ and the negative phase clock signal φ ₁₂ are shown, and FIG. 6B shows the output waveforms of the output voltages V _o1 and V _i2 in this conventional example. Hereinafter, FIG. 8, FIG.
The operation of the conventional example will be described with reference to (c) and (d).

In FIG. 8, whether the positive phase clock signal φ ₁₁ input to the base of the NPN transistor Q ₅ becomes high level or low level (the negative phase clock signal φ input to the base of the NPN transistor Q ₆ ). Depending on whether ₁₁ becomes a low level or a high level), the current of the constant current source 4 flows to either one of the input voltage comparison section 1 and the positive feedback latch section 2 via the current switch 3. When the positive-phase clock signal φ ₁₁ goes high (the negative-phase clock signal φ ₁₁ goes low) is called follow mode, and the negative-phase clock signal φ ₁₁ goes high (the positive-phase clock signal φ ₁₁ goes low). When this happens, it is called the latch mode. Usually, like the conventional comparison circuit shown in FIG. 8, a comparison circuit having an input voltage comparison unit 1 and a positive feedback latch unit 2 has a difference voltage | V _i1 −V between two analog input voltages V _i1 and V _i2. It is often used when _i2 | is a minute voltage. Therefore, in the following, the difference voltage | V _i1 between the analog input voltages V _i1 and V _i2
A case where −V _i2 | is a minute voltage will be described. A case where the clock frequency is low will be described.

As shown in the output waveform of FIG. 2 (b),
In the follow mode (see FIG. 2 (d)), the analog input voltages V _i1 and V _i2 (see FIG. 2 (c)) are compared in the input voltage comparison unit 1 in terms of voltage level, and both analogs are compared. The minute difference voltage of the input voltage is amplified and output. Then, in the latch mode (see FIG. 2 (d)), the output voltage amplified in the follow mode is shown in FIG. 2 (b) by the positive feedback latch unit 2 which is positively fed back. Then, it is amplified again up to the voltage level below.

When V _i1 > V _i2 , V _o1 = V _H (V _o2 = V _L ) ... (1) When V _i1 <V _i2 , V _o1 = V _L (V _o2 = V _{o H} ) ... (2) It is said that the comparison circuit outputs a normal comparison result when the magnitude relationships of the expressions (1) and (2) are satisfied.

Next, the comparator circuit is set to follow mode (see FIG. 2).
2D), the output voltages V _o1 and V _o2 once have the same voltage level after a certain time, as shown in FIG. 2B, and then the two analog input voltages V _i1. , V _i2 are compared, and the minute input difference voltage is amplified by the input voltage comparison unit 1. As shown in FIGS. 2D and 2B, the comparison circuit switches from the latch mode to the follow mode until the two output voltages V _o1 and V _o2 become the same potential as described above. The time is called the recovery time T _r2 . In the conventional comparison circuit shown in FIG. 8, the recovery time T _r2 is determined by the current value of the constant current source 4, the load capacitance of the output terminal, and the like. When the load capacitance is large, the recovery time becomes long.

[0008]

In the conventional comparison circuit described above, when the clock frequency is high, it takes a long recovery time when the comparison circuit switches from the latch mode to the follow mode. Since the two output voltages V _o1 and V _o2 have the same potential and the input difference voltages are latched without being compared, there is a possibility that an erroneous comparison result may be output. .

[0009]

In the comparison circuit of the present invention, the first electrode is connected to the first power source through the first and second resistors, respectively, and the second and first outputs are provided, respectively. The first and second semiconductor elements connected to the terminal, the second electrodes connected to the first and second analog input terminals, and the third electrode commonly connected, and the first electrode, respectively. The first electrode of the first semiconductor element is connected to the first power source through second and first resistors, and is connected to the second and first output terminals, respectively, and the second electrode is connected to the first semiconductor element of the first semiconductor element.
An electrode, connected to the first electrode of the second semiconductor element,
Third and fourth semiconductor elements having a third electrode commonly connected,
Between the first electrode of the first semiconductor element and the first electrode of the second semiconductor element, the first electrode is inserted and connected between the first electrode of the second semiconductor element and the first electrode of the second semiconductor element. Switch means for controlling conduction / interruption of the first electrode and the first electrode,
Each of the first and second semiconductor elements is connected to a commonly connected third electrode, and each of the third and fourth semiconductor elements is commonly connected to a third electrode. Fifth and sixth semiconductor elements connected to a second clock signal terminal and commonly connected to a third electrode, and the fifth and sixth semiconductor elements.
The sixth semiconductor element is configured to include a commonly connected third electrode and a constant current source connected between the second power source and the second power source.

The first, second, third, fourth and fifth
The sixth semiconductor element may be formed by an NPN transistor having a collector as a first electrode, a base as a second electrode, and an emitter as a third electrode,
Alternatively, an NMOS having a drain as a first electrode, a gate as a second electrode, and a source as a third electrode, respectively.
It may be formed by a transistor.

In the switching means, the gates are connected to the third and fourth clock signal terminals, the drains are commonly connected to the second output terminal, and the sources are common to the first output terminal. It may be formed by a transfer gate including a PMOS transistor and an NMOS transistor connected to each other, or the gate is connected to the third clock signal terminal, the drain is connected to the second output terminal, and the source is connected to the second output terminal. It may be formed by a PMOS transistor connected to the first output terminal, and further has a gate connected to the third clock signal terminal, a drain connected to the second output terminal, and a source connected to the first output terminal. It may be formed by an NMOS transistor connected to the output terminal of 1.

[0012]

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention. As shown in FIG. 1, in this embodiment, the collector is connected to the power supply terminal V _cc via resistors R ₁ and R ₂ , respectively.
Connected to the analog input voltage V _i1 , respectively to the base,
The input voltage comparison unit 1 including NPN transistors Q ₁ and Q ₂ to which V _i2 is input and whose emitters are commonly connected and the resistors R ₁ and R ₂ and collectors of the NPN transistors Q ₂ and Q ₁ respectively An NPN transistor Q having a base connected to the collectors of the NPN transistors Q ₁ and Q ₂ and common emitters
Positive feedback latch unit 2 including ₃ and Q ₄ , collectors are common emitters of NPN transistors Q ₁ and Q ₂ , NP, respectively.
Connected to the common emitters of N-transistors Q ₃ and Q ₄ ,
The positive phase clock signal φ ₁₁ and the negative phase clock signal φ ₁₂ are input to the gates, and the emitters are commonly connected.
A current switch 3 including N transistors Q ₅ and Q ₆ , a constant current source 4 having one end connected to the common emitter of the NPN transistors Q ₅ and Q ₆ and the other end grounded, and a switch 5. It

2 (a), (b), (c),
(D) and (e) are output waveform diagrams in the present embodiment and the above-described conventional comparison circuit, and FIGS.
_Are the analog input voltages V _i1 in the present embodiment,
V _i2 and the positive-phase clock signal φ ₁₁ and the negative-phase clock signal φ ₁₂ are shown. FIG. _6A shows the output waveforms of the output voltages V _o1 and V _i2 in the present embodiment. ) Is a switch control signal φ for the switch 5 in this embodiment.
₂ is shown. The switch control signal φ ₂ is
It is input as a pulse signal synchronized with the positive-phase clock signal φ ₁₁ , but the high-level time width of the pulse signal is set to a value shorter than the high-level time width of the positive-phase clock signal φ _11. , And is input to the switch 5 to set the switch 5 to the conductive state at the time of high level. Less than,
The operation of this embodiment will be described with reference to FIGS. 1, 2A, 2C, 2D and 2E.

In FIG. 1, as in the case of the conventional example, N
Whether the positive phase clock signal φ ₁₁ input to the base of the PN transistor Q ₅ becomes high level or low level (NP
Depending on whether the negative-phase clock signal φ ₁₁ input to the base of the N-transistor Q ₆ becomes low level or high level), the input voltage comparison unit 1 and the positive feedback latch unit 2 are connected via the current switch 3. A current flows to the constant current source 4 in either one of the above. Normally, a comparison circuit having the input voltage comparison unit 1 and the positive feedback latch unit 2 is often used when the difference voltage | V _i1 −V _i2 | between the two analog input voltages V _i1 and V _i2 is a minute voltage. Therefore, as in the case of the above-mentioned conventional example, in the following, the difference voltage | V _i1 − between the analog input voltages V _i1 and V _{i2 will be described.}
A case where V _i2 | is a minute voltage will be described.

As shown in the waveforms of the output voltages V _o1 and V _o2 in FIG. 2A, when the switch control signal φ ₂ is at a low level, the switch 5 is in the cutoff state, which is the case of the conventional example. Similar to the case, in the follow mode (see FIG. 2D), the analog input voltages V _i1 and V _i2 (see FIG.
In (c), the input voltage comparison unit 1 compares the voltage levels and the minute difference voltage between both analog input voltages is amplified and output. Then, in the latch mode (see FIG. 2D), the output voltages V _o1 and V _o2 amplified in the follow mode are fed back by the positive feedback latch unit 2 which is positively fed back, as shown in FIG. ), The voltage levels V _H and V _L shown in the equations (1) and (2) are amplified again and output.

Next, when the next follow mode from the latch mode is entered, the switch control signal φ _{2 in} synchronization with the positive phase clock signal φ ₁₁ becomes high level immediately after the comparator circuit enters the follow mode, As a result, the switch 5 is turned on, and the two output voltages V _o1 and V _o2 corresponding to the input voltages V _i1 and V _i2 are forced to have substantially the same potential (FIGS. 2A, 2C and 2C). See d) and (e)).
The recovery time in this case is T _r1 as shown in FIG. The recovery time T _r2 in the above-described conventional comparison circuit is substantially determined by the current value of the constant current source 4, the load capacity of the output terminal, and the like. When the load capacity is large, there is a problem that the recovery time becomes long. ,
On the other hand, in this embodiment, the switch means is provided between the output terminals to forcefully output the two output voltages V _o1 and V _o2.
The recovery time is drastically shortened by pulling in the same potential (T _r1 <T _r2 ). As a result, FIG.
As shown in (a) and (b), in the conventional comparison circuit, when the clock frequencies of the positive phase clock signal φ ₁₁ and the negative phase clock signal φ ₁₂ are high,
In the mode, the state shifts to the latch mode while the input voltage cannot be compared, and a normal comparison result can be output as a comparison circuit like the equations (1) and (2). There is a fear of not being able to do it.
However, in the comparison circuit of the present invention, by shortening the recovery time as described above, a normal comparison can be performed even for the positive-phase clock signal φ ₁₁ and the negative-phase clock signal φ ₁₂ having a higher clock frequency than the conventional one. The result can be output.

3 (a), 3 (b), 3 (c), 3 (d) and 3 (e) show the present embodiment when the comparison circuit is operated at a timing different from the output waveform chart shown in FIG. It is an output waveform diagram in an example and the above-mentioned conventional comparison circuit. The difference from FIG. 2 is that the switch control signal φ ₂ is a positive phase clock signal φ ₁₁
Is a waveform that is synchronized with and has the same high level and low level states. The output waveform in FIG. 3B is the output waveform itself in the above-mentioned conventional example and is the same waveform as in FIG. 2B. As shown in FIGS. 3 (c), 3 (d) and 3 (e), the switch control signal φ ₂ is always at the high level in the follow mode in response to the input voltages V _i1 and V _i2. The switch 5 becomes conductive, and in the latch mode, it is always at a low level, and the switch 5 is in a cutoff state. In the follow mode, the switch 5 is turned on and
A current flows into the constant current source 4 via the input voltage comparison unit 1 so that the two output voltages V _o1 and V _o2 have substantially the same potential, but due to the ON resistance of the switch 5, a slight difference occurs. A voltage is generated, and its magnitude relation corresponds to the input voltages V _i1 and V _i2 . In the subsequent latch mode, the switch 5 is cut off, and a current flows into the constant current source 4 via the positive feedback latch unit 2, whereby two output voltages V _{o1 with} a slight difference voltage, V _o2 is V _H due to positive feedback NPN transistors Q ₃ and Q _4.
Alternatively, it is amplified to a voltage level of V _L. Then, when the comparison circuit enters the follow mode, the switch 5 is turned on, and the two output voltages V _o1 and V _o2 are forcibly brought to the same potential and output. Recovery time T in this case
_r1 can be significantly shortened as compared with the conventional comparison circuit, similarly to the output waveform shown in FIG.
As a result, even for the positive-phase clock signal φ ₁₁ and the negative-phase clock signal φ ₁₂ having a higher clock frequency than the conventional one,
A normal comparison result can be output.

FIG. 4 is a circuit diagram showing a second embodiment of the present invention. As shown in FIG. 4, in the present embodiment, the drains are connected to the power supply terminal V _cc via the resistors R ₁ and R ₂ , respectively, and the gates are respectively analog input voltages V _i1 and V _i1 .
_The input voltage comparator 1 including the NMOS transistors M ₁ and M ₂ and the resistors R ₁ and R ₂ to which _i2 is input and whose sources are commonly connected, and the drains thereof are connected to the drains of the NMOS transistors M ₂ and M ₁ , respectively. The positive feedback latch unit 2 including the NMOS transistors M ₃ and M ₄ whose gates are connected to the drains of the NMOS transistors M ₁ and M _{2 and} whose sources are commonly connected, and the drains of the NMOS transistors M ₁ and M 2, respectively. ₂ is connected to the common source and the common sources of the NMOS transistors M ₃ and M ₄ , and the positive-phase clock signal φ ₁₁ and the negative-phase clock signal φ ₁₂ are input to the gates, respectively, and the sources are commonly connected to the NMOS transistor M ₅ , a current switch 3 including M _6, one end connected to a common source of the NMOS transistor M _5, M _6, the other end A constant current source 4 connected to a point, and a switch 5 which is connected between the collector of the NMOS transistors M _1, M _2. The operation of the second embodiment is similar to that of the first embodiment described above, and the description of the operation is omitted because it is redundant.

Further, FIGS. 5, 6 and 7 are circuit diagrams showing third, fourth and fifth embodiments of the present invention, respectively. In the third embodiment shown in FIG. 5, the switch 5 in Figure 1, the switch control signal phi ₂₁ to the gate,
φ ₂₂ is applied, the drain is connected to the collector of the NPN transistor Q ₁ , and the source is connected to the collector of the NPN transistor Q _2. The transfer gate TG is formed by an NMOS transistor and a PMOS transistor. . The switch control signal φ ₂₂ in this case is an inverted signal of the switch control signal φ ₂₁ . In the fourth embodiment shown in FIG. 6, the switch 5 in FIG. 1 has a gate to which the switch control signal φ ₂₁ is applied, a drain connected to the collector of the NPN transistor Q ₁ , and a source connected to the NPN transistor Q _2. Of the NMOS transistor MN ₁ connected to the collector of the. In addition, in the fifth embodiment shown in FIG. 7, the switch 5 in FIG.
However, the switch control signal φ ₂₂ is applied to the gate, and the drain is connected to the collector of the NPN transistor Q ₁ ,
The source is constituted by a PMOS transistor MP ₁ connected to the collector of the NPN transistor Q ₂ .
The operation of the third, fourth and fifth embodiments is similar to the basic operation of the first embodiment described above, and the description thereof is omitted because it is redundant.

[0021]

As described above, according to the present invention, the switching means is provided between the two output terminals so that the normal comparison result can always be output even when the clock signal of the high speed clock frequency is input. effective.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

FIG. 2 is an output waveform diagram in the embodiment and the conventional example.

FIG. 3 is an output waveform diagram in the embodiment and the conventional example.

FIG. 4 is a circuit diagram showing a second embodiment of the present invention.

FIG. 5 is a circuit diagram showing a third embodiment of the present invention.

FIG. 6 is a circuit diagram showing a fourth embodiment of the present invention.

FIG. 7 is a circuit diagram showing a fifth embodiment of the present invention.

FIG. 8 is a circuit diagram showing a conventional example.

[Explanation of symbols]

1 Input voltage comparison unit 2 Positive feedback latch unit 3 Current switch 4 Constant current source 5 Switch R ₁ , R ₂ Resistance Q ₁ , Q ₂ , Q ₃ , Q ₄ , Q ₅ , Q ₆ NPN transistor M ₁ , M ₂ , M ₃ , M ₄ , M ₅ , M ₆ , MN ₁ NM
OS transistor TG Transfer gate MP ₁ PMOS transistor

Claims (6)

[Claims] 1. A first electrode is connected to a first power supply via first and second resistors, respectively, and is connected to second and first output terminals, respectively, and a second electrode is The first and second semiconductor elements connected to the first and second analog input terminals and commonly connected to the third electrode, and the first electrode are respectively connected via the second and first resistors. The first electrode of the first semiconductor element and the first electrode of the second semiconductor element are connected to the first power source and the second and first output terminals, respectively, and the second electrodes are respectively connected to the first electrode and the first electrode of the first semiconductor element. Between the third and fourth semiconductor elements connected to the electrodes and commonly connected to the third electrode, the first electrode of the first semiconductor element and the first electrode of the second semiconductor element Between the first electrodes of the first and second semiconductor elements, which are inserted and connected, and by a predetermined switch control signal. A switch means for controlling conduction / interruption, a first electrode, a third electrode commonly connected to the first and second semiconductor elements, and a third electrode commonly connected to the third and fourth semiconductor elements, respectively. Fifth and sixth semiconductor elements connected to three electrodes, second electrodes connected to first and second clock signal terminals, respectively, and third electrodes commonly connected, and the fifth and sixth semiconductor elements. 3. A comparison circuit comprising: a third electrode, which is commonly connected to the semiconductor elements, and a constant current source connected between a second power source. 2. An NPN transistor in which each of the first, second, third, fourth, fifth and sixth semiconductor elements has a collector as a first electrode, a base as a second electrode, and an emitter as a third electrode. The comparison circuit according to claim 1, which is formed by: 3. An NMOS transistor in which each of the first, second, third, fourth, fifth and sixth semiconductor elements has a drain as a first electrode, a gate as a second electrode, and a source as a third electrode. The comparison circuit according to claim 1, which is formed by: 4. The switch means has a gate connected to the third and fourth clock signal terminals, a drain commonly connected to the second output terminal, and a source common to the first output terminal. 4. A comparison circuit according to claim 2, formed by a transfer gate including a PMOS transistor and an NMOS transistor connected to each other. 5. The switching means comprises a PMOS transistor having a gate connected to a third clock signal terminal, a drain connected to the second output terminal, and a source connected to the first output terminal. Claim 2 formed
And the comparison circuit described in 3. 6. The switch means comprises an NMOS transistor having a gate connected to a third clock signal terminal, a drain connected to the second output terminal, and a source connected to the first output terminal. Claim 2 formed
And the comparison circuit described in 3.