JPH0878542A - Nonvolatile semiconductor device - Google Patents

Abstract

PURPOSE: To lower the bias being applied at the time of writing/erasing information by providing a cell array arranged with a plurality of memory cells which can rewrite electric information and forming an irregular part, corresponding to the memory cell region, on the semiconductor substrate. CONSTITUTION: Source 12 and drain 13 are formed in a p-type well 11 and a gate insulation film, i.e., tunnel oxide 14, is deposited thereon and then a floating gate 15, is formed thereon. Subsequently, a control gate 17 is formed on the floating gate 15 through an insulation film 16 thus producing a cell array arranged with a plurality of memory cells which can rewrite information electrically. An irregular recess 18 is made in the memory cell region, i.e., the source region 12. Since the bias being applied at the time of writing/erasing the information can be lowered, the rate for writing/erasing the information can be increased.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a non-volatile semiconductor device.

[0002]

2. Description of the Related Art In a nonvolatile semiconductor device in which information can be electrically rewritten, an FN (Fowler-Nordheim) tunnel current passing through a gate insulating film when writing and / or erasing information in a floating gate is performed. The electron is used for taking in and out. FIG. 22 shows an example of a conventional non-volatile semiconductor device using LOCOS element isolation, and FIG. 22 (A) is a sectional view in the word line direction.
FIG. 22B is a cross-sectional view in the bit line direction. The memory cell of this nonvolatile semiconductor device is manufactured as follows.

Well 1 is formed on a silicon substrate which is a semiconductor substrate.
Then, a buffer oxide film is formed thereon. A polysilicon film and a silicon nitride film are sequentially formed thereon. After that, patterning is performed with a resist, and the silicon nitride film in the region for element isolation is etched.
Then, it is oxidized to form LOCOS2. Then, the buffer oxide film is removed by etching to form a gate insulating film 3 which is a so-called tunnel oxide film. Since these gate insulating films follow the surface shape of the substrate, the surface is usually flat. Next, a polysilicon film 4 to be a floating gate is formed on the gate insulating film 3, and ONO (Oxid
After forming an insulating film 5 such as an e-Nitride-Oxide) laminated film, a polysilicon film 6 to be a control gate is formed thereon. Further, wiring is formed by a conventional method.

On the other hand, FIG. 23 shows an example of a conventional non-volatile semiconductor device using trench isolation.
23A is a cross-sectional view in the word line direction.
FIG. 6B is a sectional view in the bit line direction. The memory cell of this nonvolatile semiconductor device is manufactured as follows.

A well 7 is formed on a silicon substrate which is a semiconductor substrate.
Then, a buffer oxide film is formed thereon. A polysilicon film and a CVD oxide film are sequentially formed on it. After that, patterning is performed with a resist, and the trenches are formed by etching the CVD oxide film, the polysilicon film, the buffer oxide film, and the silicon substrate in the regions to be element isolation. Then, as a filling material in this trench, for example, LP-TEOS (Low Pressure Tetra) is used.
-Ethyl-Oxide-Silicon) 8 is embedded. Then CMP
The entire surface is planarized by the (Chemical Mechanical Polishing) method or the etch back method, and the polysilicon film on the gate is removed to complete the element isolation. Then, the buffer oxide film is removed to form the gate insulating film 2. Then L
As in the case of OCOS, the floating gate 4, the insulating film 5,
And the control gate 6 is formed. Since the edge 9 of the SDG (source / drain / gate) at this time is covered with the oxide film and is not exposed, the surface of the gate insulating film 3 formed on the SDG follows the surface shape of the oxide film. It becomes flat.

In the conventional nonvolatile semiconductor device shown in FIGS. 22 and 23, the surface of the gate insulating film which is a tunnel oxide film is generally a flat surface or a curved surface having a curvature close to a flat surface. Therefore, when a bias is applied for writing / erasing information, the electric field distribution in the channel region of the transistor forming the memory cell becomes substantially uniform throughout. Moreover, since the gate insulating film is a flat plane, the electric field distribution in the thickness direction in the gate insulating film is also uniform. Specifically, in the case of the LOCOS element separation type shown in FIG. 22, the electric field distribution is as shown in FIG.
In the case of the trench element separation type shown in FIG. 23, the electric field distribution is as shown in FIG.

[0007]

In the above non-volatile semiconductor device, the value of the voltage applied to the control gate or well at the time of writing / erasing information is determined by the capacitance between the control gate and the floating gate. If the values are the same,
That is, the shape of the memory cell (including the type, thickness, or cross-sectional area of the insulating film between the control gate and the floating gate)
Are uniquely determined by the thickness of the tunnel oxide film. Therefore, by reducing the thickness of the tunnel oxide film, the voltage required for writing / erasing information can be lowered.

In recent years, in order to reduce the power consumption of a non-volatile semiconductor device, it is required to lower the voltage for writing / erasing information, but there is a limit to thinning the tunnel oxide film. For example, a very thin oxide film cannot be stably formed by the current oxidation method, and there is a possibility that the film thickness will vary greatly, or even if it can be formed, the breakdown voltage will decrease. Further, the stress leak value that determines the reliability of the nonvolatile semiconductor device also increases as the oxide film becomes thinner, and the reliability of the device, particularly the read retention characteristic, tends to deteriorate. Specifically, as shown in FIG. 25, as the thickness Tox of the tunnel oxide film becomes thinner,
Read Disturb Time, which shows the read retention characteristic, becomes low.

The present invention has been made in view of the above point, and the bias applied at the time of writing / erasing information can be suppressed to a low level without making the thickness of the tunnel oxide film thinner than before. An object of the present invention is to provide a non-volatile semiconductor device capable of increasing the speed of writing / erasing information.

[0010]

According to the present invention, a semiconductor substrate, a gate insulating film formed on the semiconductor substrate, a floating gate formed on the gate insulating film, and an insulating film on the floating gate are provided. And a control gate formed via a memory cell array, and comprising a cell array in which a plurality of electrically rewritable memory cells are arranged.
There is provided a nonvolatile semiconductor device, wherein at least a part of the semiconductor substrate corresponding to the memory cell region has an uneven shape.

Further, according to the present invention, a semiconductor substrate, a gate insulating film formed on the semiconductor substrate, a floating gate formed on the gate insulating film, and an insulating film formed on the floating gate via an insulating film. And a control gate that is electrically connected to each other, and includes a cell array in which a plurality of electrically rewritable memory cells are arranged. According to a bias direction applied when writing and erasing information, The direction of a tunnel current passing through the gate insulating film changes bidirectionally, at least a part of the semiconductor substrate corresponding to the memory cell region has an uneven shape, and the tunnel current has an electric field concentrated therein. Provided is a non-volatile semiconductor device which is characterized in that it passes through the region.

[0012]

The non-volatile semiconductor device of the present invention is characterized in that at least a part of the semiconductor substrate corresponding to the memory cell region has an uneven shape. Therefore, the tunnel oxide film formed on the semiconductor substrate is formed so as to follow the uneven shape, and the surface is not flat but has the uneven shape.

When a voltage is applied at the time of writing / erasing information, an electric field concentrates on the curved surface or the corner of the tunnel oxide film. Therefore, the apparent strength of the electric field increases at the curved surface or the corner. Therefore, even if the tunnel oxide film has the same thickness as the conventional one, it is possible to write / erase information at a lower voltage, and to write / erase information.
The erasing speed can be increased.

Further, according to the nonvolatile semiconductor device of the present invention, the direction of the tunnel current passing through the gate insulating film is bidirectional depending on the bias direction applied at the time of writing and erasing information such as NAND type. Even in a device that changes to a high speed, since the tunnel current passes through the region where the electric field is concentrated in both directions, it is possible to write / erase information at a lower voltage faster in both the information writing state and the erasing state. it can.

[0015]

Embodiments of the present invention will be specifically described below with reference to the drawings. (Embodiment 1) FIG. 1 shows a nonvolatile semiconductor device according to a first embodiment of the present invention.
It is sectional drawing which shows the Example of. In the figure, 11 indicates a p-type well. A source 12 and a drain 13 are formed in the p-type well 11. On top of this, a thickness of 60-150
An angstrom tunnel oxide film 14 is formed. The silicon substrate which is the semiconductor substrate is the source 12
A recess 18 that is an uneven portion is formed in the area of. Therefore, the tunnel oxide film 14 is formed so as to follow the depression 18. This recess 18 is, as shown in FIG.
It may be formed continuously in a linear shape, or may be formed in a bowl shape as shown in FIG. 2 (B). Further, the depression 18 may extend not only to the source 12 region but also to the channel region and the drain region 13. Further, a floating gate 15 made of polysilicon is formed on the tunnel oxide film 14. A control gate 17 made of polysilicon is formed on the floating gate 15 via an ONO laminated film 16. Although this embodiment shows a single memory cell structure, this memory cell is generally a part of a NOR type cell array. An example of the cell array structure is shown in FIG.

The manufacturing process of this memory cell will be described below. First, as shown in FIG. 4A, after forming a necessary well 11 in a silicon substrate, a buffer oxide film is formed thereon. A polysilicon film and a silicon nitride film are sequentially formed thereon. After that, patterning is performed with a resist, and the silicon nitride film in the region for element isolation is etched. Then oxidize this to LOC
The OS 19 is formed. Next, as shown in FIG. 4B, after removing the buffer oxide film by etching, the resist 20 is patterned and left in a region other than the region where the depression 18 is formed. Next, isotropic etching is applied to this to form a recess 18 as shown in FIG. Then, after removing the resist 20, tunnel oxidation is performed to form a tunnel oxide film 14, and a polysilicon film is formed thereon to form a floating gate 15 as shown in FIG. After that, an insulating film made of an ONO laminated film and a control gate are formed on the floating gate 15.

Next, writing / writing of information in this memory cell
The erasing method will be described. First, in writing information, electrons are injected into the floating gate 15 by hot carrier injection. The bias conditions at this time are, for example, 12V for the control gate 17, 0V for the source 12, and 5V for the drain 13. The electrons emitted from the source 12 are
It is accelerated in the channel portion and injected into the floating gate 15 at the strongest electric field near the drain 13. In this case, the shape of the tunnel oxide film 14 does not have a function of changing the voltage or speed applied during writing. That is, the characteristics are equivalent to those of a flat tunnel oxide film.

In erasing information, electrons are injected from the floating gate 15 into the silicon substrate by the FN tunnel current. The bias condition at this time is, for example, the control gate 1
7 to -12V, source 12 to 5V, drain 13 to 0V
Is. In this case, if the tunnel oxide film 14 of the source 12 is convex toward the silicon substrate, the electric field distribution in this portion will not be uniform. Electric field distributions in the tunnel oxide film 14 at this time and corresponding energy band diagrams are shown in FIGS. 5 (A) and 5 (B), respectively. For comparison, the electric field distribution and the corresponding band diagram when the shape of the tunnel oxide film 14 is uniformly flat are shown in FIGS. 6A and 6B, respectively.

As can be seen from FIG. 6, in the uniformly flat tunnel oxide film, the strengths of the electric fields on the floating gate 15 'side and the silicon substrate side are the same, and the value of the electric field strength depends on the applied voltage. It is equal to the value Ea.v divided by the film thickness of 14 '. On the other hand, the tunnel oxide film 1 in the present embodiment
In Example 4, since the electric field lines on the floating gate 15 side have a high density, the electric field on the floating gate 15 side becomes stronger than the electric field on the silicon substrate side, and the band bends and an acute angle portion 14a appears as shown in FIG. 5 (A). . The strength of the electric field in this part is Eaverag
It becomes larger than e (hereinafter abbreviated as Ea.v). Thus, even if the same voltage is applied to both sides of the tunnel oxide film 14, the apparent electric field becomes larger in the tunnel oxide film as in this embodiment shown in FIG. 5, resulting in a large FN.
Tunnel current will flow. That is, when passing the same value of FN tunnel current through the tunnel oxide film,
By using the tunnel oxide film having the depression 18 having the curved surface as in this embodiment, the voltage for erasing information can be lowered. (Embodiment 2) FIG. 7 shows a nonvolatile semiconductor device according to the second embodiment of the present invention.
It is sectional drawing which shows the Example of. In the first embodiment, the depression 18 is formed in the source region of the memory cell. Example 1
The reason is that electrons are extracted to the source when erasing information, and the electric field on the floating gate side in this region needs to be strengthened. On the other hand, when electrons are extracted into the silicon substrate when erasing information, it is effective to concentrate the electric field in the region that will be the channel. In this embodiment, the depression 21 is formed in the channel region. This recess 21 is shown in FIG.
As shown in (A), it may be continuously formed in a linear shape, or as shown in FIG. 8 (B), it may be formed in a bowl shape. Although the present embodiment shows a single memory cell structure, this memory cell is generally a part of a NOR type cell array. The method of manufacturing this memory cell is basically the same as that of the first embodiment, and is different only in the resist pattern when forming the depression 21.

Next, a method of writing / erasing information in this memory cell will be described. First, in writing information, electrons are injected into the floating gate 15 by hot carrier injection. The bias conditions at this time are, for example, 12 V for the control gate 17, 0 V for the source 12, and the drain 1
3 to 5V. The electrons emitted from the source 12 are accelerated in the channel portion and injected into the floating gate 15 at the strongest electric field near the drain 13. in this case,
It has almost the same characteristics as a flat tunnel oxide film.

In erasing information, electrons are injected from the floating gate 15 into the silicon substrate by the FN tunnel current. The bias condition at this time is, for example, the control gate 1
7 is 0V, source 12 and drain 13 are floating, and well 11 is -20V. In this case, the electrons in the floating gate 15 are FN tunneled at the strongest electric field and injected into the well 11. The state of the electric field distribution at this time is shown in FIG. Also in this case, compared with the case of a flat tunnel oxide film, the FN tunnel current starts to flow from the low voltage side, and as a result, the applied voltage at the time of erasing information can be lowered. (Embodiment 3) In Embodiments 1 and 2, a NOR type non-volatile semiconductor device in which hot electrons are used for writing information and an FN tunnel current is used for erasing information has been described, but this embodiment writes information. A NAND type non-volatile semiconductor device that uses an FN tunnel current for both erasing and erasing will be described. Also in this case, the voltage at the time of writing / erasing information can be lowered by utilizing the electric field concentration effect of the tunnel oxide film having the uneven shape.

FIG. 10 is a sectional view showing a third embodiment of the non-volatile semiconductor device of the present invention, and FIG. 11 is a plan view thereof. Each memory cell has a trench 32 (Shallow Trench Isolation) on the p-type well 31 for element isolation.
n) are formed, and SDG regions 33 are formed on the stripes in the direction parallel to the bit line direction. Also,
The source and drain are also formed. A filling material 34 such as STI (Shallow Trench Isolation) is filled in the trench 32, and plays a role as a region for element isolation. This embedding material 34 is used in the SDG area 3
It is filled up to a position slightly lower than the height of 3, so that a corner portion 35 is formed in the SDG region 33. A tunnel oxide film 36 is formed thereon so as to follow the uneven shape. A floating gate 37 made of polysilicon is formed on the tunnel oxide film 36. A control gate 39 made of polysilicon is formed on the floating gate 37 via an ONO laminated film 38.
In this embodiment, a single memory cell structure is shown.
Generally, this memory cell is a part of a NAND type cell array. An example of the cell array structure is shown in FIG.

The manufacturing process of this memory cell will be described below. First, as shown in FIG. 13A, after forming a necessary well 31 in a silicon substrate, a buffer oxide film 41 is formed thereon. Polysilicon film 42 is formed thereon
Then, the CVD oxide film 43 is sequentially formed. Then, FIG.
As shown in FIG. 3B, patterning is performed with a resist 44, and the trench 32 is formed by etching the CVD oxide film 43, the polysilicon film 42, the buffer oxide film 41, and the silicon substrate in the regions for element isolation. Then, for example, LP-TEOS is filled in the trench 32 as a filling material 34. Then, FIG. 13 (C)
As shown in, the entire surface is planarized by the CMP method or the etch back method, and the polysilicon on the gate is removed to complete the element isolation. Then, the buffer oxide film 41 is removed and a gate insulating film is formed thereon. That is, after forming the oxide film of the select gate, the region to be the tunnel oxide film is patterned using a resist, and the oxide film in that region is removed.

At this time, the relationship between the height of the SDG region 33 and the height of the embedding material 34 is as shown in FIG.
The height of the filling material 34 is slightly lower than the height of the SDG region 33, and a corner portion 35 is formed in the SDG region. In this state, the tunnel oxide film 36 is formed to have a desired thickness. Then, a floating gate 37 made of polysilicon, an ONO laminated film 38, and a control gate 39 made of polysilicon are sequentially formed on the tunnel oxide film.

Next, writing / writing of information in this memory cell
The erasing method will be described. In this type of memory cell, both writing and erasing of information are performed by the FN tunnel current in the tunnel oxide film. The bias conditions for writing information are, for example, 18 V for the control gate, 0 V for the source, drain, and the substrate. At this time, electrons are injected into the floating gate 37 from the well (silicon substrate), but electric field concentration occurs at the corners 35 of the SDG region 33, and the electric field on the silicon substrate side is strengthened, and as a result, the SDG region 33 The FN tunnel current of the same value can flow at a voltage lower than that in the flat portion. The distribution and band diagram of the lines of electric force at this time are shown in FIG. 14 (A) and FIG. 1, respectively.
4 (B).

On the other hand, in the case of erasing information, the SDG area 33
In the corner portion 35, the electric field is weaker than the electric field strength Ea.v of the flat tunnel oxide film. Therefore, in the case of erasing information, the FN tunnel current does not pass through the corner portion 35 but through the flat portion in the center of the SDG region 33.

In the present embodiment, the electric field is concentrated at the corners 35 at both ends of the SDG area 33.
As shown in FIG. 15, one end of the SDG region 33 may be covered with a thick oxide film 40, and the electric field may be concentrated at the other corner 35. The fabrication of this memory cell is basically the same as that of the present embodiment, but it is necessary to increase the resist patterning step in order to change the height of the filling material 34 at the end portions on both sides of the SDG region 33. (Embodiment 4) The non-volatile semiconductor device of the third embodiment has a configuration capable of reducing only the voltage when writing information, but the non-volatile semiconductor device of the present embodiment also lowers the voltage when erasing information. This is a possible configuration.

FIG. 16 is a sectional view showing a fourth embodiment of the non-volatile semiconductor device of the present invention, and FIG. 17 is a plan view thereof. Although a single memory cell structure is shown in this embodiment, this memory cell is generally a part of a NAND cell array. Each memory cell is p
A trench 52 (Shallo
w Trench Isolation) is formed, and SDG regions 53 are formed on the stripes in the direction parallel to the bit line direction. Further, a source and a drain are also formed.
A filling material 54 such as STI is filled in the trench 52 and plays a role as an element isolation region. The embedding material 54 is filled up to a position slightly lower than the height of the SDG region 53, whereby a corner portion 55 is formed in the SDG region 53. In addition, the SDG area 53
A depression 56 similar to the depression 18 formed in the source 12 of the first embodiment is formed in the central portion of the. The tunnel oxide film 5 is formed so as to cover the corner portion 55 and the depression 56.
7 are formed. A floating gate 58 made of polysilicon is formed on the tunnel oxide film 57.
A control gate 60 made of polysilicon is formed on the floating gate 58 via an ONO laminated film 59.

The manufacturing process of this memory cell will be described below. First, as shown in FIG. 18A, after forming a necessary well 51 in a silicon substrate, a buffer oxide film 61 is formed thereon. Polysilicon film 6 on it
2 and the CVD oxide film 63 are sequentially formed. Next, as shown in FIG. 18B, patterning is performed with a resist 64 to form a CVD oxide film 63 in a region for element isolation,
A trench 52 is formed by etching the polysilicon film 62, the buffer oxide film 61, and the silicon substrate.
Then, the trench 52 is filled with, for example, LP-TEOS as a filling material 54. Then, FIG.
As shown in (C), the entire surface is planarized by the CMP method or the etchback method, and the polysilicon on the gate is removed to complete the element isolation. Next, the buffer oxide film 41 is removed, and patterning is performed so that the resist 64 is left in a region other than the region where the depression 56 is formed, and FIG.
As shown in (D), a recess 56 is formed in the SDG region 53 by isotropic etching. Next, a gate insulating film is formed on this. That is, after forming the oxide film of the select gate, the region to be the tunnel oxide film is patterned using a resist, and the oxide film in that region is removed.

At this time, the relationship between the height of the SDG region 53 and the height of the embedding material 54 is that the height of the embedding material 54 is slightly lower than the height of the SDG area 53 as shown in FIG. A corner portion 55 is formed at. In this state, the tunnel oxide film 57 is formed to have a desired thickness. Then, a floating gate 58 made of polysilicon, an ONO laminated film 59, and a control gate 60 made of polysilicon are sequentially formed on the tunnel oxide film.

Next, writing / writing of information in this memory cell
The erasing method will be described. In this type of memory cell, both writing and erasing of information are performed by the FN tunnel current in the tunnel oxide film. The bias conditions for writing information are, for example, 18 V for the control gate, 0 V for the source, drain, and the substrate. At this time, electrons are injected from the well (silicon substrate) into the floating gate 58, but electric field concentration occurs at the corner portion 55 of the SDG region 53, and the electric field on the silicon substrate side is strengthened, and as a result, the SDG region 53 The FN tunnel current of the same value can be passed at a voltage lower than that in the central portion.

On the other hand, in the case of erasing information, the SDG area 53
At the corner 55, the electric field strength E of the flat tunnel oxide film is
Conversely, the electric field becomes weaker than av. Therefore, in the case of erasing information, the FN tunnel current is SD instead of the corner 55.
It passes through the central portion of the G region 53, that is, the depression 56. At this time, the electrons are injected from the floating gate 58 into the silicon substrate, but in the depression 56, the electric field is concentrated so that the floating gate 58 is filled.
The side electric field is strengthened, and as a result, the FN tunnel current can flow at a voltage lower than that of the flat tunnel oxide film.

As described above, according to the non-volatile semiconductor device of the present embodiment, the required voltage can be lowered in both writing and erasing of information. (Embodiment 5) In this embodiment, a NAND type non-volatile semiconductor device using LOCOS element isolation will be described.

FIG. 19 is a sectional view showing a fourth embodiment of the non-volatile semiconductor device of the present invention, and FIG. 20 is a plan view thereof. Note that FIG. 19A is a cross-sectional view in the word line direction and FIG. 19B is a cross-sectional view in the bit line direction.

Although this embodiment shows a single memory cell structure, this memory cell is generally a part of a NAND cell array. In the figure, 71 indicates a p-type well. In the p-type well 71, LO is formed as an element isolation region.
COS 72 is formed. A large depression is formed in the channel region of the p-type well 71, and a plurality of small depressions 78 are formed in the large depression at substantially equal positions. That is, a recess having an uneven shape is formed. The size of the small depression 78 is about one fifth to one tenth of that of the large depression.

A tunnel oxide film 73 is formed on this channel region. A floating gate 74 made of polysilicon is formed on the tunnel oxide film 73.
A control gate 76 made of polysilicon is formed on the floating gate 74 via an ONO laminated film 75.

The manufacturing process of this memory cell will be described below. First, as shown in FIG. 21A, after forming a necessary well 71 in a silicon substrate, a buffer oxide film is formed thereon. A polysilicon film and a silicon nitride film are sequentially formed thereon. After that, patterning is performed with a resist, and the silicon nitride film in the region for element isolation is etched. Then, oxidize this to LO
COS 72 is formed. Next, as shown in FIG. 21B, after removing the buffer oxide film by etching,
The resist 79 is left in the region other than the region where the large depression is formed by patterning. Then, FIG.
As shown in FIG. 1 (C), this is isotropically etched to form a large depression, and patterning is performed using a resist, and etching is performed to form a plurality of small depressions 78. Next, after removing the resist 79, tunnel oxidation is performed to form a tunnel oxide film 73, and as shown in FIG. 21D, a polysilicon film is formed thereon to form a floating gate 74. After that, an insulating film made of an ONO laminated film and a control gate are formed on the floating gate 74.

Next, writing / writing of information in this memory cell
The erasing method will be described. In this type of memory cell, both writing and erasing of information are performed by the FN tunnel current in the tunnel oxide film. The bias conditions for writing information are, for example, 18 V for the control gate, 0 V for the source, drain, and the substrate. At this time, electrons are injected from the well (silicon substrate) into the floating gate 74, but at this time, the electric field concentrates on the small protrusions between the small depressions 78. The electric field in this portion becomes larger than the electric field Ea.v of the flat tunnel oxide film having the same film thickness, and the FN tunnel current flows in this small protruding portion.

On the other hand, the bias condition for erasing information is, for example, 0V for the control gate and 20V for the substrate. At this time, the electrons are discharged from the floating gate to the well, but at this time, the electric field is concentrated near the small recess 78. The electric field in this portion becomes larger than the electric field Ea.v of the flat tunnel oxide film having the same film thickness, and the FN tunnel current flows into this small recess 78.

As described above, in this embodiment, the required voltage is lower than the voltage required in the case of the flat tunnel oxide film having the same film thickness in both the writing of information and the erasing of information. can do. Further, the voltage value in that case can be adjusted by changing the curvature of the large depressions and the arrangement and number of the small depressions.

[0041]

As described above, in the non-volatile semiconductor device of the present invention, at least a part of the semiconductor substrate corresponding to the memory cell region has an uneven shape, so that a voltage is applied at the time of writing / erasing information. At times, the electric field is concentrated due to the uneven shape, which makes it possible to suppress the bias applied when writing / erasing information, without making the thickness of the tunnel oxide film thinner than before. The writing / erasing speed can be increased.

[Brief description of drawings]

FIG. 1 is a sectional view showing a first embodiment of a non-volatile semiconductor device of the present invention.

2A and 2B are plan views of the nonvolatile semiconductor device shown in FIG.

FIG. 3 is a plan view showing a cell array structure of the nonvolatile semiconductor device shown in FIG.

4A to 4D are cross-sectional views illustrating a manufacturing process of the nonvolatile semiconductor device shown in FIG.

5A is a diagram showing an electric field distribution in a tunnel oxide film of the nonvolatile semiconductor device shown in FIG. 1, and FIG. 5B is a band diagram corresponding to FIG.

6A is a diagram showing an electric field distribution in a tunnel oxide film of a conventional nonvolatile semiconductor device, and FIG. 6B is a band diagram corresponding to FIG.

FIG. 7 is a sectional view showing a second embodiment of the non-volatile semiconductor device of the present invention.

8A and 8B are plan views of the nonvolatile semiconductor device shown in FIG.

9 is a diagram showing an electric field distribution in a tunnel oxide film of the nonvolatile semiconductor device shown in FIG.

FIG. 10 is a cross-sectional view showing a third embodiment of the non-volatile semiconductor device of the present invention.

11 is a plan view showing the nonvolatile semiconductor device shown in FIG.

12 is a plan view showing a cell array structure of the non-volatile semiconductor device shown in FIG.

13A to 13D are cross-sectional views illustrating a manufacturing process of the nonvolatile semiconductor device shown in FIG.

14A is a diagram showing an electric field distribution in a tunnel oxide film of the nonvolatile semiconductor device shown in FIG. 10, and FIG. 14B is a diagram showing FIG.
Band diagram corresponding to.

15 is a cross-sectional view showing another aspect of the nonvolatile semiconductor device shown in FIG.

FIG. 16 is a sectional view showing a nonvolatile semiconductor device according to a fourth embodiment of the present invention.

FIG. 17 is a plan view showing the nonvolatile semiconductor device shown in FIG.

18A to 18D are cross-sectional views illustrating a manufacturing process of the nonvolatile semiconductor device shown in FIG.

19A and 19B are cross-sectional views showing a fourth embodiment of the non-volatile semiconductor device of the present invention.

20 is a plan view showing the nonvolatile semiconductor device shown in FIG.

21A to 21D are cross-sectional views illustrating a manufacturing process of the nonvolatile semiconductor device shown in FIG.

22A and 22B are cross-sectional views showing a conventional nonvolatile semiconductor device, where FIG. 22A is a cross-sectional view in the word line direction and FIG. 22B is a cross-sectional view in the bit line direction.

23A and 23B are cross-sectional views showing a conventional nonvolatile semiconductor device, where FIG. 23A is a cross-sectional view in the word line direction and FIG. 23B is a cross-sectional view in the bit line direction.

24A and 24B are diagrams showing directions of lines of electric force in a conventional nonvolatile semiconductor device.

FIG. 25 is a graph showing the relationship between the film thickness of the tunnel oxide film and the read retention characteristics.

[Explanation of symbols]

11, 31, 51, 71 ... P-type well, 12 ... Source,
13 ... Drain, 14, 36, 57, 73 ... Tunnel oxide film, 15, 37, 58, 74 ... Floating gate, 16, 3
8, 59, 75 ... ONO laminated film, 17, 39, 60, 7
6 ... Control gate, 18, 21, 56 ... Dimple, 19, 72
... LOCOS, 20, 44, 64, 79 ... Resist, 3
2, 52 ... Trench, 33, 53 ... SDG region, 34,
54 ... Buried material, 35, 55 ... Corners, 40 ... Thick oxide film, 41, 61 ... Buffer oxide film, 42, 62 ... Polysilicon film, 43, 63 ... CVD oxide film, 78 ... Small depression.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location H01L 27/115

Claims (2)

[Claims] 1. A semiconductor substrate, a gate insulating film formed on the semiconductor substrate, a floating gate formed on the gate insulating film, and a control gate formed on the floating gate via an insulating film. And a memory cell array in which a plurality of electrically rewritable memory cells are arranged, and at least a part of the semiconductor substrate corresponding to the memory cell region has an uneven shape. A non-volatile semiconductor device characterized in that. 2. A semiconductor substrate, a gate insulating film formed on the semiconductor substrate, a floating gate formed on the gate insulating film, and a control gate formed on the floating gate via an insulating film. And a gate array film comprising: a cell array in which a plurality of electrically rewritable memory cells are arrayed, the gate insulating film depending on a bias direction applied when writing and erasing information. Direction of the tunnel current passing through the semiconductor substrate changes bidirectionally, at least a part of the semiconductor substrate corresponding to the memory cell region has an uneven shape, and the tunnel current passes through a region of the semiconductor substrate where an electric field is concentrated. A non-volatile semiconductor device comprising: