JPH0878537A - Static semiconductor memory - Google Patents

Abstract

PURPOSE: To attain a sufficiently high cell ratio required for reading out the data stably by varying the work function at the gate electrode of an MOS transistor thereby making the threshold voltage variable and increasing the area of transistor. CONSTITUTION: Drive transistors Q11 , Q12 have n-type gate electrodes G11 , G12 whereas transfer transistors Q15 , Q16 have P-type gate electrodes G15 , G16 . Consequently, the gate drive voltage of the drive transistor Q11 , Q12 can be set higher than that of the transfer transistor. Since-the ON resistance per unit channel width is substantially proportional inversely to the gate drive voltage, the cell ratio is doubled when the gate drive voltage of the drive transistor Q11 , Q12 is set two times as high as that of the transfer transistor Q15 , Q16 . Consequently, the cell ratio can be quadruplicated when both the channel width and the gate drive voltage are doubled.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a static semiconductor memory device (hereinafter referred to as SRAM).

[0002]

2. Description of the Related Art A conventional SRAM memory cell (SRAM
The configuration and operation of a cell will be described by taking a CMOS SRAM as an example.

FIG. 3 shows a circuit diagram of a CMOS type SRAM cell. The drive transistors Q ₁₁ and Q ₁₂ formed of n-channel MOS transistors and the load transistors Q ₁₃ and Q ₁₄ formed of p-channel MOS transistors are respectively (Q
₁₁ and Q ₁₃ and Q ₁₂ and Q ₁₄ ) are connected in series to form two inverters. Load transistor Q ₁₃ ,
The source terminal of Q ₁₄ is connected to the power supply voltage V _DD , and the source terminals of the driving transistors Q ₁₁ and Q ₁₂ are connected to the ground potential V _SS .

The interconnection point of the two transistors forming each inverter is connected to the gate terminals of the two transistors forming the other inverter, and the transfer transistors Q ₁₅ and Q ₁₆ formed of n-channel MOS transistors are connected. It is connected to the bit lines BL ₁ and BL ₂ via. The gate terminals of the transfer transistors Q ₁₅ and Q ₁₆ are both connected to the word line WL.

The data stored in the memory cell shown in FIG.
When reading the data, a high level signal is applied to the word line WL.
To give two transfer transistors Q₁₅, Q₁₆On state
To Drive transistor Q₁₁, Q₁₂Of the drain terminal
The potential state of each transfer transistor Q₁₅, Q₁₆Through
Bit line BL₁, BL₂Appear in. Bit line B
L ₁, BL₂The potential states appearing in the
Input to the inverting and non-inverting input terminals of a differential amplifier,
It is amplified and taken out.

Normally, the transfer transistor Q₁₅, Q₁₆On
The resistance of the state is the drive transistor Q ₁₁, Q₁₂Than that
Is also designed to be large. Transfer transistor
Q₁₅, Q ₁₆If the on-state resistance of the
When taking out, drive transistor Q ₁₁, Q₁₂The drain edge
Bits whose child potentials were precharged before the read operation started
Data that fluctuates and is stored under the influence of the line potential
May be destroyed.

The ratio of the on-state resistance of the transfer transistor to the on-state resistance of the drive transistor is called the cell ratio. The cell ratio is usually set to about 3 or more.

[0008]

Generally, in order to increase the cell ratio, the channel width of the driving transistor is made larger than that of the transfer transistor. If the channel width of the driving transistor is increased, the cell ratio increases and the read operation becomes stable, but the area occupied by the transistor increases, which goes against the demand for higher integration.

On the other hand, although the channel width of the transfer transistor may be made small, a certain width is required to function as a MOS transistor, and it is difficult to make it smaller than that width.

Although the cell ratio can be increased even if the channel length of the transfer transistor is increased, it is against the demand for high integration as in the case of increasing the channel width of the driving transistor.

An object of the present invention is to provide an SRAM cell capable of obtaining a sufficiently large cell ratio for stable data reading without increasing the area of the transistor.

[0012]

A static type semiconductor memory device of the present invention includes a parallel connection circuit in which two sets of a drive transistor and a load are connected in series, and a drive transistor and a load in each series connection are mutually connected. In a static semiconductor memory device having wirings connecting connection points to control terminals of drive transistors of different sets, and transfer transistors connected to the interconnection points, the drive transistor and the transfer transistor may be a first transistor. When the first conductivity type is an n-type, the work function of the gate electrode of the transfer transistor is larger than the work function of the gate electrode of the drive transistor, and the first conductivity type is p-type. In the mold, the work function of the gate electrode of the transfer transistor is related to the work function of the gate electrode of the driving transistor. Less than.

The gate electrode of the drive transistor may be the first conductivity type silicon, and the gate electrode of the transfer transistor may be the second conductivity type silicon opposite to the first conductivity type.

[0014]

The threshold voltage can be changed by changing the work function of the gate electrode of the MOS transistor. Driving transistor and transfer transistor are nMO
In the case of an S transistor, the threshold voltage of the transfer transistor can be made higher than that of the driving transistor by making the work function of the gate electrode of the transfer transistor larger than the work function of the gate electrode of the driving transistor. it can. Conversely, when the drive transistor and the transfer transistor are pMOS transistors, the work function of the gate electrode of the transfer transistor is made smaller than the work function of the gate electrode of the drive transistor, so that the threshold voltage of the transfer transistor changes. It can be greater than the threshold voltage.

As the threshold voltage increases, the on-state resistance also increases. Therefore, the cell ratio can be increased without changing the channel size.

[0016]

EXAMPLE FIG. 1A shows a plan view of an SRAM cell in which the circuit of the SRAM cell shown in FIG. 3 is formed on a silicon substrate. The configuration and operation of the SRAM cell circuit shown in FIG. 3 have already been described. Figure 1 (B)
Shows a cross-sectional view taken along the alternate long and short dash line BB in FIG.

As shown in FIG. 1B, a silicon substrate 1
Active region surrounded by field oxide film 2 on the surface of
A₁, A₂Is defined. As shown in Figure 1 (A)
And the gate electrode G₁₃, Source region S₁₃, Drain region D
₁₃Load transistor Q consisting of₁₃, And the gate electrode
G₁₄, Source region S₁₄, Drain region D₁₄Consisting of a load
Transistor Q₁₄Is the active area A₁Is formed in.

The gate electrode G _11, the source region S _11, the driving transistor Q ₁₁ consisting of the drain region D _11, the gate electrode G _12, the source region S _12, the driving transistor Q ₁₂ consisting of the drain region D _12, the gate electrode G _15, Source region S ₁₅ ,
Transfer transistor Q ₁₅ consists drain region D ₁₅ and the gate electrode G _16,, the source region S _16, the transfer transistors Q ₁₆ consisting of the drain region D ₁₆ are formed in the active region A _2.

Source region S₁₃And S₁₄Is integrally formed
Contact hole H₁₉Through the first layer wiring L₁₉Contact
1st layer wiring L₁₉Is the power supply formed on the second layer
Pressure line V _DDIt is connected to the. Source area S₁₁And S₁₂Is
Contact hole H formed integrally₂₀Through the first layer
Wiring L₂₀Connected to the first layer wiring L₂₀Is not shown in the figure
Connected to the ground line extending in the lateral direction of the figure formed on the second layer
Has been done.

The gate electrodes G ₁₁ and G ₁₂ have a film thickness of 200 nm.
Of the amorphous silicon layer. The gate electrodes G ₁₁ and G ₁₃ , and G ₁₂ and G ₁₄ are connected to each other on the field oxide film 2 as shown in FIG.

The gate electrodes G ₁₁ and G ₁₂ are n-type, and the gate electrodes G ₁₃ and G ₁₄ are p-type. For this reason, pn junctions are formed at the connection interfaces between the gate electrodes, but since the surfaces of these gate electrodes are covered with an alloy (silicide) layer of a refractory metal and silicon, the gate electrodes G ₁₁ and G
₁₃ , and G ₁₂ and G ₁₄ are ohmic connected.

The gate electrodes G ₁₅ and G ₁₆ are connected to each other and extend in the lateral direction of the drawing to form a word line WL.
The drain region D ₁₁ and the source region S ₁₅ , and the drain region D ₁₂ and the source region S ₁₆ are integrally formed.

Drain regions D ₁₁ and D ₁₃ and gate electrode G ₁₄
(And G ₁₂ ) are contact holes H ₁₁ ,
It is connected to the wiring L ₁ via H ₁₃ and H ₁₈ . Similarly, the drain regions D ₁₂ , D ₁₄ and the gate electrode G ₁₁ (and G
₁₃ ) is connected to the wiring L ₂ via contact holes H ₁₂ , H ₁₄ and H ₁₇ , respectively.

The drain regions D ₁₅ and D ₁₆ are provided with first-layer wirings L ₁₅ and L ₁₆ via contact holes H ₁₅ and H ₁₆ , respectively.
The first layer wirings L ₁₅ and L ₁₆ are connected to bit lines BL ₁ and BL ₂ (FIG. 3) formed in the third layer (not shown) and extending in the vertical direction. There is.

Next, the SRAM shown in FIGS. 1A and 1B
A method for manufacturing the cell will be described. p-type silicon substrate 1
A surface oxide film 2 having a thickness of 250 nm is formed by selective oxidation on the surface of ₁ to define active regions A ₁ and A ₂ . p
P ⁺ ions for forming an n-type well are ion-implanted into the active region A ₁ forming the MOS transistor. Then, nM
B ⁺ ions for forming a p-type well are ion-implanted into the active region A ₂ forming the OS transistor.

A thickness of 6 n is formed on the surface of the silicon substrate in the active region.
m gate oxide film is formed, and a 200 nm-thick amorphous silicon layer is further deposited on the gate oxide film by CVD. Next, in the amorphous silicon layer, the gate electrodes G ₁₁ and G
P ⁺ ions for forming an n-type gate electrode are ion-implanted into the region where ₁₂ is formed under the conditions of ²⁰ keV and 4 × 10 ¹⁵ cm ^-2 . Then, p is formed in the region where the gate electrodes G _{13 to} G ₁₆ are formed.
Type BF ₂ ⁺ ions for forming a gate electrode, 20 keV, 4
Ion implantation is performed under the condition of × 10 ¹⁵ cm ^-2 . Amorphous silicon is patterned by photolithography and etching to form gate electrodes G _{11 to} G ₁₆ .

Next, the resist pattern and the gate electrode are formed.
As a mask, in the area where the nMOS transistor is formed
As⁺Ion 20 keV, 2 × 10¹⁵cm^-2Under the conditions
Ion implantation. Similarly, resist pattern and gate
PMOS transistor is formed using the electrode as a mask
BF in the area₂ ⁺Ion 20 keV, 2 × 10¹⁵cm ^-2
Ion implantation is performed under the conditions of.

After ion implantation, heat treatment is performed at 1000 ° C. for 10 seconds by the rapid thermal annealing method (RTA method). At this time, the implanted ions are activated and the gate electrode becomes p-type or n-type,
Source and drain regions of the transistor are formed.

Next, a 100 nm thick silicon oxide film is deposited on the entire surface by CVD. RIE this silicon oxide film
Is anisotropically etched to form a sidewall on the sidewall of the gate electrode.

By sputtering, a C layer having a thickness of 10 nm is formed on the entire surface.
Deposit the o layer. 30 seconds at about 600 ° C using RTA method
Heat treatment is performed for about a period of time. At this time, the gate electrode, the source
And C in the region where the Co layer is in contact with the surface of the drain region
o and Si react, CoSi ₂A layer is formed. CoS
i₂After the layer formation, the unreacted Co layer is treated with hydrogen peroxide solution and sulfuric acid.
Remove with mixture.

PS with a thickness of 300 nm is formed on the entire surface by CVD.
A G (phosphosilicate glass) interlayer insulating film is deposited. This
Contact hole H in the silicon oxide film of₁₁~ H₁₄, H₁₇
~ H ₁₉Open the power supply voltage line V_DD, Wiring L₁, L₂Shape
To achieve.

Further, an interlayer insulating film is deposited, contact holes H ₁₅ and H ₁₆ are opened, and bit lines are formed. Further, an interlayer insulating film is deposited and a contact hole H ₂₀ is opened to form a ground line.

Hereinafter, with reference to FIG.
The operation of the transfer transistor will be described. Explanation in Figure 1
Drive transistor Q₁₁, Q₁₂Gate of
Pole G ₁₁, G₁₂Is n-type, transfer transistor Q₁₅, Q₁₆Ge of
Electrode G₁₅, G₁₆Is p-type.

FIGS. 2A and 2B show the energy band structure of the MOS structure when the gate electrodes of the driving transistor and the transfer transistor and the p-type substrate have the same potential, respectively. 2C and 2D show the case where a voltage of 2.5 V is applied to the gate electrodes of the driving transistor and the transfer transistor, respectively. Since the gate electrode is amorphous silicon, unlike the case of a single crystal, the valence band,
The boundaries between the forbidden band and the conduction band are not clear, but the boundaries are described as clear.

As shown in FIG. 2A, the Fermi level E _F is almost equal to the conduction band lower end E _C because the n-type gate electrode G ₁₁ is heavily doped with P. Also, FIG.
As shown in (B), since a large amount of B is doped in the p-type gate electrode G ₁₅ , the Fermi level E _F is almost equal to the valence band upper end E _V.

Therefore, the vacuum level E ₀ and the Fermi level E _F
The work function qφ _a, which is the difference from the p-type gate electrode G ₁₅ , is larger than the n-type gate electrode G ₁₁ by a voltage (1 V) corresponding to the band gap of silicon. Further, since the gate electrode and the p-type substrate have the same potential, the Fermi levels of both are equal.

As shown in FIG. 2A, the gate electrode is n
In the case of the mold, the energy band bends downward near the interface of the p-type substrate 1. On the other hand, when the gate electrode is p-type, as shown in FIG. 2B, the energy band bends slightly upward near the interface of the p-type substrate 1.

When the gate electrode is p-type, the same downward bending of the energy band as in the case of the n-type gate electrode is generated, and the p-type gate electrode has a work function difference of about n. It is necessary to apply a voltage of 1V. Therefore, the threshold voltage V _TH of the MOSFET in the case of the p-type gate electrode is about 1 V higher than that in the case of the n-type gate electrode.

FIG. 2E shows the drain current characteristic with respect to the gate voltage. Curves a ₁ and a ₂ represent the drain currents of the driving transistor and the transfer transistor, respectively. As described above, the threshold voltage V _TH2 of the transfer transistor having the p-type gate electrode is higher than the threshold voltage V _TH1 of the driving transistor having the n-type gate electrode by about 1 V. Under the conditions described with reference to FIG. 1, the threshold voltages V _TH1 and V _TH2 are about 0.5 V and 1.5 V, respectively.

When a voltage higher than the threshold voltage V _TH is applied to the gate electrode, a drain current flows as shown in FIG. 2 (E). The drain current increases almost linearly as the gate voltage increases in the range where the gate voltage is lower than a certain voltage. Curve a ₂ in the figure around the curve a ₁ in the horizontal axis direction 1
V is almost equal to the translated one. As described above, the gate drive voltage V _DRV used to actually drive the drain current among the gate voltage V _GS is V _DRV = V _GS −V _TH .

When a voltage of 2.5 V is applied to the gate electrode, the energy band structure bends largely downward near the interface of the p-type substrate 1 as shown in FIGS. 2 (C) and 2 (D). The gate drive voltage at this time is 2.0 V for the drive transistor and 1.0 V for the transfer transistor.
Therefore, the bending amount of the band is larger in the n-type gate electrode than in the p-type gate electrode. At this time, the drain currents of the driving transistor and the transfer transistor are I _D1 and I _D2 , respectively, as shown in FIG.

As in the above embodiment, the gate electrode of the driving transistor is n-type and the gate electrode of the transfer transistor is p-type.
By adopting a mold, the gate drive voltage of the drive transistor can be made higher than the gate drive voltage of the transfer transistor. Since the on-state resistance per unit channel width is almost inversely proportional to the gate drive voltage,
If the gate drive voltage of the drive transistor is set to be twice the gate drive voltage of the transfer transistor, the cell ratio will be approximately doubled even if the channel sizes are the same.

When the channel width of the drive transistor is set to be twice the channel width of the transfer transistor, the cell ratio is doubled if the threshold voltages are equal. Therefore, by making the channel width of the drive transistor twice the channel width of the transfer transistor and the gate drive voltage of the drive transistor twice the gate drive voltage of the transfer transistor, the cell ratio can be quadrupled. .

In the above embodiment, the case where p-type amorphous silicon is used to increase the work function of the gate electrode of the transfer transistor has been described, but other materials can be used as long as they are larger than the work function of n-type amorphous silicon. Materials may be used. For example, aluminum, titanium, titanium nitride or the like may be used.

In the above embodiment, the case where the nMOS transistor is used for both the drive transistor and the transfer transistor has been described, but a pMOS transistor may be used. In this case, the work function of the gate electrode of the transfer transistor may be made smaller than the work function of the gate electrode of the drive transistor.

Conventionally, an n-type gate electrode has been used for both the nMOS transistor and the pMOS transistor. In this case, in order to make the threshold voltage of the pMOS transistor equal to that of the nMOS transistor, the channel region of the pMOS transistor is a weak p type. Therefore, the p-type region is formed from the surface of the channel region to a slightly deep region, and punch-through due to the short channel effect is likely to occur.

According to the above embodiment, since the gate electrode of the pMOS transistor is p-type, it is not necessary to dope the channel region of the pMOS transistor to p-type.
There is also an effect that punch-through due to the short channel effect hardly occurs.

Although the threshold voltage can be changed by changing the impurity concentration of the channel region, the number of steps is smaller than that of the method of changing the impurity concentration of the channel region according to the method of the above embodiment. There are also advantages.

The present invention has been described above with reference to the embodiments.
The present invention is not limited to these. For example, it will be apparent to those skilled in the art that various modifications, improvements, combinations, and the like can be made.

[0050]

As described above, according to the present invention,
SR without increasing the area occupied by the transistor
The cell ratio of AM cells can be increased. Therefore, a more stable read operation becomes possible.

[Brief description of drawings]

FIG. 1 is a plan view and a cross-sectional view of an SRAM cell according to an embodiment.

2 is an energy band diagram of a MOS structure of a drive transistor and a transfer transistor shown in FIG. 1 and a graph showing a drain current characteristic with respect to a gate voltage.

FIG. 3 is a circuit diagram of a CMOS type SRAM cell.

[Explanation of symbols]

 1 Silicon substrate 2 Field oxide film 3 Interlayer insulating film A Active region Q MOS transistor G Gate electrode S Source region D Drain region H Contact hole L Wiring BL Bit line WL Word line

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical display location H01L 27/06 29/786 9056-4M H01L 29/78 613 B

Claims (2)

[Claims] 1. A drive transistor and a load are connected in series to each other.
Pairs of parallel connection circuits connected in parallel, wiring connecting the interconnection points of the drive transistors and loads in each series connection to the control terminals of the drive transistors of other pairs, and the transfer connected to each interconnection point In a static semiconductor memory device having a transistor, the drive transistor and the transfer transistor have a first
When the first conductivity type is an n-type, the work function of the gate electrode of the transfer transistor is larger than the work function of the gate electrode of the drive transistor, and the first conductivity type is p-type. In the static type, the work function of the gate electrode of the transfer transistor is smaller than the work function of the gate electrode of the drive transistor in a static type semiconductor memory device. 2. The static type according to claim 1, wherein the gate electrode of the drive transistor is the first conductivity type silicon, and the gate electrode of the transfer transistor is the second conductivity type silicon opposite to the first conductivity type. Semiconductor memory device.