JPH0877714A - Pll device - Google Patents

Abstract

PURPOSE: To perform an always stable PLL operation by inputting a produced pseudo phase difference signal to LPF and obtaining and adjusting an offset amount in a window comparator based on its output and a reference voltage so as to make this a minimum value. CONSTITUTION: An EFM signal 1 read from a CD and a PLCK signal 2 obtained by dividing the output frequency of a VCO circuit 6 by 2<n> by a frequency devider 7 are inputted to a phase comparing circuit 8 within a phase comparator 4 and phases there of are compared, a phase compared value is inputted to a charge pump 9 and outputted as a PDO (phase difference) signal 3. The PDO signal 3 is inputted to the VCO circuit 6 through LPF 5, producing a PLCK signal 2. The signal 2 is guided again from the frequency devider 7 into the phase comparator 4 so as to be a signal synchronized with the EFM signal 1. In this case, a wave form is rather flat and a phenomenon for giving an influence to the average voltage of the signal 3 appears as an offset against the reference voltage of the DC component of the output value of the LPF 5. AD/A converter 13 is operated so as to make an offset amount minimum by monitoring the output value of a comparator 12 with CPU and a PLL operation is stably performed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PLL (Phase Locked Loop) device.

[0002]

2. Description of the Related Art Conventionally, an EFM signal containing a clock component is read by reproducing a recording medium mounted in an optical pickup device, for example, a compact disc (CD), and a PLCK signal (bit clock signal) synchronized with the clock component is read. In order to obtain (1), a PLL device is used. FIG. 7 shows E read from a compact disc.
An example of the FM signal 1 is shown. This EFM signal 1 is 3T-1
During 1T (T: 1 clock), it randomly changes by an integral multiple of 1T. PL to EFM signal 1 having such a waveform
In order to synchronize the CK signal 2 as shown in FIG. 8, a circuit (phase comparator) for comparing the phases of these two signals 1 and 2 is required, and for this purpose, it is provided in the PLL device. The phase comparison of the two signals 1 and 2 is performed using the phase comparator, and the EFM signal 1 and the PLCK signal 2 are synchronized with each other.

FIGS. 9A to 9C show a general method for performing phase comparison using the phase comparator of the PLL device. A PDO signal 3 (phase difference signal) is created to indicate the phase difference between the EFM signal 1 and the PLCK signal 2. The PDO signal 3 has periods of H level and L level, and is in high impedance (Z) during the other periods.
Has become. In terms of specific numerical values, in the LSI, the H level is 5V, the L level is 0V, and the high impedance is set to 2.5V (considering pull-up resistance and pull-down resistance of the same constant external to the circuit). . Figure 9
(A) shows the case where the EFM signal 1 and the PLCK signal 2 are synchronized, and the lengths of the H level and the L level of the PDO signal 3 are equal. FIG. 9B shows P rather than EFM signal 1.
The case where the phase of the LCK signal 2 is advanced is shown, and the length of the H level of the PDO signal 3 at this time is shorter than that when the two signals 1 and 2 are synchronized. Figure 9 (c) is EFM
The case where the phase of the PLCK signal 2 is delayed from the signal 1 is shown, and the length of the H level of the PDO signal 3 at this time is longer than that when the two signals 1 and 2 are synchronized. Therefore, the PDO signal 3 indicating the phase difference between the EFM signal 1 and the PLCK signal 2 in this way is at the L level of a half cycle (0.5T) of the PLCK signal 2 and 0 of the PLCK signal 2 depending on the phase difference. H level that changes in 1 cycle (0 to 1T),
The high impedance period is set to 2.5 V by the pull-up resistor and the pull-down resistor.

When a DC component (DC component) is extracted from the PDO signal 3 output from such a phase comparator using an LPF (low-pass filter), it becomes 2.5 V when synchronized, and the PLCK signal When the phase of 2 advances, the voltage drops below 2.5V, and when the phase of the PLCK signal 2 lags, the voltage rises above 2.5V. Thus P
Since the H level of the DO signal 3 changes according to the phase difference,
The average voltage changes around 2.5 V depending on the phase difference. PDO signal 3 represented by this average voltage is set to P
By inputting to the control terminal of the VCO circuit (voltage controlled oscillator) that produces the LCK signal 2, the EFM signal 1
And PLCK signal 2 are synchronized. In addition, PLCK
The signal 2 is obtained by dividing the output value of the VCO circuit by the nth power of 2, and the duty ratio is 50%.

[0005]

[Problem to be Solved by the Invention] Phase comparator to LPF
The high impedance period of the PDO signal 3 which is output to is set to 2.5V by the pull-up resistor and the pull-down resistor, and the length of 1T of the EFM signal 1 reproduced from the CD is 115.7ns at the standard speed. ing. Therefore, the high impedance period of the PDO signal 3 is very short, and if a resistance value of several KΩ or more is used for the pull-up resistance and pull-down resistance, as shown in FIG. The change from 5V (high impedance), 0V (L level) to 2.5V (high impedance) becomes gentle, and in particular, the change from 5V to 2.5V changes to 2.5V. 0V period is entered before. In order to eliminate such a gradual phenomenon and make a steep waveform, the resistance values of the pull-up resistor and pull-down resistor should be lowered.
When the resistance value is lowered, the voltage at the H level is lower than 5V and the voltage at the L level is higher than 0V. As a result, the average voltage of the PDO signal 3 is affected and the phase is locked in the PLL operation. It is hard to peel off and easily comes off. The phenomenon of such out-of-phase is
As the rotation speed of the recording medium (CD) becomes twice as high as the standard speed, that is, four times as fast as the standard speed.

[0006]

According to a first aspect of the invention, the PFM obtained by dividing the EFM signal read from the recording medium and the output signal from the voltage controlled oscillator by a frequency divider is obtained.
Input the LCK signal to the phase comparator to perform phase comparison,
The direct current component of the phase difference signal obtained by this phase comparison is detected by a low pass filter, and the detected direct current component is input again to the voltage controlled oscillator, whereby the E
In a PLL device for generating a PLCK signal synchronized with an FM signal, a pseudo phase difference signal generating means for generating a pseudo phase difference signal similar to the phase difference signal is provided at an input stage of the low pass filter, and the generated pseudo phase difference is provided. An offset adjusting means for determining a difference between a direct current component obtained by inputting a signal to the low-pass filter and a reference voltage as an offset amount is provided, and an offset adjusting means for determining an offset adjusting value that minimizes the offset amount. It was connected to the low pass filter.

According to a second aspect of the present invention, in the first aspect of the invention, the rising edge and the falling edge of the EFM signal are extracted in the phase comparator to create an edge signal that holds the H level for a certain period of time. EFM edge extraction means, first flagging means for setting a flag by the output value of the EFM edge extraction means, PLCK level holding means for holding the current level of the PLCK signal by the output value of the EFM edge extraction means, and The falling edge extracting means for extracting the falling edge of the PLCK signal to create an edge signal, and the output value of the PLCK level holding means being at the H level and the first flag making means flagging the signal. Second flag forming means for setting a flag according to the output value of the falling edge extracting means and the EFM signal for one clock And a delay means to make DEFM signal by al, DEF created by the delay means
DEFM edge extraction means for extracting the rising and falling edges of the M signal to create an edge signal that holds the H level for a certain period of time, and a third flagging means for setting a flag according to the output value of this DEFM edge extraction means, There is provided signal switching means for switching the phase difference signal to the L level or the H level and outputting the phase difference signal according to the output value of the second flagging means and the output value of the third flagging means.

According to a third aspect of the present invention, in the second aspect of the invention, the PLCK signal is delayed by one clock, and D
A delay means for producing a PLCK signal is provided.

[0009]

In the invention described in claim 1, the actual PLL
At the time of adjusting the offset before starting the operation, the pseudo phase difference signal generated by the pseudo phase difference signal generating means is input to the low pass filter, the output value of the low pass filter and the reference voltage are sent to the window comparator, and this window comparator While monitoring the offset amount which is the output value, the offset adjusting means is operated to determine the offset adjustment value so that the offset amount becomes the minimum value. In this way, the offset adjustment value predetermined by the offset adjusting means is applied to the low-pass filter during the actual operation, thereby minimizing the offset or canceling the offset to stabilize the PLL operation.

According to the second aspect of the invention, since the EFM signal is input to the EFM edge extraction means, the EF signal is extracted.
An edge signal for maintaining the H level is created by extracting the rising and falling edges of the M signal, the current signal level of the PLCK signal is held by the PLCK level holding means by this edge signal, and the falling edge of the PLCK signal is extracted. An edge signal is created by being input to the means,
When the signal level of the PLCK level holding means is H level and the flag of the first flagging means is set at the time when this edge signal is created, the flag of the second flagging means is set, and the second flag forming means is set. When the flag of the means is set, the phase difference signal is set to the L level and output by the signal switching means, and by the EFM signal being input to the delaying means, the EFM signal is delayed by one clock. A DEFM signal is created and this DEFM signal is
An edge signal is created by inputting the signal to the DEFM edge extraction means, this edge signal is input to the third flagging means and is flagged, and a signal is output when the flag of this third flagging means is raised. The phase difference signal is set to H level by the switching means and output.

According to the third aspect of the invention, the DPCK is delayed by one clock for the PLCK signal by the delaying means.
By generating the LCK signal, the DPLCK signal is output to the outside instead of the PLCK signal.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described with reference to FIGS. 1 and 2 (corresponding to the invention of claim 1). The same names and reference numerals are used for the same parts as those in the conventional example (see FIGS. 7 to 10) described above.

FIG. 1 shows a circuit configuration in the PLL device. A phase comparator 4 to which the EFM signal 1 and the PLCK signal 2 read from the recording medium (here, the CD) is input is provided, and the phase comparator 4 outputs the PDO signal 3 (phase difference signal). An LPF 5 for detecting a DC component of the PDO signal 3 is connected to the output stage via a pull-up resistor R and a pull-down resistor R. This L
A VCO circuit 6 for producing a PLCK signal 2 is connected to the output stage of the PF 5, and a PLC is connected to the output stage of the VCO circuit 6.
A frequency divider 7 for dividing the K signal 2 by the nth power of 2 is connected. The PLCK signal 2 divided by the divider 7 is input to the phase comparator 4.

In the phase comparator 4, a phase comparison circuit 8 for comparing the phases of the input EFM signal 1 and PLCK signal 2, a charge pump 9 to which the phase compared signal is sent, and a PDO signal 3 are provided. 2 and a pseudo phase difference signal generating circuit 11 as a pseudo phase difference signal generating means for generating a pseudo PDO signal 10 (pseudo phase difference signal) as shown in FIG. Further, a comparator 12 (window comparator) is provided which compares the DC component of the PDO signal 3 which is the output value of the LPF 5 with the reference voltage Vo and detects the difference as an offset amount. Furthermore, LP
A D / A converter 13 as an offset adjusting unit for adjusting the offset of the LPF 5 is connected to the F5.

In such a configuration, the EFM signal 1 read from the CD and the PLCK signal 2 output from the VCO circuit 6 and obtained by dividing the frequency by 2 to the nth power of the frequency divider 7 are the phase comparator 4 The phase comparison is performed by being input to the phase comparison circuit 8 therein, and the phase comparison value is sent to the charge pump 9 and output as the PDO signal 3. This PD
The DC component of the O signal 3 is detected by the LPF 5,
The PLCK signal 2 is created by being sent to the VCO circuit 6. The PLCK signal 2 is guided again from the frequency divider 7 into the phase comparator 4 so that it becomes a signal synchronized with the EFM signal 1. In this case, as shown in FIG. 10, the phenomenon that the waveform becomes gentle and affects the average voltage of the PDO signal 3 appears as an offset with respect to the reference voltage of the DC component that is the output value of the LPF 5.

Therefore, the pseudo phase difference signal generation circuit 11, the comparator 12, and the D / A converter 13 operate so as to cancel the offset. First,
The connection between the phase comparison circuit 8 in the phase comparator 4 and the charge pump 9 is cut off, and the loop-shaped normal PLL operation (actual operation) is stopped. Then, the charge pump 9 is connected to the pseudo phase difference signal generating circuit 11, and the pseudo phase difference signal generating circuit 11 outputs the pseudo PDO signal 10 having a fixed pattern as shown in FIG. When the pseudo PDO signal 10 is output, since the same phase comparator 4 is used as when the PDO signal 3 is output, the same amount of offset as in the normal PLL operation is included in the output voltage of the LPF 5. Therefore, by comparing the output voltage of the LPF 5 and the reference voltage Vo with the comparator 12 which is a window comparator, the output value of the comparator 12 becomes H level when the output voltage is near the reference voltage Vo, and the output voltage becomes The output value of the comparator 12 is at the L level when the reference voltage Vo has a value that is separated from the reference voltage Vo in the + direction or the − direction by a certain amount or more. In this state, the CPU sends the data to be sent to the D / A converter 13 (waveform having a predetermined size), and outputs the output value of the comparator 12 to the CPU.
Check by port. At this time, while the H level is being input to the CPU port, the maximum value and the minimum value of the data from the D / A converter 13 are obtained. Therefore, it is possible to know the desired offset amount by obtaining the intermediate value. You can Thus, while monitoring the output value of the comparator 12 at the CPU port, the offset adjustment value is determined by operating the D / A converter 13 so that the offset amount becomes the minimum value.

Next, the offset adjustment value thus determined is added to the D / A converter 13 when the actual operation state of the normal PLL operation is set. As a result, the offset value can be completely canceled by the adjustment value, so that the average voltage of the PDO signal 3 is not affected, the phase is less likely to occur, and the PLL operation is performed stably. Can be made.

Next, a second embodiment of the present invention will be described with reference to FIGS.
(Corresponding to the invention of claim 2). The description of the same parts as those in the first embodiment is omitted, and the same reference numerals are used for the same parts.

The present embodiment relates to the structure of the phase comparison circuit 8 in the phase comparator 4. The EFM edge extraction circuit 14 as an EFM edge extraction means that extracts the rising and falling edges of the EFM signal 1 and holds the H level for a certain period of time to create an edge signal serves as a first flagging means that sets a flag. First flag circuit 15 (hereinafter referred to as flag 1)
And a PLCK level holding circuit 16 as a PLCK level holding means for holding the current level of the PLCK signal 2. These first flag circuits 15
The PLCK level holding circuit 16 and the PLCK level holding circuit 16 are connected to a second flag circuit 19 (hereinafter, referred to as flag 2) as a second flag forming unit that sets a flag through an AND circuit 18. The flag 2 and a third flag circuit 23 (hereinafter, referred to as flag 3) as a third flag forming means for setting a flag are used to extract the falling edge of the PLCK signal 2 to generate an edge signal. A falling edge extraction circuit 17 as an edge extraction means is connected.

Further, the EFM signal 1 is delayed by one clock to produce the DEFM signal 20, which is 1T as a delaying means.
The delay line circuit 21 is connected to a DEFM edge extraction circuit 22 as a DEFM edge extraction means that extracts the rising and falling edges of the DEFM signal 20 and holds the H level for a certain period of time to create an edge signal 27.
The DEFM edge extraction circuit 22 is connected to the flag 3. The flag 2 is connected to the switch 24a of the signal switching circuit 24 as a signal switching means for switching the PDO signal 3 to the L level or the H level and outputting the PDO signal 3, and the flag 3 is connected to the switch 24b of the signal switching circuit 24. It is connected to the.

In such a configuration, when the EFM signal 1 is input to the EFM edge extraction circuit 14, both the rising edge and the falling edge of the signal are extracted to maintain the H level state for a certain period of time therebetween. Edge signal 25
Is created. The edge signal 25 causes the current signal level of the PLCK signal 2 to change to the PLCK level holding circuit 16
It is held and output by. At the same time, the flag 1 is set by the edge signal 25. Further, the edge signal 26 is created by inputting the PLCK signal 2 to the falling edge extraction circuit 17, and at the time when the edge signal 26 is created, the signal level of the PLCK level holding circuit 16 is H level and the flag is set. 1
When the flag of 1 is set, the flag of flag 2 is set by the output of the AND circuit 18. When the flag 2 is set, the switch 24 of the signal switching circuit 24 is turned on.
a is switched and the PDO signal 3 is output while the PLCK signal 2 is being output as it is and is fixed at the L level.
Is output.

When the EFM signal 1 is input to the 1T delay line circuit 21, a DEFM signal 20 delayed by one clock from the EFM signal 1 is created.
The edge signal 27 is created by inputting the FM signal 20 to the DEFM edge extraction circuit 22, and the flag 3 is set by this edge signal 27. When the flag 3 is set, the switch 24b of the signal switching circuit 24 is switched, and the PDO signal 3 is fixed at the H level and output. At this time, the flags 1 and 2 are cleared.

Further, when the edge signal 26 is output from the falling edge extraction circuit 17 to which the PLCK signal 2 is input, the flag 23 is cleared, and the flag 19 has already been cleared at this point, so the signal switching circuit The switches 24a and 24b of 24 are switched, and the PLCK signal 2 is output as it is as the PDO signal 3. Below, E again
The FM signal 1 is input to the EFM edge extraction circuit 14 and the edge signal 25 is created, so that the same operation is repeated.

As described above, the PDO signal 3 obtained from the phase comparison circuit 8 is represented as a signal of only L level and H level, and is output as a signal in which no high impedance period exists. Also, by sending the EFM signal 1 to the 1T delay line circuit 21, the EFM signal 1
On the other hand, the DEFM signal 20 delayed by 1T is created, and the PLCK signal 2 is also synchronized with the DEFM signal 20. As a result, the PLL operation can be performed in a stable state even when the recording medium from which the EFM signal 1 is read becomes double speed or quad speed.

Next, the PDO signal 3 which is output from the phase comparison circuit 8 and consists of only the L level and the H level in which the high impedance period does not exist depends on the magnitude of the phase shift with respect to the EFM signal 1 and the L level and the H level. How the length of the variable changes will be described with reference to FIG. First, preconditions (a) to (e) for changing the lengths of the L level and the H level will be described. When the level of the PLCK signal 2 at the change point (edge) of the EFM signal 1 is H level, the following conditions (a) to (c) are satisfied. (A) The PDO signal 3 outputs the L level until the change point of the DEFM signal 20 after the next fall of the PLCK signal 2. (B)
After the changing point of the DEFM signal 20, the H level is output after the changing point and until the first fall of the PLCK signal 2. (C) PLC under the above two conditions (a) and (b)
The K signal 2 is output as it is. When the level of the PLCK signal 2 at the change point (edge) of the EFM signal 1 is L level, the following conditions (d) and (e) are satisfied. (D) D
After the change point of the EFM signal 20, the H level is output after the change point and until the first fall of the PLCK signal 2. (E) The PLCK signal 2 is output as it is after the condition (d).

Based on the above-described preconditions, how the length of the L level and the length of the H level change depending on the magnitude of the phase shift will be described with reference to FIGS. In FIG. 4, the DEFM signal 20 is a signal delayed by 1T from the EFM signal 1, and the PLC
The K signal 2 is also synchronized with its DEFM signal 20. FIG.
Shows the case where the phase of the PLCK signal 2 is slightly advanced from the phase of the EFM signal 1. The sum of the L level (period A) and the H level (period B) in the PDO signal is 1T,
The L level is slightly wider than the H level. As a result, the level of the average voltage of the PDO signal 3 is slightly biased to the L level side. Next, FIG. 4 shows a case where the phase of the PLCK signal 2 is slightly delayed with respect to the EFM signal 1. The sum of the L level (period A) and the H level (period B) in the PDO signal is 1T, and the L level is slightly narrower than the H level. As a result, the level of the average voltage of the PDO signal 3 is slightly biased to the H level side. Next, FIG. 4 shows a case where the phase of the PLCK signal 2 is considerably advanced with respect to the EFM signal 1. The sum of the L level (period A) and the H level (period B) in the PDO signal is 1T,
The L level is considerably wider than the H level. As a result, the level of the average voltage of the PDO signal 3 is considerably biased to the L level side. Next, FIG. 4 shows a case where the phase of the PLCK signal 2 is considerably delayed with respect to the EFM signal 1. P
L level (period A) and H level (period B) in the DO signal
Is 1T, and the L level is considerably narrower than the H level. As a result, the level of the average voltage of the PDO signal 3 is considerably biased to the H level side. In addition, FIG.
In the examples 1 to 3, the sum of the lengths of the L level and the H level in the PDO signal 3 is set to 1T, but the length of the signal is not limited to 1T. FIG. 5 shows changes in the lengths of the H level and the L level with respect to the phase difference in the PDO signal 3 as a phase difference output that does not include high impedance. In this way, the lengths of the H level and the L level can be changed within the range of + 2T to -2T with respect to the phase difference of -180 ° to + 180 °.

Next, a third embodiment of the present invention will be described with reference to FIG. 6 (corresponding to the invention of claim 3). The description of the same parts as those of the first and second embodiments will be omitted, and the same parts will be denoted by the same reference numerals.

This embodiment relates to the phase comparison circuit 8 in the phase comparator 4 in the first embodiment, and is related to the second embodiment (FIG. 3).
The configuration is different from that of the phase comparison circuit 8 (see (1)). In the phase comparison circuit 8 of FIG. 6, a 1T delay line circuit 29 is provided as a delaying unit that delays the PLCK signal 2 by one clock (T) to generate the DPLCK signal 28. The 1T delay line circuit 29 and the 1T delay line circuit 21 are the same delay line IC 30.
Is configured as

In this case, the EFM signal 1 is input to the 1T delay line circuit 21 of the delay line IC 30 so that the EFM signal 1 is delayed by 1T with respect to the EFM signal 1.
The EFM signal 20 is generated, while the PLCK signal 2 is input to the 1T delay line circuit 29 in the same IC to generate the DPLCK signal 28 delayed by 1T from the PLCK signal 2. Then, by outputting the DPLCK signal 28 instead of the PLCK signal 2 to the external circuit, when the DEFM signal 20 is synchronized with the PLCK signal 2, the PLCK signal 2 and E
The stationary phase difference generated between the FM signal 1 and the FM signal 1 can be eliminated, whereby the EFM signal 1 and the DPLCK signal 28 can be perfectly synchronized, and the PLL operation can be further stabilized.

[0030]

According to the first aspect of the present invention, the pseudo phase difference signal generating means generates a pseudo phase difference signal similar to the phase difference signal, and the pseudo phase difference signal is input to the low-pass filter, and its output value and the reference value. The voltage and the voltage are sent to the window comparator to obtain the offset amount, and the offset adjusting means is adjusted so that the offset amount becomes the minimum value, so that the offset adjusting value is determined in actual operation. By applying the adjusted offset adjustment value to the low-pass filter, it is possible to minimize or cancel the offset amount appearing in the output value of the low-pass filter, thereby preventing the phase deviation from occurring and performing stable PLL operation. It is possible to provide a highly reliable PLL device.

According to a second aspect of the present invention, the signal level of the PLCK level holding means is H when the PLCK signal is input to the falling edge extraction means and the edge signal is created.
At the level and when the flag of the first flag forming means is set, the flag of the second flag forming means is set and the phase difference signal is set to the L level by the signal switching means and output, and the EFM signal is delayed. When the edge signal created by being input from the means to the DEFM edge extracting means is input to the third flag forming means and is flagged, the phase difference signal is set to the H level and output by the signal switching means. Therefore, the phase difference signal output from the phase comparator does not include the high impedance state L
It can be created only from the level or H level state, and thus the PLL operation can be performed in a more stable state even when the recording medium from which the EFM signal is read becomes double speed or quad speed.

According to the third aspect of the present invention, the delaying means delays the PLCK signal by one clock to generate the DPLCK signal. Therefore, the DPCK signal is replaced by the DPCK signal.
By outputting the LCK signal, the steady phase difference between the DPLCK signal and the EFM signal can be eliminated, and the synchronization state can be further improved.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a circuit configuration of a PLL device that is a first embodiment of the present invention.

FIG. 2 is a waveform diagram showing a pseudo phase difference signal.

FIG. 3 is a circuit diagram showing a circuit configuration in a phase comparator which is a second embodiment of the present invention.

FIG. 4 is a waveform diagram showing how the phase difference signal changes depending on the magnitude of the phase difference shift with respect to the EFM signal.

FIG. 5 is a characteristic diagram showing a change in length of H and L levels with respect to a phase difference.

FIG. 6 is a circuit diagram showing a circuit configuration in a phase comparator which is a third embodiment of the present invention.

FIG. 7 is a waveform diagram showing a conventional EFM signal.

FIG. 8 is a waveform diagram showing changes in the phase difference signal with respect to the EFM signal.

FIG. 9A is a waveform diagram showing a state in which the EFM signal and the phase difference signal are synchronized, and FIG. 9B is a PLC from the EFM signal.
FIG. 6C is a waveform diagram showing that the phase of the K signal is advanced, and FIG. 7C is a waveform diagram showing that the phase of the PLCK signal is delayed from the EFM signal.

FIG. 10 is a waveform diagram showing how the waveform of the phase difference signal becomes gentle and deformed.

[Explanation of symbols]

 1 EFM Signal 2 PLCK Signal 3 Phase Difference Signal 4 Phase Comparator 5 Low Pass Filter 6 Voltage Controlled Oscillator 7 Frequency Divider 10 Pseudo Phase Difference Signal 11 Pseudo Phase Difference Signal Generating Means 12 Window Comparator 13 Offset Adjusting Means 14 EFM Edge Extracting Means 15 First flag forming means 16 PLCK level holding means 17 Falling edge extracting means 19 Second flag forming means 20 DEFM signal 21 Delaying means 22 DEFM edge extracting means 23 Third flag forming means 24 Signal switching means 25-27 Edge signal 28 DEFM signal 29 delaying means Vo reference voltage

Claims (3)

[Claims] 1. An EFM signal read from a recording medium and a PLCK signal obtained by dividing an output signal from a voltage controlled oscillator by a frequency divider are input to a phase comparator to perform phase comparison, A PLL device that detects a DC component of a phase difference signal obtained by this phase comparison by a low-pass filter, and inputs the detected DC component to the voltage controlled oscillator again to generate a PLCK signal synchronized with the EFM signal. In, the pseudo phase difference signal generating means for generating a pseudo phase difference signal similar to the phase difference signal is provided in the input stage of the low pass filter, and the generated pseudo phase difference signal is input to the low pass filter. An offset is provided so that the difference between the DC component and the reference voltage is detected as an offset amount, and the offset amount is minimized. A PLL device in which an offset adjusting means for determining an adjustment value is connected to the low-pass filter. 2. An EFM edge extraction means for extracting rising and falling edges of an EFM signal and holding an H level for a certain period of time to create an edge signal in a phase comparator, and the EFM edge extracting means.
First flagging means for setting a flag by the output value of the FM edge extraction means, PLCK level holding means for holding the current level of the PLCK signal by the output value of the EFM edge extraction means, and the falling edge of the PLCK signal. The output value of the falling edge extraction means for extracting the edge signal and the output value of the PLCK level holding means is H.
At the level and when the flag is set by the first flag forming means, a second flag forming means for setting a flag by the output value of the falling edge extracting means and a DEFM signal by delaying the EFM signal by one clock Delaying means and DEFM created by this delaying means
Extract the rising and falling edges of the signal for a certain time H
DEFM edge extracting means for holding a level and creating an edge signal, third flag making means for setting a flag by the output value of the DEFM edge extracting means, output value of the second flag making means and the third flag making means 2. The PLL device according to claim 1, further comprising signal switching means for switching the phase difference signal to an L level or an H level and outputting the phase difference signal according to the output value of the. 3. The PLCK signal is delayed by one clock for D
3. The PLL device according to claim 2, further comprising delaying means for generating a PLCK signal.