JPH0877141A - Vector data processor - Google Patents

Abstract

PURPOSE: To improve the throughput by improving the request processing efficiency of a vector data processor. CONSTITUTION: A constitution example of the vector data processor corresponding to a 4B odd skip load/store instruction is shown, and this processor is provided with an operation part 1, a network part 5, and a memory part 9, and the operation part 1 includes an instruction recognition circuit 2, a network control circuit 3, and a vector operation circuit 4, and the network part 5 includes a contention arbitrating circuit 6, a buffer circuit 7, and a crossbar circuit 8. When each input port is held because of the occurrence of port contention, all input ports are held in the case of a normal instruction, but only input ports which are not processed as the result of contention are held in the case of a 4B odd skip vector instruction. Thus, port contention for the 4B odd skip vector instruction is reduced to improve the throughput.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a vector data processing device, and more particularly to a vector processing device which performs request processing in response to vector load / store instructions.

[0002]

2. Description of the Related Art In recent years, in a vector data processing device of an information processing device, in order to process a large amount of data between a main memory and a register or an arithmetic unit at high speed, a plurality of data are simultaneously processed at the same timing. By continuously supplying the data to the network unit, the speed of information processing is increased.

The configuration of an example of a conventional vector data processing device is shown in FIG. This conventional example is an example of a vector processing device corresponding to a 4B (when N = 4) odd-numbered jump load / store instruction, and as shown in FIG. 5, an operation including an instruction recognition circuit 2 and a vector operation circuit 4. Network section 5 including section 1, contention arbitration circuit 6, buffer circuit 7 including a buffer receiving register, and crossbar circuit 8
And a memory unit 9.

In FIG. 5, a predetermined instruction code 100 is analyzed in the instruction recognition circuit 2, and a vector operation execution instruction 101 corresponding to the vector instruction recognized by the analysis is output and input to the vector operation circuit 4. To be done. The vector operation circuit 4 receives the vector operation execution instruction 101 input from the instruction recognition circuit 2 and executes a predetermined vector operation. This conventional example is an example of the vector processing device corresponding to the 4B continuous load / store instruction and the 4B odd skip load / store instruction as described above, and these instructions are vector instructions. Corresponding to this, the vector operation circuit 4 is provided with four output ports. When the vector operation execution instruction 101 is received and the vector instruction is executed, an address and an address are output from these four output ports. The request 103, which is formed as one element by forming a pair with the operation result data, is sequentially issued and input to the input port of the buffer circuit 7.

When the 4B consecutive store instruction is recognized in the instruction recognition circuit 2, the vector recognition execution instruction 1 corresponding to the 4 byte consecutive store instruction is issued from the instruction recognition circuit 2.
01 is output and input to the vector operation circuit 4.
In the vector operation circuit 4, the vector operation execution instruction 101 is received, the address is determined from the base address and the distance included in the instruction, and the data to be stored and the address are paired and formed as one element. A request is generated. In this case, since the vector operation execution instruction 101 is an execution instruction corresponding to the 4B continuous store instruction, the distance of the instruction is 4B (4B * 1), and the destination of the request is continuously arranged. It is a command to be done. When the vector operation execution instruction 101 is an execution instruction corresponding to a 4B odd skip instruction, the instruction has a distance of 4B (4B * 3), and the destination of the request is arranged in an odd jump. Becomes In this prior art example, since the vector operation circuit 4 is provided with four output ports, the vector operation circuit 4 sequentially outputs four request 103 as one set, respectively. It is input to the buffer circuit 7.

The buffer circuit 7 is a buffer buffer that temporarily holds the request input from the vector operation circuit 4 in the buffer receiving register when there is an unprocessed request. 10
3 is element 0, according to the order through the buffer,
Each of the four elements, element 1, element 2 and element 4, is stored in the register in order. Then, in response to the input of the request 103, the request address 104 in the front row is output and input to the contention arbitration circuit 6.
At the time when the request stored in the buffer receiving register of the buffer circuit 7 becomes full, the hold signal 106 is output and input to the vector operation circuit 4,
The hold signal 106 temporarily stops the output of the request 103 from the vector operation circuit 4. On the other hand, the contention arbitration circuit 6 receives the request address 104 in the front row input from the buffer circuit 7, and checks the contention state of the request 103 based on the address. When there is contention between the requests, the hold signal 105 output to the buffer circuit 7 is turned on, and when there is no contention, it is turned off. The select signal 107 is output from the competitive arbitration circuit 6 and input to the crossbar circuit 8.
In the crossbar circuit 8, in response to the select signal 107 input from the contention arbitration circuit 6, the request 108 input from the buffer receiving register of the buffer circuit 7 is appropriately selected and output, and input to the memory unit 9. In the memory unit 9, the request 8 input from the crossbar circuit 8 is classified into an address and data, and data corresponding to the designated address is stored. In this conventional example, for each input of four elements,
Substantially, the number of elements processed and output to the memory unit 9 is only two elements, which means ½ of the maximum throughput.

Next, FIGS. 6 (a), 6 (b), 6 (c),
(D) and (e) and FIGS. 7 (a), (b), (c),
With reference to (d) and (e), the operation of this prior art example will be described.

FIG. 6 is an explanatory diagram of a request processing operation at the time of a 4B odd jump (4B * 1 jump) vector instruction in the conventional example. A, B, C and D in FIG. 6 (a)
Indicates a memory port of the memory unit 9, and each memory port is divided into an upper (U) and a lower (L). The numbers circled under these memory ports indicate the request arrival location and the request issuing order at the time of the 4B vector instruction of the distance "4B". FIG. 6B shows the 1T state of the buffer and the register when the request is issued in this order. In the request processing in the normal vector instruction, the request input to the buffer is output to the register in the order. The numbers and letters in the boxes indicate the request issuing sequence and the destination memory port, respectively, as described above. In the 1T, the two requests of 1A and 3B surrounded by ◯ in the four registers are processed, but the two requests of 2A and 4B are not processed, so these two ports are processed. The hold signal is turned on, the hold signals are ORed, and the hold signals for all the input ports of the buffer and the register are turned on (hold all processing). Therefore, in the 2T of FIG. 6C, only the remaining two requests 2A and 4B out of the four registers are processed. At this time, since there is no competition in the request, the hold signal is turned off. Figure 6 (d)
In the 3T, the hold signal is released, so that a request is output from each buffer to the register, and two requests are processed as a result of the conflict check. The hold signals for all buffers and registers turn on again because the two requests were lost due to contention. At the 4Tth shown in FIG. 6E, the remaining two requests are processed. After that, the operation from the 1T to the 4T is repeated. At the time of this 4B odd jump (4B * 1 jump) vector instruction, for each input of 4 elements at each timing,
The output is 2 elements each, which is 1 of the maximum throughput.
It is equivalent to / 2.

FIG. 7 is an explanatory diagram of a request processing operation at the time of issuing a 4B odd jump (4B * 3 jump) load / store instruction in the conventional example. In FIG. 7A, when this instruction is issued, the order of requests sent to the four memory ports A, B, C and D is as follows:
,,,, ... are shown. In the arithmetic unit 1, at the time of the 4B odd skip instruction, the request 1A, 2B and 3D is generated at the 1T shown in FIG. 7A.
However, since the request 4A lost the competition, the hold signals for all the buffers are turned on (HoldAll processing). At the 2T shown in FIG. 7C, since no new request is sent from the buffer, only the request 4A left in the register is processed. Next, at the 3T shown in FIG. 7D, a new request is sent from each buffer and processed, and as a result, the request 8C loses contention and is not processed. It turns on. At the 4Tth shown in FIG. 7E, only the remaining 8C is processed. After that, the operation pattern is the same as that of the first to fourth operations, and the processing is repeated. It can be seen that two requests are processed at each timing by averaging the above first to fourth Ts. This means that the throughput in this conventional example corresponds to 1/2 of the maximum throughput in the configuration of this conventional example.

[0010]

In the above-described conventional vector data processing device, the ON / OFF state of the hold signal input to the buffer circuit from the contention arbitration circuit determines the request address of the front row input from the buffer circuit. Therefore, the throughput is lower than the maximum value because the contention state of the request is controlled only by the judgment method that checks based on the relevant address, and the access time to the main memory of the vector load and store instructions is reduced. However, there is a drawback in that the processing speed increases and the processing speed significantly decreases.

[0011]

A vector data processing apparatus according to the present invention has at least one arithmetic unit for performing vector arithmetic and a plurality of banks each having 2NB as a minimum request unit, and performs simultaneous parallel processing. It is possible to perform data transfer in units of 2 NB in parallel between at least one main storage unit configured by a memory module having a plurality of ports capable of performing the above operations, and the arithmetic unit and the main storage unit. In a vector processing device including a possible network unit, the arithmetic unit analyzes a predetermined instruction code and outputs a vector operation execution instruction corresponding to the recognized vector instruction, and an instruction to output the vector instruction. Receiving the request corresponding to each output port by executing the predetermined vector operation in response to the recognition circuit and the vector operation execution instruction. And a network control circuit that receives the vector instruction, encodes the vector instruction and temporarily holds the vector instruction, and outputs a network control signal at a predetermined timing. A network unit receives a request from each port output from the vector operation circuit, temporarily stores a buffer circuit in a register, and inputs the network control signal, and through the network control signal, the vector While recognizing the request format of each port output from the arithmetic circuit,
When the request contention state in the register is detected by the request address information sent from the register in the buffer circuit, and the request format is used as the selection control criterion, the input port corresponding to the element lost in the contention and the occurrence of the contention , A request for each port output from the buffer circuit is input, a select signal output from the contention arbitration circuit is received, and the request of each port is requested by the select signal. And a crossbar circuit for outputting to the corresponding input port of the main memory section.

The contention arbitration circuit receives the address information corresponding to each port output from the register of the buffer circuit, detects the contention state of the request, and outputs the select signal to the crossbar circuit. In addition, an arbiter that outputs a hold signal corresponding to each port and a network control signal input from the network control circuit are received, and the request of each port output from the vector operation circuit via the network control signal. Upon receiving the NB odd-numbered jump instruction recognition circuit which recognizes the format and outputs the switching control signal as ON when the NB odd-numbered jump instruction format is recognized, and the hold signal corresponding to each port output from the arbiter, A logical sum circuit that takes the logical sum of these and outputs it, and the output from the arbiter The hold signal corresponding to each port and the logical sum output of the logical sum circuit are input, the hold signal corresponding to a predetermined port controlled by the switching control signal is selected, and the corresponding hold signal in the buffer circuit is selected. You may comprise with the select output to a register.

[0013]

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. In this embodiment, as in the case of the above-mentioned conventional example, N
2 is an example of a vector data processing device corresponding to a 4B odd jump load / store instruction corresponding to the case of = 4, and includes an instruction recognition circuit 2, a network control circuit 3 and a vector operation circuit 4 as shown in FIG. The arithmetic unit 1, a network unit 5 including a competitive arbitration circuit 6, a buffer circuit 7 and a crossbar circuit 8, and a memory unit 9 are provided.

In FIG. 1, a predetermined instruction code 100 is analyzed in the instruction recognition circuit 2, and a vector operation execution instruction 101 corresponding to the recognized vector instruction is output and input to the vector operation circuit 4. , The vector command is input to the network control circuit 3. The vector operation circuit 4 receives the vector operation execution instruction 101 output from the instruction recognition circuit 2 and executes a predetermined vector operation. In this embodiment,
The 4B continuous load / store instruction and the 4B odd skip load / store instruction are vector instructions, and correspondingly,
The vector operation circuit 4 is provided with four output ports corresponding to the element 0, the element 1, the element 2 and the element 3, respectively. When the vector operation execution instruction 101 is received and the vector instruction is executed, From these four output ports, corresponding to these four elements, four request 103, each of which is formed by combining an address and data of the operation result, are issued in order and output to the buffer circuit 7. To be done. On the other hand, in the network control circuit 3, the command input from the command recognition circuit 2 is coded and temporarily stored. Then, at the timing when the request 103 is input from the vector operation circuit 4 to the buffer circuit 7, the instruction code, which is the generation source of the request 103, changes to the network control signal 102.
And is input to the competitive arbitration circuit 6. In addition,
In the following, the operation when the instruction recognition circuit 2 recognizes a 4B continuous store instruction as a vector instruction will be described.

When the 4B consecutive store instruction is recognized by the instruction recognition circuit 2, the instruction recognition circuit 2 outputs 4B.
Vector operation execution instruction 101 corresponding to continuous store instruction
Is output and input to the vector operation circuit 4. The vector operation circuit 4 receives the vector operation execution instruction 101, determines the address from the base address and the distance included in the instruction, and forms a pair with the data stored in the address to form one element. A request is generated. In this case, since the vector operation execution instruction 101 is an execution instruction corresponding to the 4B continuous store instruction, the distance of the instruction is 4B (4B * 1), and the destination of the request is continuously arranged. It is a command to be done. When the vector operation execution instruction 101 is an execution instruction corresponding to a 4B odd skip instruction, the instruction has a distance of 4B (4B * 3), and the destination of the request is arranged in an odd jump. Becomes As described above, since the vector operation circuit 4 is provided with four output ports, from the vector operation circuit 4, the request 103 of the four main parts corresponding to each output port is sequentially formed as a set. And is input to the buffer circuit 7. Further, in the network control circuit 3, the vector operation circuit 4 outputs the network control signal 102 including the information of the 4-byte continuous store instruction at the timing when the request 103 is first output and inputs it to the contention arbitration circuit 6. To be done.

The buffer circuit 7 is a buffer buffer for temporarily storing the request input from the vector operation circuit 4 in the buffer receiving register when there is an unprocessed request. 10
3 is stored in the register in order through the buffer for each of four elements 0, 1, 1, 2 and 4 according to the order. Then, in response to the input of the request 103, the request address 104 in the front row of each element is output from the register and input to the contention arbitration circuit 6. This buffer circuit 7
When the request stored in the register is full, the hold signal 106 is output and input to the vector operation circuit 4, and the hold signal 106 stops the output of the request 103 from the vector operation circuit 4. It On the other hand, in the contention arbitration circuit 6, the contention state of the request 103 is checked based on the address 104 of the request in the front row input from the buffer circuit 7. If there is a conflict, a select signal 107 that operates so that the request corresponding to each element is output is output according to a predetermined priority order, and is output to the crossbar circuit 8 and the network control circuit 3 With reference to the input network control signal 102, the hold signal corresponding to the request that was not output from the crossbar circuit 8 due to competition is turned on and output, and at the same time, the buffer circuit in which the processed request exists Register 7 is cleared. Of course, if there is no competition between the requests,
The hold signal 105 output to the buffer circuit 7 is off and not output. In this case, an important point as a feature of the present invention is that the ON / OFF of the hold signal 105 output to the buffer circuit 7 in the contention arbitration circuit 6 determines the contention check by the request address 104 in the front row. In addition, it is controlled by the information of the instruction code, which is the generation source of the request 103, which is recognized by the network control signal 102 from the network control circuit 3. In the crossbar circuit 8,
Upon receiving the select signal 107 input from the contention arbitration circuit 6, the request 108 for each of the four elements of the element 0, the element 1, the element 2, and the element 4 input from the register of the buffer circuit 7 is appropriately selected and output, It is input to the memory unit 9. In the memory unit 9, the request 8 input from the crossbar circuit 8 is classified into an address and data, and data corresponding to the designated address is stored for each main part.

FIG. 2 is a block diagram showing the configuration of an embodiment of the contention arbitration circuit 6 described above. As shown in FIG. 2, in this embodiment, the arbiter 10 and the OR circuit 11 are used.
And a selector 12 and a 4B odd skip instruction recognition circuit 13. Addresses 104 of the four front row request requests corresponding to the element 0, the element 1, the element 2, and the element 3 output from the buffer circuit 7 shown in FIG. 1 are input to the arbiter 10. In arbiter 10, the address 10 of the front row request
4, the contention state of the request 103 is checked, and if there is a contention state, a select signal that operates so that the request corresponding to each element is output to the memory unit 9 according to a predetermined priority order. 107 is output and sent to the crossbar circuit 8. Also, arbiter 1
From 0, the output line of the hold signal corresponding to each element is
The hold signals output from the arbiter 10 are connected to the logical sum circuit 11 and the selector 12, respectively, and the logical sum is taken in the logical sum circuit 11, and the logical sum output is used as a hold signal corresponding to the main part of the selector 12.
Is input to Further, the hold signal corresponding to each main part output from the arbiter 10 is directly input to the selector 12. On the other hand, the network control signal 102 input from the network control circuit 3 is input to the 4B odd skip instruction recognition circuit 13, and the format of the request issued from the vector operation circuit 4 via the network control signal 102 is 4B. When it is recognized that it corresponds to an odd-number jump instruction, the network control signal 102 input from the network control circuit 3 to the contention arbitration circuit 6
The selection control signal 109 output from the 4B odd-numbered jump instruction recognition circuit 13 is turned on via. Selector 12
, The OR output and selection control signal 109
When both are turned on, the hold signal 105 corresponding to each main part is output for the first time and sent to the buffer circuit 7.

Next, FIGS. 3 (a), (b), (c),
(D) and (e) and FIGS. 4 (a), (b), (c),
With reference to (d) and (e), the operation of this embodiment will be described in a delayed manner.

FIG. 3 is an explanatory diagram of a request processing operation at the time of a 4B odd jump (4B * 1 jump) vector instruction in this embodiment. A, B, C and D in FIG.
Indicates a memory port of the memory unit 9, and each memory port is divided into an upper (U) and a lower (L). The numbers circled under these memory ports indicate the request arrival location and the request issuing order at the time of the 4B vector instruction of the distance "4B". The state of the first T of the buffer and the register when the request is issued in this order is shown in FIG. The request processing in the normal vector instruction is the same as the conventional operation, but the 4B odd jump vector instruction is recognized in the instruction recognition circuit 2, and the Hold all processing to the Hold o processing are performed.
Switched to nly processing. At the 1T, as a result of the contention check for the four requests stored in the register, two requests surrounded by a circle are processed. At this time, a hold signal corresponding to an input port having a request that has lost competition is selected and output as a hold signal for each buffer and register. That is, only the hold signal for the buffer and the register of the input port having the request that has lost the competition at the 1T is turned on (Hold only process).

Next, in the 2T of FIG. 3C, the request is sent from the buffers of the input port # 0 and the input port # 2 whose hold signals were not turned on to the register, and a total of four requests are generated. Conflict checked and processed. At this time, since the four requests are aimed at different memory ports, no conflict occurs, and the hold signals for the buffers and registers of the respective input ports also remain off. Then Fig. 3
At the 3T of (d), requests are sent from the buffers of all the input ports to the registers and a conflict check is performed, but since the four requests are aimed at different memory ports, conflict does not occur, and all The request is processed. This is the same for the 4T and subsequent figures in FIG. 3 (e). As is clear from the comparison between FIG. 3 of the present embodiment and FIG. 6 of the conventional example, it is understood that the request processing according to the present embodiment can perform the request processing with twice the efficiency of the conventional example.

4 (a), (b), (c), (d) and (e) show 4B odd number jumps (4B *) in this embodiment.
FIG. 9 is an operation explanatory diagram of request processing when a load / store instruction is issued. In FIG. 4A, when this instruction is issued, the order of requests sent to the four memory ports A, B, C and D is as follows:
,,, ... are shown. In the arithmetic unit 1, when a 4B odd-numbered jump instruction is issued, the request is transmitted in the order of input port # 0, input port # 1, input port # 2, input port # 3, input port # 0, .... FIG.
(B), (c), (d) and (e) show the request indicating the order of sending in this order and the memory port of the destination, and in 1T of FIG. 4 (b). Shows that the transmitted request is stored in the buffer and the register. In FIG. 4B, the three requests 1A, 2B, and 3D surrounded by ◯ are processed, and the hold signal is turned on only for the buffer # 3 in which the request 4A that has lost the competition exists. Hold Only treatment). To this end, FIG.
At the 2T shown in (c), the next request is sent to the register from the three buffers whose hold signals have been turned off, and as a result of the conflict check, all requests are processed. At the 3T in FIG. 7D, the next request is sent from the four buffers to the register, but all the requests are processed without conflict. Even after the 4th T in the figure (e), competition does not occur, and all four requests are processed. This is the maximum throughput in the configuration of the present embodiment, and the request can be processed with approximately twice the efficiency of the operation in the conventional example.

[0023]

As described above, the present invention detects an instruction such as a 4B odd jump load / store instruction that does not need to maintain the consistency between requests and outputs Ho.
By switching from ldall processing to Hold only processing, competition always occurs between request 4
Even when the B odd skip load / store instruction is issued, it is possible to prevent a decrease in request processing efficiency.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a block diagram showing an embodiment of a contention arbitration circuit according to the present embodiment.

FIG. 3 is an operation explanatory diagram at the time of a 4B continuous load / store instruction in the present embodiment.

FIG. 4 is an explanatory diagram of an operation at the time of a 4B odd-numbered jump load / store instruction in this embodiment.

FIG. 5 is a block diagram showing a configuration of a conventional example.

FIG. 6 is an operation explanatory diagram at the time of a 4B continuous load / store instruction in a conventional example.

FIG. 7 is an explanatory diagram of an operation at the time of a 4B odd-numbered jump load / store instruction in the conventional example.

[Explanation of symbols]

 1 arithmetic unit 2 instruction recognition circuit 3 network control circuit 4 vector arithmetic circuit 5 network unit 6 competitive arbitration circuit 7 buffer circuit 8 crossbar circuit 9 memory unit 10 arbiter 11 OR circuit 12 selector 13 4B odd skip instruction recognition circuit

Claims (2)

[Claims] 1. At least one arithmetic unit for performing vector arithmetic and 2N bytes (hereinafter abbreviated as 2NB; N).
Is an integer of 1 or more), and at least one main storage unit configured by a memory module having a plurality of banks in which data is a minimum request unit and having a plurality of ports capable of performing simultaneous parallel processing, In a vector data processing device comprising a network unit capable of parallelly transferring data in units of 2NB between the arithmetic unit and the main storage unit, the arithmetic unit analyzes a predetermined instruction code. And outputs a vector operation execution instruction corresponding to the recognized vector instruction, and an instruction recognition circuit that outputs the vector instruction, and executes a predetermined vector operation in response to the vector operation execution instruction, and outputs to each output port. A vector operation circuit which outputs a corresponding request, and which receives the vector instruction and encodes the vector instruction into a single And a network control circuit that outputs a network control signal at a predetermined timing, and the network unit receives the request of each port output from the vector operation circuit, and temporarily A buffer circuit that is stored in a register, and recognizes the request format of each port output from the vector operation circuit by inputting the network control signal and the network control signal. The request contention state in the register is detected by the request address information sent from the register, and the input format corresponding to the element lost in the contention and all the input ports when the contention occurs, using the request format as the selection control criterion. A competitive arbitration circuit that holds the The request of each port output from the logic circuit is input, the select signal output from the contention arbitration circuit is received, the request of each port is selected by the select signal, and the corresponding input port of the main memory unit is selected. And a crossbar circuit for outputting to a vector data processing device. 2. The contention arbitration circuit receives address information corresponding to each port output from a register of the buffer circuit, detects a contention state of a request, and outputs the select signal to the crossbar circuit. In addition, an arbiter that outputs a hold signal corresponding to each port and a network control signal input from the network control circuit, and a request for each port output from the vector operation circuit via the network control signal. NB which recognizes the format and outputs the switching control signal as ON at the time when the NB odd skip instruction format is recognized.
An odd jump instruction recognition circuit, a logical sum circuit for receiving a hold signal corresponding to each port output from the arbiter, taking a logical sum of them, and outputting the result, and a hold corresponding to each port output from the arbiter Input the signal and the logical sum output of the logical sum circuit,
2. The vector data processing device according to claim 1, further comprising a selector controlled by the switching control signal to select a hold signal corresponding to a predetermined port and output the selected hold signal to a corresponding register in the buffer circuit. .