JPH0877089A - Transmission and reception processor - Google Patents

Abstract

PURPOSE: To maintain the real-time property of transmission and reception processing and securely process sent and received frames even when they are asynchronous. CONSTITUTION: This transmission and reception processor is equipped with data input holding parts 11 and 12 which input and hold input data for transmission and reception, a data processing part 16 which is equipped with plural processing programs corresponding to plural block data generated by dividing the input data for transmission and reception and performs transmission and reception processing by selectively inputting the respective block data from the data input holding parts 11 and 12 and selectively executing the processing programs, decision parts 13 and 14 which decide respective frame head positions and block data head positions of the input data for transmission and reception, and a scheduler 15 which schedules the processing order of the data processing part 16 on the basis of the respective decided frame head positions and block data head positions of the input data for transmission and reception and specifies block data to be processed and processing programs to be executed to the data processing part 16 according to the scheduling order.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transmission / reception processing device for performing transmission processing and reception processing by one CPU, and more particularly to improvement of real-time property.

[0002]

2. Description of the Related Art As is well known, in digital communication such as satellite communication, full-duplex communication is performed, and in a communication device, a transmission / reception function is always operated by only one terminal. In such a communication device, generally one C
The PU processes the transmission / reception data. Conventional 1CP
FIG. 5 shows a data processing method of the transmission / reception processing device by U.

That is, as shown in FIG. 5A, the CPU serially performs a transmission process 2 and a reception process 4 in synchronization with a predetermined specific frame timing 1 by a single task.

Here, the transmission frame and the reception frame do not necessarily have the same phase, as in the case where the reception processing is performed using the clock reproduced from the reception signal. In consideration of such a case, in order to process the received data at the timing of the transmission processing, the received data 6 is stored in the phase correction memory as shown in FIG. part),
The reception data is extracted again at the processing timing of the transmission data 5 to perform the reception processing.

However, the conventional 1CP as described above
In the transmission / reception processing device by U, the reception data is delayed by a maximum of one frame, so that a processing delay occurs and the real-time property of the reception processing is lost. Furthermore, when the original frames of the transmission frame and the reception frame are different and asynchronous, when the transmission frame is faster,
The received data is not in time for the transmission processing and becomes discontinuous. On the contrary, when it is late, the received data overflows from the phase correction memory and is missed.

[0006]

As described above, in the transmission / reception processing device using the conventional 1CPU, processing delay occurs and the real-time property is lost, and when the transmission / reception frame is asynchronous, the reception data is unsuccessful. There are problems such as continuity and dropouts. The present invention has been made to solve the above problems, and has a small processing delay in reception processing and transmission processing, can maintain the real-time property of each processing, and even if transmission and reception frames are asynchronous. An object of the present invention is to provide a transmission / reception processing device that can reliably process reception data.

[0007]

In order to achieve the above object, the present invention provides a transmission / reception processing apparatus for serially processing a single task of input data for transmission and input data for reception whose frame data formats are known by a single CPU. A data input holding means for sequentially inputting and holding the transmission input data and the reception input data independently, and a plurality of blocks obtained by dividing the transmission input data and the reception input data based on respective data formats. Dividing processing means having a plurality of processing programs corresponding to data, and performing transmission processing and reception processing by selectively fetching transmission block data and reception block data from the data input holding means and selectively executing the processing program And the start position of each frame of the input data for transmission and the input data for reception A discriminating means for discriminating a block data head position, and scheduling of the processing order of the division processing means based on the frame head positions of the transmission input data and the reception input data discriminated by the means, and the block data head position. It is configured to include a scheduling control unit that specifies block data to be processed by the division processing unit and a processing program to be executed according to the scheduled order.

[0008]

In the transmission / reception processing device having the above configuration, the transmission input data and the reception input data are divided into block data based on the respective data formats in advance, and a processing program corresponding to each block data is prepared.
Input data for transmission and input data for reception are sequentially input and held independently, and each frame start position and block data start position of input data for transmission and input data for reception are determined, and division processing is performed based on the determined position. The order scheduling is performed, the block data to be processed is taken in according to the scheduled order, the corresponding processing program is executed, and the transmission processing and the reception processing are performed.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to FIGS. FIG. 1 shows a CPU internal functional configuration of a transmission / reception processing device according to the present invention. Reference numeral 11 is a transmission data input holding unit, and 12 is a reception data input holding unit. Each of the data input holding units 11 and 12 has a data capacity of, for example, one frame, and sequentially holds input data for transmission (hereinafter referred to as transmission data) and input data for reception (hereinafter referred to as reception data). , Output only the specified amount of data. Further, the frame signal of the input data is monitored, the head of the frame is discriminated from this frame signal, and the discrimination results are respectively transmitted clock counter 1
3. It has a function of sending to the reception clock counter 14.

The transmission clock counter 13 and the reception clock counter 14 respectively reset the count value at the frame head by the frame head discrimination output and count the transmission clock and the reception clock. Each count value is sent to the scheduler 15.

The scheduler 15 executes the main program, and determines the frame head and block data head of transmission data and reception data from the count values of the clock counters 13 and 14, and transmits and receives and processes which block data. This is scheduled, and the block data to be processed and the processing program to be executed are instructed to the data processing unit 16 according to the schedule.

The data processing section 16 is provided with a plurality of processing programs (subprograms for the main program) corresponding to each block data of the transmission data and the reception data in advance, and the transmission data input is performed according to an instruction from the scheduler 15. The designated block data is read from the holding unit 11 and the received data input holding unit 12, the designated processing program is executed, and the transmission process and the reception process are performed. The transmission output data subjected to the transmission processing is output through the reception data output unit 16, and the reception output data subjected to the reception processing is output through the transmission data output unit 17.

That is, in the transmission / reception processing device having the above-described configuration, the processing procedure is divided so that the transmission processing and the reception processing are executed in the order corresponding to the order of the respective data. Since the divided processing corresponds to the transmission / reception data, the scheduling is performed so that the reception processing is started at the data reception timing and the transmission processing is completed at the data transmission timing.

Specifically, the transmission clock and the reception clock are counted, and the division processing corresponding to the block data is selected from the distance from the frame head. The transmission process and the reception process are alternately performed, and a process is selected and scheduling is performed each time each division process is completed. If the input hold of the received data is not completed and the receiving process cannot be performed, select the sending process continuously, and if the clock on one side is stopped,
Continue to select one side.

According to the above processing, since the transmission processing and the reception processing are independently processed in accordance with the data input / output timing obtained from each clock, even if the phases of the transmission data and the reception data change, This does not affect the processing of 1), and the real-time processing performance close to that when the processing is performed individually by 2 CPUs is obtained. In addition, it is not necessary to correct the phase of data to a unique frame timing.

Further, the specific operation will be described with reference to FIGS. FIG. 2 is a timing chart showing the flow of basic data processing of the transmission processing and the reception processing in the above configuration. In FIG. 2, 1 is a transmission frame, 2 is a transmission process, 3 is a reception frame, 4 is a reception process, 5 is reception data, 6 is transmission data, and (a) is a timing relationship between the transmission process and the reception process. , (B) show the phase relationship between the transmission data and the reception data.

As shown in FIG. 2, the two tasks of the transmission processing 2 and the reception processing 4 are time-division multiplexed in small processing units (referred to as blocks here). Basically, the task switching is alternately performed such that when the transmission process is completed, the task is switched to the reception process.

FIG. 3 shows the software configuration of the above processing. Two tasks are divided into a plurality of subprograms,
The main program manages the schedule collectively. The subprogram to be executed next is selected after the processing of each subprogram is completed. The main program monitors the clock of the transmitted and received data and determines whether the sub program can be executed.

FIG. 4 shows a timing chart of processing for one frame. Here, each block of transmission data is indicated by 1 to 8, and each block of reception data is indicated by a to g.
The reception process cannot move to the process until the corresponding reception data is input. Therefore, in that case, the transmission process is continuously executed instead. Since the transmission process only needs to be completed before the data is transmitted, the gap of the reception process is filled.

For example, after the transmission process 3 is completed, the process should originally be switched to the reception process, but since the received data a is not completely input and held, the mode is switched to the transmission again and the transmission process 4 is executed. After that, when the input holding of the reception data a is completed, the task moves to the reception process and the reception process a is executed. At this time, the processing delay of the reception processing can be suppressed to about the time for executing the subprogram in the transmission processing, so that almost complete real-time processing becomes possible.

Therefore, the transmission / reception processing device having the above-mentioned configuration can process the transmission / reception frame signals without using the phase correction memory even if the transmission / reception frame signals do not have the same phase. Can also be reduced. In addition, asynchronous data transmission / reception processing can be performed by 1 CPU without discontinuous transmission of transmission data or omission of reception data.
Can be realized with, and the practical effect is extremely large.

It is needless to say that the present invention is not limited to the above embodiments, and that various modifications can be made without departing from the gist of the present invention.

[0023]

As described above in detail, according to the present invention,
Provided is a transmission / reception processing device capable of maintaining the real-time property of each process with little processing delay of the reception process and the transmission process, and reliably receiving the reception data even if the transmission and reception frames are asynchronous. can do.

[Brief description of drawings]

FIG. 1 is a block circuit diagram showing a configuration of an embodiment of a transmission / reception processing device according to the present invention.

FIG. 2 is a timing chart showing a flow of basic data processing of transmission processing and reception processing in the above configuration.

FIG. 3 is a diagram showing a software configuration of transmission / reception processing of the same embodiment.

FIG. 4 is a timing chart showing an example of processing for one frame in the embodiment.

FIG. 5 is a timing diagram for explaining a data processing method of a transmission / reception processing device using a conventional 1CPU.

[Explanation of symbols]

11 ... Transmission data input holding unit, 12 ... Reception data input holding unit, 13 ... Transmission clock counter, 14 ... Reception clock counter, 15 ... Scheduler, 16 ... Data processing unit, 17 ... Transmission data output unit, 18 ... Reception data output Department.

Claims (5)

[Claims] 1. A transmission / reception processing device for serially processing transmission input data and reception input data having a known data format in a frame by a single CPU by a single CPU, wherein the transmission input data and the reception input data are independent of each other. And a plurality of processing programs corresponding to a plurality of block data obtained by dividing the transmission input data and the reception input data based on the respective data formats. Division processing means for performing transmission processing and reception processing by selectively fetching transmission block data and reception block data from the means and selectively executing a processing program; and each frame of the transmission input data and the reception input data A discriminating means for discriminating the start position and the block data start position, and The division processing means schedules the processing order of the division processing means based on the frame start position of each of the transmission input data and the reception input data and the block data start position which are discriminated by the division processing means, and the division processing means is executed in accordance with the scheduled order. And a scheduling control means for designating a processing program to be executed. 2. The data position discriminating means discriminates each frame head position from each frame signal of the transmission input data and the reception input data, and the frame head position obtained by this means is used as a reference. To send clock,
The transmission / reception process according to claim 1, further comprising: a unit that counts the reception clock and detects that the count value has reached the number of bits at each block data start position to determine each block data start position. apparatus. 3. The scheduling control means basically schedules such that the transmission processing and the reception processing are alternately performed, monitors the data input holding means and the division processing means, and completes the processing of the transmission block data. 2. The transmission / reception processing apparatus according to claim 1, wherein the transmission block data is scheduled to be continuously processed when input reception of the reception block data is not completed. 4. The scheduling control means basically schedules the transmission processing and the reception processing alternately, and monitors the data position determination means and the division processing means to monitor the transmission clock and the reception clock. 3. The transmission / reception processing device according to claim 2, wherein when either one of the clocks stops, the block data of the other clock is scheduled to be continuously processed. 5. The transmission / reception processing device according to claim 1, wherein the transmission clock and the reception clock are asynchronous with each other.